1 // Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD 2 // 3 // Licensed under the Apache License, Version 2.0 (the "License"); 4 // you may not use this file except in compliance with the License. 5 // You may obtain a copy of the License at 6 // 7 // http://www.apache.org/licenses/LICENSE-2.0 8 // 9 // Unless required by applicable law or agreed to in writing, software 10 // distributed under the License is distributed on an "AS IS" BASIS, 11 // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 // See the License for the specific language governing permissions and 13 // limitations under the License. 14 15 #pragma once 16 17 #ifdef __cplusplus 18 extern "C" { 19 #endif 20 21 // ESP32-S3 has 1 GPIO peripheral 22 #define SOC_GPIO_PORT (1) 23 #define SOC_GPIO_PIN_COUNT (49) 24 25 // On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. 26 #define SOC_GPIO_SUPPORT_RTC_INDEPENDENT (1) 27 // Force hold is a new function of ESP32-S3 28 #define SOC_GPIO_SUPPORT_FORCE_HOLD (1) 29 30 // 0~48 except from 22~25 are valid 31 #define SOC_GPIO_VALID_GPIO_MASK (0x1FFFFFFFFFFFFULL & ~(0ULL | BIT22 | BIT23 | BIT24 | BIT25)) 32 // No GPIO is input only 33 #define SOC_GPIO_VALID_OUTPUT_GPIO_MASK (SOC_GPIO_VALID_GPIO_MASK) 34 35 // Support to configure slept status 36 #define SOC_GPIO_SUPPORT_SLP_SWITCH (1) 37 38 #ifdef __cplusplus 39 } 40 #endif 41
