1 /*
2 * Copyright (c) 2021 Telink Semiconductor
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include "analog.h"
8
9 #include <zephyr/device.h>
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/irq.h>
12 #include <zephyr/drivers/gpio/gpio_utils.h>
13 #include <zephyr/drivers/interrupt_controller/riscv_plic.h>
14
15
16 /* Driver dts compatibility: telink,b91_gpio */
17 #define DT_DRV_COMPAT telink_b91_gpio
18
19 /* Get GPIO instance */
20 #define GET_GPIO(dev) ((volatile struct gpio_b91_t *) \
21 ((const struct gpio_b91_config *)dev->config)->gpio_base)
22
23 /* Get GPIO IRQ number defined in dts */
24 #define GET_IRQ_NUM(dev) (((const struct gpio_b91_config *)dev->config)->irq_num)
25
26 /* Get GPIO IRQ priority defined in dts */
27 #define GET_IRQ_PRIORITY(dev) (((const struct gpio_b91_config *)dev->config)->irq_priority)
28
29 /* Get GPIO port number: port A - 0, port B - 1, ..., port F - 5 */
30 #define GET_PORT_NUM(gpio) ((uint8_t)(((uint32_t)gpio - DT_REG_ADDR(DT_NODELABEL(gpioa))) / \
31 DT_REG_SIZE(DT_NODELABEL(gpioa))))
32
33 /* Check that gpio is port C */
34 #define IS_PORT_C(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpioc)))
35
36 /* Check that gpio is port D */
37 #define IS_PORT_D(gpio) ((uint32_t)gpio == DT_REG_ADDR(DT_NODELABEL(gpiod)))
38
39 /* Check that 'inst' has only 1 interrupt selected in dts */
40 #define IS_INST_IRQ_EN(inst) (DT_NUM_IRQS(DT_DRV_INST(inst)) == 1)
41
42 /* Max pin number per port (pin 0..7) */
43 #define PIN_NUM_MAX ((uint8_t)7u)
44
45 /* IRQ Enable registers */
46 #define reg_irq_risc0_en(i) REG_ADDR8(0x140338 + i)
47 #define reg_irq_risc1_en(i) REG_ADDR8(0x140340 + i)
48
49 /* Pull-up/down resistors */
50 #define GPIO_PIN_UP_DOWN_FLOAT ((uint8_t)0u)
51 #define GPIO_PIN_PULLDOWN_100K ((uint8_t)2u)
52 #define GPIO_PIN_PULLUP_10K ((uint8_t)3u)
53
54 /* GPIO interrupt types */
55 #define INTR_RISING_EDGE ((uint8_t)0u)
56 #define INTR_FALLING_EDGE ((uint8_t)1u)
57 #define INTR_HIGH_LEVEL ((uint8_t)2u)
58 #define INTR_LOW_LEVEL ((uint8_t)3u)
59
60 /* Supported IRQ numbers */
61 #define IRQ_GPIO ((uint8_t)25u)
62 #define IRQ_GPIO2_RISC0 ((uint8_t)26u)
63 #define IRQ_GPIO2_RISC1 ((uint8_t)27u)
64
65
66 /* B91 GPIO registers structure */
67 struct gpio_b91_t {
68 uint8_t input; /* Input: read GPI input */
69 uint8_t ie; /* IE: input enable, high active. 1: enable, 0: disable */
70 uint8_t oen; /* OEN: output enable, low active. 0: enable, 1: disable */
71 uint8_t output; /* Output: configure GPIO output */
72 uint8_t polarity; /* Polarity: interrupt polarity: rising, falling */
73 uint8_t ds; /* DS: drive strength. 1: maximum (default), 0: minimal */
74 uint8_t actas_gpio; /* Act as GPIO: enable (1) or disable (0) GPIO function */
75 uint8_t irq_en; /* Act as GPIO: enable (1) or disable (0) GPIO function */
76 };
77
78 /* GPIO driver configuration structure */
79 struct gpio_b91_config {
80 struct gpio_driver_config common;
81 uint32_t gpio_base;
82 uint32_t irq_num;
83 uint8_t irq_priority;
84 void (*pirq_connect)(void);
85 };
86
87 /* GPIO driver data structure */
88 struct gpio_b91_data {
89 struct gpio_driver_data common; /* driver data */
90 sys_slist_t callbacks; /* list of callbacks */
91 };
92
93
94 /* Set IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_set(const struct device * dev,gpio_pin_t pin)95 static inline void gpiob_b91_irq_en_set(const struct device *dev, gpio_pin_t pin)
96 {
97 uint8_t irq = GET_IRQ_NUM(dev);
98
99 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
100
101 if (irq == IRQ_GPIO) {
102 BM_SET(gpio->irq_en, BIT(pin));
103 } else if (irq == IRQ_GPIO2_RISC0) {
104 BM_SET(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
105 } else if (irq == IRQ_GPIO2_RISC1) {
106 BM_SET(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
107 } else {
108 __ASSERT(false, "Not supported GPIO IRQ number.");
109 }
110 }
111
112 /* Clear IRQ Enable bit based on IRQ number */
gpiob_b91_irq_en_clr(const struct device * dev,gpio_pin_t pin)113 static inline void gpiob_b91_irq_en_clr(const struct device *dev, gpio_pin_t pin)
114 {
115 uint8_t irq = GET_IRQ_NUM(dev);
116 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
117
118 if (irq == IRQ_GPIO) {
119 BM_CLR(gpio->irq_en, BIT(pin));
120 } else if (irq == IRQ_GPIO2_RISC0) {
121 BM_CLR(reg_irq_risc0_en(GET_PORT_NUM(gpio)), BIT(pin));
122 } else if (irq == IRQ_GPIO2_RISC1) {
123 BM_CLR(reg_irq_risc1_en(GET_PORT_NUM(gpio)), BIT(pin));
124 }
125 }
126
127 /* Get IRQ Enable register value */
gpio_b91_irq_en_get(const struct device * dev)128 static inline uint8_t gpio_b91_irq_en_get(const struct device *dev)
129 {
130 uint8_t status = 0;
131 uint8_t irq = GET_IRQ_NUM(dev);
132 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
133
134 if (irq == IRQ_GPIO) {
135 status = gpio->irq_en;
136 } else if (irq == IRQ_GPIO2_RISC0) {
137 status = reg_irq_risc0_en(GET_PORT_NUM(gpio));
138 } else if (irq == IRQ_GPIO2_RISC1) {
139 status = reg_irq_risc1_en(GET_PORT_NUM(gpio));
140 }
141
142 return status;
143 }
144
145 /* Clear IRQ Status bit */
gpio_b91_irq_status_clr(uint8_t irq)146 static inline void gpio_b91_irq_status_clr(uint8_t irq)
147 {
148 gpio_irq_status_e status = 0;
149
150 if (irq == IRQ_GPIO) {
151 status = FLD_GPIO_IRQ_CLR;
152 } else if (irq == IRQ_GPIO2_RISC0) {
153 status = FLD_GPIO_IRQ_GPIO2RISC0_CLR;
154 } else if (irq == IRQ_GPIO2_RISC1) {
155 status = FLD_GPIO_IRQ_GPIO2RISC1_CLR;
156 }
157
158 reg_gpio_irq_clr = status;
159 }
160
161 /* Set pin's irq type */
gpio_b91_irq_set(const struct device * dev,gpio_pin_t pin,uint8_t trigger_type)162 void gpio_b91_irq_set(const struct device *dev, gpio_pin_t pin,
163 uint8_t trigger_type)
164 {
165 uint8_t irq_lvl = 0;
166 uint8_t irq_mask = 0;
167 uint8_t irq_num = GET_IRQ_NUM(dev);
168 uint8_t irq_prioriy = GET_IRQ_PRIORITY(dev);
169 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
170
171 /* Get level and mask based on IRQ number */
172 if (irq_num == IRQ_GPIO) {
173 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO;
174 irq_mask = FLD_GPIO_IRQ_MASK_GPIO;
175 } else if (irq_num == IRQ_GPIO2_RISC0) {
176 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC0;
177 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC0;
178 } else if (irq_num == IRQ_GPIO2_RISC1) {
179 irq_lvl = FLD_GPIO_IRQ_LVL_GPIO2RISC1;
180 irq_mask = FLD_GPIO_IRQ_MASK_GPIO2RISC1;
181 }
182
183 /* Set polarity and level */
184 switch (trigger_type) {
185 case INTR_RISING_EDGE:
186 BM_CLR(gpio->polarity, BIT(pin));
187 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
188 break;
189
190 case INTR_FALLING_EDGE:
191 BM_SET(gpio->polarity, BIT(pin));
192 BM_CLR(reg_gpio_irq_risc_mask, irq_lvl);
193 break;
194
195 case INTR_HIGH_LEVEL:
196 BM_CLR(gpio->polarity, BIT(pin));
197 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
198 break;
199
200 case INTR_LOW_LEVEL:
201 BM_SET(gpio->polarity, BIT(pin));
202 BM_SET(reg_gpio_irq_risc_mask, irq_lvl);
203 break;
204 }
205
206 if (irq_num == IRQ_GPIO) {
207 reg_gpio_irq_ctrl |= FLD_GPIO_CORE_INTERRUPT_EN;
208 }
209 gpio_b91_irq_status_clr(irq_num);
210 BM_SET(reg_gpio_irq_risc_mask, irq_mask);
211
212 /* Enable peripheral interrupt */
213 gpiob_b91_irq_en_set(dev, pin);
214
215 /* Enable PLIC interrupt */
216 riscv_plic_irq_enable(irq_num);
217 riscv_plic_set_priority(irq_num, irq_prioriy);
218 }
219
220 /* Set pin's pull-up/down resistor */
gpio_b91_up_down_res_set(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,uint8_t up_down_res)221 static void gpio_b91_up_down_res_set(volatile struct gpio_b91_t *gpio,
222 gpio_pin_t pin,
223 uint8_t up_down_res)
224 {
225 uint8_t val;
226 uint8_t mask;
227 uint8_t analog_reg;
228
229 pin = BIT(pin);
230 val = up_down_res & 0x03;
231 analog_reg = 0x0e + (GET_PORT_NUM(gpio) << 1) + ((pin & 0xf0) ? 1 : 0);
232
233 if (pin & 0x11) {
234 val = val << 0;
235 mask = 0xfc;
236 } else if (pin & 0x22) {
237 val = val << 2;
238 mask = 0xf3;
239 } else if (pin & 0x44) {
240 val = val << 4;
241 mask = 0xcf;
242 } else if (pin & 0x88) {
243 val = val << 6;
244 mask = 0x3f;
245 } else {
246 return;
247 }
248
249 analog_write_reg8(analog_reg, (analog_read_reg8(analog_reg) & mask) | val);
250 }
251
252 /* Config Pin pull-up / pull-down resistors */
gpio_b91_config_up_down_res(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)253 static void gpio_b91_config_up_down_res(volatile struct gpio_b91_t *gpio,
254 gpio_pin_t pin,
255 gpio_flags_t flags)
256 {
257 if ((flags & GPIO_PULL_UP) != 0) {
258 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLUP_10K);
259 } else if ((flags & GPIO_PULL_DOWN) != 0) {
260 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_PULLDOWN_100K);
261 } else {
262 gpio_b91_up_down_res_set(gpio, pin, GPIO_PIN_UP_DOWN_FLOAT);
263 }
264 }
265
266 /* Config Pin In/Out direction */
gpio_b91_config_in_out(volatile struct gpio_b91_t * gpio,gpio_pin_t pin,gpio_flags_t flags)267 static void gpio_b91_config_in_out(volatile struct gpio_b91_t *gpio,
268 gpio_pin_t pin,
269 gpio_flags_t flags)
270 {
271 uint8_t ie_addr = 0;
272
273 /* Port C and D Input Enable registers are located in another place: analog */
274 if (IS_PORT_C(gpio)) {
275 ie_addr = areg_gpio_pc_ie;
276 } else if (IS_PORT_D(gpio)) {
277 ie_addr = areg_gpio_pd_ie;
278 }
279
280 /* Enable/disable output */
281 WRITE_BIT(gpio->oen, pin, ~flags & GPIO_OUTPUT);
282
283 /* Enable/disable input */
284 if (ie_addr != 0) {
285 /* Port C and D are located in analog space */
286 if (flags & GPIO_INPUT) {
287 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) | BIT(pin));
288 } else {
289 analog_write_reg8(ie_addr, analog_read_reg8(ie_addr) & (~BIT(pin)));
290 }
291 } else {
292 /* Input Enable registers of all other ports are located in common GPIO space */
293 WRITE_BIT(gpio->ie, pin, flags & GPIO_INPUT);
294 }
295 }
296
297 /* GPIO driver initialization */
gpio_b91_init(const struct device * dev)298 static int gpio_b91_init(const struct device *dev)
299 {
300 const struct gpio_b91_config *cfg = dev->config;
301
302 cfg->pirq_connect();
303
304 return 0;
305 }
306
307 /* API implementation: pin_configure */
gpio_b91_pin_configure(const struct device * dev,gpio_pin_t pin,gpio_flags_t flags)308 static int gpio_b91_pin_configure(const struct device *dev,
309 gpio_pin_t pin,
310 gpio_flags_t flags)
311 {
312 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
313
314 /* Check input parameters: pin number */
315 if (pin > PIN_NUM_MAX) {
316 return -ENOTSUP;
317 }
318
319 /* Check input parameters: open-source and open-drain */
320 if ((flags & GPIO_SINGLE_ENDED) != 0) {
321 return -ENOTSUP;
322 }
323
324 /* Check input parameters: simultaneous in/out mode */
325 if ((flags & GPIO_OUTPUT) && (flags & GPIO_INPUT)) {
326 return -ENOTSUP;
327 }
328
329 /* Set GPIO init state if defined to avoid glitches */
330 if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
331 gpio->output |= BIT(pin);
332 } else if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
333 gpio->output &= ~BIT(pin);
334 }
335
336 /* GPIO function enable */
337 WRITE_BIT(gpio->actas_gpio, BIT(pin), 1);
338
339 /* Set GPIO pull-up / pull-down resistors */
340 gpio_b91_config_up_down_res(gpio, pin, flags);
341
342 /* Enable/disable input/output */
343 gpio_b91_config_in_out(gpio, pin, flags);
344
345 return 0;
346 }
347
348 /* API implementation: port_get_raw */
gpio_b91_port_get_raw(const struct device * dev,gpio_port_value_t * value)349 static int gpio_b91_port_get_raw(const struct device *dev,
350 gpio_port_value_t *value)
351 {
352 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
353
354 *value = gpio->input;
355
356 return 0;
357 }
358
359 /* API implementation: port_set_masked_raw */
gpio_b91_port_set_masked_raw(const struct device * dev,gpio_port_pins_t mask,gpio_port_value_t value)360 static int gpio_b91_port_set_masked_raw(const struct device *dev,
361 gpio_port_pins_t mask,
362 gpio_port_value_t value)
363 {
364 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
365
366 gpio->output = (gpio->output & ~mask) | (value & mask);
367
368 return 0;
369 }
370
371 /* API implementation: port_set_bits_raw */
gpio_b91_port_set_bits_raw(const struct device * dev,gpio_port_pins_t mask)372 static int gpio_b91_port_set_bits_raw(const struct device *dev,
373 gpio_port_pins_t mask)
374 {
375 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
376
377 gpio->output |= mask;
378
379 return 0;
380 }
381
382 /* API implementation: port_clear_bits_raw */
gpio_b91_port_clear_bits_raw(const struct device * dev,gpio_port_pins_t mask)383 static int gpio_b91_port_clear_bits_raw(const struct device *dev,
384 gpio_port_pins_t mask)
385 {
386 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
387
388 gpio->output &= ~mask;
389
390 return 0;
391 }
392
393 /* API implementation: port_toggle_bits */
gpio_b91_port_toggle_bits(const struct device * dev,gpio_port_pins_t mask)394 static int gpio_b91_port_toggle_bits(const struct device *dev,
395 gpio_port_pins_t mask)
396 {
397 volatile struct gpio_b91_t *gpio = GET_GPIO(dev);
398
399 gpio->output ^= mask;
400
401 return 0;
402 }
403
404 /* API implementation: interrupts handler */
405 #if IS_INST_IRQ_EN(0) || IS_INST_IRQ_EN(1) || IS_INST_IRQ_EN(2) || \
406 IS_INST_IRQ_EN(3) || IS_INST_IRQ_EN(4)
gpio_b91_irq_handler(const struct device * dev)407 static void gpio_b91_irq_handler(const struct device *dev)
408 {
409 struct gpio_b91_data *data = dev->data;
410 uint8_t irq = GET_IRQ_NUM(dev);
411 uint8_t status = gpio_b91_irq_en_get(dev);
412
413 gpio_b91_irq_status_clr(irq);
414 gpio_fire_callbacks(&data->callbacks, dev, status);
415 }
416 #endif
417
418 /* API implementation: pin_interrupt_configure */
gpio_b91_pin_interrupt_configure(const struct device * dev,gpio_pin_t pin,enum gpio_int_mode mode,enum gpio_int_trig trig)419 static int gpio_b91_pin_interrupt_configure(const struct device *dev,
420 gpio_pin_t pin,
421 enum gpio_int_mode mode,
422 enum gpio_int_trig trig)
423 {
424 int ret_status = 0;
425
426 switch (mode) {
427 case GPIO_INT_MODE_DISABLED: /* GPIO interrupt disable */
428 gpiob_b91_irq_en_clr(dev, pin);
429 break;
430
431 case GPIO_INT_MODE_LEVEL:
432 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt High level */
433 gpio_b91_irq_set(dev, pin, INTR_HIGH_LEVEL);
434 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Low level */
435 gpio_b91_irq_set(dev, pin, INTR_LOW_LEVEL);
436 } else {
437 ret_status = -ENOTSUP;
438 }
439 break;
440
441 case GPIO_INT_MODE_EDGE:
442 if (trig == GPIO_INT_TRIG_HIGH) { /* GPIO interrupt Rising edge */
443 gpio_b91_irq_set(dev, pin, INTR_RISING_EDGE);
444 } else if (trig == GPIO_INT_TRIG_LOW) { /* GPIO interrupt Falling edge */
445 gpio_b91_irq_set(dev, pin, INTR_FALLING_EDGE);
446 } else {
447 ret_status = -ENOTSUP;
448 }
449 break;
450
451 default:
452 ret_status = -ENOTSUP;
453 break;
454 }
455
456 return ret_status;
457 }
458
459 /* API implementation: manage_callback */
gpio_b91_manage_callback(const struct device * dev,struct gpio_callback * callback,bool set)460 static int gpio_b91_manage_callback(const struct device *dev,
461 struct gpio_callback *callback,
462 bool set)
463 {
464 struct gpio_b91_data *data = dev->data;
465
466 return gpio_manage_callback(&data->callbacks, callback, set);
467 }
468
469 /* GPIO driver APIs structure */
470 static const struct gpio_driver_api gpio_b91_driver_api = {
471 .pin_configure = gpio_b91_pin_configure,
472 .port_get_raw = gpio_b91_port_get_raw,
473 .port_set_masked_raw = gpio_b91_port_set_masked_raw,
474 .port_set_bits_raw = gpio_b91_port_set_bits_raw,
475 .port_clear_bits_raw = gpio_b91_port_clear_bits_raw,
476 .port_toggle_bits = gpio_b91_port_toggle_bits,
477 .pin_interrupt_configure = gpio_b91_pin_interrupt_configure,
478 .manage_callback = gpio_b91_manage_callback
479 };
480
481 /* If instance 0 is present and has interrupt enabled, connect IRQ */
482 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 0
gpio_b91_irq_connect_0(void)483 static void gpio_b91_irq_connect_0(void)
484 {
485 #if IS_INST_IRQ_EN(0)
486 IRQ_CONNECT(DT_INST_IRQN(0), DT_INST_IRQ(0, priority),
487 gpio_b91_irq_handler,
488 DEVICE_DT_INST_GET(0), 0);
489 #endif
490 }
491 #endif
492
493 /* If instance 1 is present and has interrupt enabled, connect IRQ */
494 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 1
gpio_b91_irq_connect_1(void)495 static void gpio_b91_irq_connect_1(void)
496 {
497 #if IS_INST_IRQ_EN(1)
498 IRQ_CONNECT(DT_INST_IRQN(1), DT_INST_IRQ(1, priority),
499 gpio_b91_irq_handler,
500 DEVICE_DT_INST_GET(1), 0);
501 #endif
502 }
503 #endif
504
505 /* If instance 2 is present and has interrupt enabled, connect IRQ */
506 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 2
gpio_b91_irq_connect_2(void)507 static void gpio_b91_irq_connect_2(void)
508 {
509 #if IS_INST_IRQ_EN(2)
510 IRQ_CONNECT(DT_INST_IRQN(2), DT_INST_IRQ(2, priority),
511 gpio_b91_irq_handler,
512 DEVICE_DT_INST_GET(2), 0);
513 #endif
514 }
515 #endif
516
517 /* If instance 3 is present and has interrupt enabled, connect IRQ */
518 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 3
gpio_b91_irq_connect_3(void)519 static void gpio_b91_irq_connect_3(void)
520 {
521 #if IS_INST_IRQ_EN(3)
522 IRQ_CONNECT(DT_INST_IRQN(3), DT_INST_IRQ(3, priority),
523 gpio_b91_irq_handler,
524 DEVICE_DT_INST_GET(3), 0);
525 #endif
526 }
527 #endif
528
529 /* If instance 4 is present and has interrupt enabled, connect IRQ */
530 #if DT_NUM_INST_STATUS_OKAY(DT_DRV_COMPAT) > 4
gpio_b91_irq_connect_4(void)531 static void gpio_b91_irq_connect_4(void)
532 {
533 #if IS_INST_IRQ_EN(4)
534 IRQ_CONNECT(DT_INST_IRQN(4), DT_INST_IRQ(4, priority),
535 gpio_b91_irq_handler,
536 DEVICE_DT_INST_GET(4), 0);
537 #endif
538 }
539 #endif
540
541 /* GPIO driver registration */
542 #define GPIO_B91_INIT(n) \
543 static const struct gpio_b91_config gpio_b91_config_##n = { \
544 .common = { \
545 .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n) \
546 }, \
547 .gpio_base = DT_INST_REG_ADDR(n), \
548 .irq_num = DT_INST_IRQN(n), \
549 .irq_priority = DT_INST_IRQ(n, priority), \
550 .pirq_connect = gpio_b91_irq_connect_##n \
551 }; \
552 static struct gpio_b91_data gpio_b91_data_##n; \
553 \
554 DEVICE_DT_INST_DEFINE(n, gpio_b91_init, \
555 NULL, \
556 &gpio_b91_data_##n, \
557 &gpio_b91_config_##n, \
558 PRE_KERNEL_1, \
559 CONFIG_GPIO_INIT_PRIORITY, \
560 &gpio_b91_driver_api);
561
562 DT_INST_FOREACH_STATUS_OKAY(GPIO_B91_INIT)
563
