1 /*! 2 \file gd32vf103_usart.h 3 \brief definitions for the USART 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2019-09-18, V1.0.1, firmware for GD32VF103 7 \version 2020-08-04, V1.1.0, firmware for GD32VF103 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32VF103_USART_H 38 #define GD32VF103_USART_H 39 40 #include "gd32vf103.h" 41 42 /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ 43 #define USART1 USART_BASE /*!< USART1 base address */ 44 #define USART2 (USART_BASE+(0x00000400U)) /*!< USART2 base address */ 45 #define UART3 (USART_BASE+(0x00000800U)) /*!< UART3 base address */ 46 #define UART4 (USART_BASE+(0x00000C00U)) /*!< UART4 base address */ 47 #define USART0 (USART_BASE+(0x0000F400U)) /*!< USART0 base address */ 48 49 /* registers definitions */ 50 #define USART_STAT(usartx) REG32((usartx) + (0x00000000U)) /*!< USART status register */ 51 #define USART_DATA(usartx) REG32((usartx) + (0x00000004U)) /*!< USART data register */ 52 #define USART_BAUD(usartx) REG32((usartx) + (0x00000008U)) /*!< USART baud rate register */ 53 #define USART_CTL0(usartx) REG32((usartx) + (0x0000000CU)) /*!< USART control register 0 */ 54 #define USART_CTL1(usartx) REG32((usartx) + (0x00000010U)) /*!< USART control register 1 */ 55 #define USART_CTL2(usartx) REG32((usartx) + (0x00000014U)) /*!< USART control register 2 */ 56 #define USART_GP(usartx) REG32((usartx) + (0x00000018U)) /*!< USART guard time and prescaler register */ 57 58 /* bits definitions */ 59 /* USARTx_STAT */ 60 #define USART_STAT_PERR BIT(0) /*!< parity error flag */ 61 #define USART_STAT_FERR BIT(1) /*!< frame error flag */ 62 #define USART_STAT_NERR BIT(2) /*!< noise error flag */ 63 #define USART_STAT_ORERR BIT(3) /*!< overrun error */ 64 #define USART_STAT_IDLEF BIT(4) /*!< IDLE frame detected flag */ 65 #define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ 66 #define USART_STAT_TC BIT(6) /*!< transmission complete */ 67 #define USART_STAT_TBE BIT(7) /*!< transmit data buffer empty */ 68 #define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ 69 #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ 70 71 /* USARTx_DATA */ 72 #define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ 73 74 /* USARTx_BAUD */ 75 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ 76 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ 77 78 /* USARTx_CTL0 */ 79 #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ 80 #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ 81 #define USART_CTL0_REN BIT(2) /*!< receiver enable */ 82 #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ 83 #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 84 #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 85 #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 86 #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 87 #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 88 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 89 #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ 90 #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 91 #define USART_CTL0_WL BIT(12) /*!< word length */ 92 #define USART_CTL0_UEN BIT(13) /*!< USART enable */ 93 94 /* USARTx_CTL1 */ 95 #define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ 96 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 97 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ 98 #define USART_CTL1_CLEN BIT(8) /*!< CK length */ 99 #define USART_CTL1_CPH BIT(9) /*!< CK phase */ 100 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ 101 #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ 102 #define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ 103 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 104 105 /* USARTx_CTL2 */ 106 #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ 107 #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 108 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 109 #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 110 #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 111 #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 112 #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ 113 #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ 114 #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 115 #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 116 #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 117 118 /* USARTx_GP */ 119 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 120 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 121 122 /* constants definitions */ 123 /* define the USART bit position and its register index offset */ 124 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 125 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)) >> 6))) 126 #define USART_BIT_POS(val) ((uint32_t)(val) & (0x0000001FU)) 127 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 128 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 129 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 130 #define USART_BIT_POS2(val) (((uint32_t)(val) & (0x001F0000U)) >> 16) 131 132 /* register offset */ 133 #define USART_STAT_REG_OFFSET (0x00000000U) /*!< STAT register offset */ 134 #define USART_CTL0_REG_OFFSET (0x0000000CU) /*!< CTL0 register offset */ 135 #define USART_CTL1_REG_OFFSET (0x00000010U) /*!< CTL1 register offset */ 136 #define USART_CTL2_REG_OFFSET (0x00000014U) /*!< CTL2 register offset */ 137 138 /* USART flags */ 139 typedef enum 140 { 141 /* flags in STAT register */ 142 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ 143 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ 144 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 145 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ 146 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ 147 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ 148 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ 149 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ 150 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ 151 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ 152 }usart_flag_enum; 153 154 /* USART interrupt flags */ 155 typedef enum 156 { 157 /* interrupt flags in CTL0 register */ 158 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 159 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 160 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 161 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 162 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 163 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 164 /* interrupt flags in CTL1 register */ 165 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 166 /* interrupt flags in CTL2 register */ 167 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 168 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 169 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 170 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 171 }usart_interrupt_flag_enum; 172 173 /* USART interrupt enable or disable */ 174 typedef enum 175 { 176 /* interrupt in CTL0 register */ 177 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 178 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 179 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 180 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 181 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 182 /* interrupt in CTL1 register */ 183 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 184 /* interrupt in CTL2 register */ 185 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 186 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 187 }usart_interrupt_enum; 188 189 /* USART receiver configure */ 190 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 191 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 192 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 193 194 /* USART transmitter configure */ 195 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 196 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 197 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 198 199 /* USART parity bits definitions */ 200 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 201 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 202 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 203 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 204 205 /* USART wakeup method in mute mode */ 206 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 207 #define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ 208 #define USART_WM_ADDR CTL0_WM(1) /*!< address match */ 209 210 /* USART word length definitions */ 211 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 212 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 213 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 214 215 /* USART stop bits definitions */ 216 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 217 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 218 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 219 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 220 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 221 222 /* USART LIN break frame length */ 223 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 224 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ 225 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ 226 227 /* USART CK length */ 228 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 229 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ 230 #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ 231 232 /* USART clock phase */ 233 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 234 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 235 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 236 237 /* USART clock polarity */ 238 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 239 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 240 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 241 242 /* USART DMA request for receive configure */ 243 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 244 #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ 245 #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ 246 247 /* USART DMA request for transmission configure */ 248 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 249 #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ 250 #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ 251 252 /* USART RTS configure */ 253 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 254 #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ 255 #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ 256 257 /* USART CTS configure */ 258 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 259 #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ 260 #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ 261 262 /* USART IrDA low-power enable */ 263 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 264 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 265 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 266 267 /* function declarations */ 268 /* initialization functions */ 269 /* reset USART */ 270 void usart_deinit(uint32_t usart_periph); 271 /* configure USART baud rate value */ 272 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 273 /* configure USART parity function */ 274 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 275 /* configure USART word length */ 276 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 277 /* configure USART stop bit length */ 278 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 279 280 /* USART normal mode communication */ 281 /* enable USART */ 282 void usart_enable(uint32_t usart_periph); 283 /* disable USART */ 284 void usart_disable(uint32_t usart_periph); 285 /* configure USART transmitter */ 286 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 287 /* configure USART receiver */ 288 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 289 /* USART transmit data function */ 290 void usart_data_transmit(uint32_t usart_periph, uint32_t data); 291 /* USART receive data function */ 292 uint16_t usart_data_receive(uint32_t usart_periph); 293 294 /* multi-processor communication */ 295 /* configure address of the USART */ 296 void usart_address_config(uint32_t usart_periph, uint8_t addr); 297 /* enable mute mode */ 298 void usart_mute_mode_enable(uint32_t usart_periph); 299 /* disable mute mode */ 300 void usart_mute_mode_disable(uint32_t usart_periph); 301 /* configure wakeup method in mute mode */ 302 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); 303 304 /* LIN mode communication */ 305 /* LIN mode enable */ 306 void usart_lin_mode_enable(uint32_t usart_periph); 307 /* LIN mode disable */ 308 void usart_lin_mode_disable(uint32_t usart_periph); 309 /* LIN break detection length */ 310 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 311 /* send break frame */ 312 void usart_send_break(uint32_t usart_periph); 313 314 /* half-duplex communication */ 315 /* half-duplex enable */ 316 void usart_halfduplex_enable(uint32_t usart_periph); 317 /* half-duplex disable */ 318 void usart_halfduplex_disable(uint32_t usart_periph); 319 320 /* synchronous communication */ 321 /* clock enable */ 322 void usart_synchronous_clock_enable(uint32_t usart_periph); 323 /* clock disable */ 324 void usart_synchronous_clock_disable(uint32_t usart_periph); 325 /* configure usart synchronous mode parameters */ 326 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 327 328 /* smartcard communication */ 329 /* guard time value configure in smartcard mode */ 330 void usart_guard_time_config(uint32_t usart_periph, uint32_t gaut); 331 /* smartcard mode enable */ 332 void usart_smartcard_mode_enable(uint32_t usart_periph); 333 /* smartcard mode disable */ 334 void usart_smartcard_mode_disable(uint32_t usart_periph); 335 /* NACK enable in smartcard mode */ 336 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 337 /* NACK disable in smartcard mode */ 338 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 339 340 /* IrDA communication */ 341 /* enable IrDA mode */ 342 void usart_irda_mode_enable(uint32_t usart_periph); 343 /* disable IrDA mode */ 344 void usart_irda_mode_disable(uint32_t usart_periph); 345 /* configure the peripheral clock prescaler */ 346 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); 347 /* configure IrDA low-power */ 348 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 349 350 /* hardware flow communication */ 351 /* configure hardware flow control RTS */ 352 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 353 /* configure hardware flow control CTS */ 354 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 355 356 /* configure USART DMA for reception */ 357 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); 358 /* configure USART DMA for transmission */ 359 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); 360 361 /* flag functions */ 362 /* get flag in STAT register */ 363 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 364 /* clear flag in STAT register */ 365 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 366 367 /* interrupt functions */ 368 /* enable USART interrupt */ 369 void usart_interrupt_enable(uint32_t usart_periph, uint32_t interrupt); 370 /* disable USART interrupt */ 371 void usart_interrupt_disable(uint32_t usart_periph, uint32_t interrupt); 372 /* get USART interrupt and flag status */ 373 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, uint32_t int_flag); 374 /* clear interrupt flag in STAT register */ 375 void usart_interrupt_flag_clear(uint32_t usart_periph, uint32_t int_flag); 376 #endif /* GD32VF103_USART_H */ 377
