1 /*! 2 \file gd32vf103_rcu.h 3 \brief definitions for the RCU 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2020-08-04, V1.1.0, firmware for GD32VF103 7 */ 8 9 /* 10 Copyright (c) 2020, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32VF103_RCU_H 37 #define GD32VF103_RCU_H 38 39 #include "gd32vf103.h" 40 41 /* RCU definitions */ 42 #define RCU RCU_BASE 43 44 /* registers definitions */ 45 46 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ 47 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ 48 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ 49 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ 50 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ 51 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ 52 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ 53 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ 54 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ 55 #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ 56 #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ 57 #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ 58 #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ 59 60 61 /* bits definitions */ 62 /* RCU_CTL */ 63 #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 64 #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 65 #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 66 #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 67 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 68 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 69 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 70 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 71 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 72 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 73 #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ 74 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ 75 #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ 76 #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ 77 78 79 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 80 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 81 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 82 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 83 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 84 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ 85 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 86 #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ 87 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 88 #define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ 89 #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ 90 #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ 91 #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ 92 93 /* RCU_INT */ 94 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 95 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 96 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 97 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 98 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 99 #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ 100 #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ 101 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 102 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 103 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 104 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 105 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 106 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 107 #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ 108 #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ 109 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ 110 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 111 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ 112 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 113 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 114 #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ 115 #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ 116 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 117 118 /* RCU_APB2RST */ 119 #define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ 120 #define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ 121 #define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ 122 #define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ 123 #define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ 124 #define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ 125 #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ 126 #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ 127 #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ 128 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 129 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 130 131 /* RCU_APB1RST */ 132 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 reset */ 133 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ 134 #define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ 135 #define RCU_APB1RST_TIMER4RST BIT(3) /*!< TIMER4 reset */ 136 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ 137 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ 138 139 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ 140 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 141 #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ 142 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 143 #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ 144 #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ 145 #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ 146 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 147 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 148 #define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ 149 #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ 150 #define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ 151 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ 152 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 153 154 /* RCU_AHBEN */ 155 #define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ 156 #define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ 157 #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ 158 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ 159 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 160 #define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ 161 #define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ 162 163 /* RCU_APB2EN */ 164 #define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ 165 #define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ 166 #define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ 167 #define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ 168 #define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ 169 #define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ 170 #define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ 171 #define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ 172 #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ 173 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 174 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 175 176 /* RCU_APB1EN */ 177 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 clock enable */ 178 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ 179 #define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ 180 #define RCU_APB1EN_TIMER4EN BIT(3) /*!< TIMER4 clock enable */ 181 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ 182 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ 183 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ 184 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 185 #define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ 186 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 187 #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ 188 #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ 189 #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ 190 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 191 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 192 #define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ 193 #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ 194 #define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ 195 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ 196 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 197 198 /* RCU_BDCTL */ 199 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 200 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ 201 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 202 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 203 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 204 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 205 206 /* RCU_RSTSCK */ 207 #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ 208 #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ 209 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 210 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 211 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 212 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 213 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 214 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 215 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 216 217 /* RCU_AHBRST */ 218 #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ 219 220 /* RCU_CFG1 */ 221 #define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ 222 #define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ 223 #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ 224 #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ 225 #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ 226 #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ 227 #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ 228 229 /* RCU_DSV */ 230 #define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ 231 232 /* constants definitions */ 233 /* define the peripheral clock enable bit position and its register index offset */ 234 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 235 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) 236 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 237 238 /* register offset */ 239 /* peripherals enable */ 240 #define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ 241 #define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ 242 #define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ 243 244 /* peripherals reset */ 245 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ 246 #define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ 247 #define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ 248 #define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ 249 250 /* clock control */ 251 #define CTL_REG_OFFSET 0x00U /*!< control register offset */ 252 #define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ 253 254 /* clock stabilization and stuck interrupt */ 255 #define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ 256 257 /* configuration register */ 258 #define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ 259 #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ 260 261 /* peripheral clock enable */ 262 typedef enum { 263 /* AHB peripherals */ 264 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ 265 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ 266 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ 267 RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ 268 RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ 269 /* APB1 peripherals */ 270 RCU_TIMER1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 0U), /*!< TIMER1 clock */ 271 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 272 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ 273 RCU_TIMER4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 3U), /*!< TIMER4 clock */ 274 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 275 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 276 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 277 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 278 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ 279 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 280 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ 281 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ 282 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ 283 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 284 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 285 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ 286 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ 287 RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ 288 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 289 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 290 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ 291 /* APB2 peripherals */ 292 RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ 293 RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ 294 RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ 295 RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ 296 RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ 297 RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ 298 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ 299 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ 300 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ 301 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 302 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ 303 } rcu_periph_enum; 304 305 /* peripheral clock enable when sleep mode*/ 306 typedef enum { 307 /* AHB peripherals */ 308 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ 309 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ 310 } rcu_periph_sleep_enum; 311 312 /* peripherals reset */ 313 typedef enum { 314 /* AHB peripherals */ 315 RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ 316 /* APB1 peripherals */ 317 RCU_TIMER1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 0U), /*!< TIMER1 clock reset */ 318 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ 319 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ 320 RCU_TIMER4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 3U), /*!< TIMER4 clock reset */ 321 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ 322 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ 323 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ 324 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ 325 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ 326 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ 327 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ 328 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ 329 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ 330 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ 331 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ 332 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ 333 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ 334 RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ 335 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ 336 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ 337 /* APB2 peripherals */ 338 RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ 339 RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ 340 RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ 341 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ 342 RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ 343 RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ 344 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ 345 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ 346 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ 347 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ 348 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ 349 } rcu_periph_reset_enum; 350 351 /* clock stabilization and peripheral reset flags */ 352 typedef enum { 353 /* clock stabilization flags */ 354 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ 355 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ 356 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ 357 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ 358 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ 359 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ 360 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ 361 /* reset source flags */ 362 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ 363 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ 364 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ 365 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ 366 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ 367 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ 368 } rcu_flag_enum; 369 370 /* clock stabilization and ckm interrupt flags */ 371 typedef enum { 372 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ 373 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 374 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ 375 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 376 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 377 RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ 378 RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ 379 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ 380 } rcu_int_flag_enum; 381 382 /* clock stabilization and stuck interrupt flags clear */ 383 typedef enum { 384 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ 385 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ 386 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ 387 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ 388 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ 389 RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ 390 RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ 391 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ 392 } rcu_int_flag_clear_enum; 393 394 /* clock stabilization interrupt enable or disable */ 395 typedef enum { 396 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ 397 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ 398 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ 399 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ 400 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ 401 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ 402 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ 403 } rcu_int_enum; 404 405 /* oscillator types */ 406 typedef enum { 407 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 408 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 409 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ 410 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ 411 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ 412 RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ 413 RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ 414 } rcu_osci_type_enum; 415 416 /* rcu clock frequency */ 417 typedef enum { 418 CK_SYS = 0, /*!< system clock */ 419 CK_AHB, /*!< AHB clock */ 420 CK_APB1, /*!< APB1 clock */ 421 CK_APB2, /*!< APB2 clock */ 422 } rcu_clock_freq_enum; 423 424 /* RCU_CFG0 register bit define */ 425 /* system clock source select */ 426 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 427 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ 428 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 429 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 430 431 /* system clock source select status */ 432 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 433 #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ 434 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 435 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ 436 437 /* AHB prescaler selection */ 438 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 439 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 440 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 441 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 442 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 443 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 444 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 445 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 446 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 447 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 448 449 /* APB1 prescaler selection */ 450 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 451 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 452 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 453 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 454 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 455 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 456 457 /* APB2 prescaler selection */ 458 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) 459 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 460 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 461 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 462 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 463 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 464 465 /* ADC prescaler select */ 466 #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ 467 #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ 468 #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ 469 #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ 470 #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ 471 #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ 472 473 /* PLL clock source selection */ 474 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ 475 #define RCU_PLLSRC_HXTAL RCU_CFG0_PLLSEL /*!< HXTAL clock selected as source clock of PLL */ 476 477 /* PLL clock multiplication factor */ 478 #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ 479 480 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) 481 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ 482 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ 483 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ 484 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ 485 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ 486 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ 487 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ 488 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ 489 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ 490 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ 491 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ 492 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ 493 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ 494 #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ 495 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ 496 #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ 497 #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ 498 #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ 499 #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ 500 #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ 501 #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ 502 #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ 503 #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ 504 #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ 505 #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ 506 #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ 507 #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ 508 #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ 509 #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ 510 #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ 511 #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ 512 513 /* USBFS prescaler select */ 514 #define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) 515 #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ 516 #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ 517 #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ 518 #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ 519 520 /* CKOUT0 clock source selection */ 521 #define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 522 #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ 523 #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ 524 #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ 525 #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ 526 #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ 527 #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ 528 #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ 529 #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected */ 530 #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ 531 532 /* RTC clock entry selection */ 533 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 534 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 535 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ 536 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ 537 #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ 538 539 /* PREDV0 division factor */ 540 #define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 541 #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ 542 #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ 543 #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ 544 #define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ 545 #define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ 546 #define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ 547 #define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ 548 #define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ 549 #define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ 550 #define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ 551 #define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ 552 #define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ 553 #define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ 554 #define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ 555 #define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ 556 #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ 557 558 /* PREDV1 division factor */ 559 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 560 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ 561 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ 562 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ 563 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ 564 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ 565 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ 566 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ 567 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ 568 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ 569 #define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ 570 #define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ 571 #define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ 572 #define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ 573 #define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ 574 #define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ 575 #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ 576 577 /* PLL1 clock multiplication factor */ 578 #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) 579 #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ 580 #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ 581 #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ 582 #define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ 583 #define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ 584 #define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ 585 #define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ 586 #define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ 587 #define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ 588 #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ 589 590 /* PLL2 clock multiplication factor */ 591 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) 592 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ 593 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ 594 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ 595 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ 596 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ 597 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ 598 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ 599 #define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ 600 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ 601 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ 602 603 604 /* PREDV0 input clock source selection */ 605 #define RCU_PREDV0SRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PREDV0 input source clock */ 606 #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ 607 608 /* I2S1 clock source selection */ 609 #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ 610 #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ 611 612 /* I2S2 clock source selection */ 613 #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ 614 #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ 615 616 617 /* deep-sleep mode voltage */ 618 #define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 619 #define RCU_DEEPSLEEP_V_1_2 DSV_DSLPVS(0) /*!< core voltage is 1.2V in deep-sleep mode */ 620 #define RCU_DEEPSLEEP_V_1_1 DSV_DSLPVS(1) /*!< core voltage is 1.1V in deep-sleep mode */ 621 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(2) /*!< core voltage is 1.0V in deep-sleep mode */ 622 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(3) /*!< core voltage is 0.9V in deep-sleep mode */ 623 624 /* function declarations */ 625 /* initialization, peripheral clock enable/disable functions */ 626 /* deinitialize the RCU */ 627 void rcu_deinit(void); 628 /* enable the peripherals clock */ 629 void rcu_periph_clock_enable(rcu_periph_enum periph); 630 /* disable the peripherals clock */ 631 void rcu_periph_clock_disable(rcu_periph_enum periph); 632 /* enable the peripherals clock when sleep mode */ 633 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 634 /* disable the peripherals clock when sleep mode */ 635 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 636 /* reset the peripherals */ 637 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 638 /* disable reset the peripheral */ 639 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 640 /* reset the BKP domain */ 641 void rcu_bkp_reset_enable(void); 642 /* disable the BKP domain reset */ 643 void rcu_bkp_reset_disable(void); 644 645 /* clock configuration functions */ 646 /* configure the system clock source */ 647 void rcu_system_clock_source_config(uint32_t ck_sys); 648 /* get the system clock source */ 649 uint32_t rcu_system_clock_source_get(void); 650 /* configure the AHB prescaler selection */ 651 void rcu_ahb_clock_config(uint32_t ck_ahb); 652 /* configure the APB1 prescaler selection */ 653 void rcu_apb1_clock_config(uint32_t ck_apb1); 654 /* configure the APB2 prescaler selection */ 655 void rcu_apb2_clock_config(uint32_t ck_apb2); 656 /* configure the CK_OUT0 clock source and divider */ 657 void rcu_ckout0_config(uint32_t ckout0_src); 658 /* configure the PLL clock source selection and PLL multiply factor */ 659 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 660 661 /* configure the PREDV0 division factor and clock source */ 662 void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); 663 /* configure the PREDV1 division factor */ 664 void rcu_predv1_config(uint32_t predv1_div); 665 /* configure the PLL1 clock */ 666 void rcu_pll1_config(uint32_t pll_mul); 667 /* configure the PLL2 clock */ 668 void rcu_pll2_config(uint32_t pll_mul); 669 670 /* peripheral clock configuration functions */ 671 /* configure the ADC division factor */ 672 void rcu_adc_clock_config(uint32_t adc_psc); 673 /* configure the USBD/USBFS prescaler factor */ 674 void rcu_usb_clock_config(uint32_t usb_psc); 675 /* configure the RTC clock source selection */ 676 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 677 678 /* configure the I2S1 clock source selection */ 679 void rcu_i2s1_clock_config(uint32_t i2s_clock_source); 680 /* configure the I2S2 clock source selection */ 681 void rcu_i2s2_clock_config(uint32_t i2s_clock_source); 682 683 /* interrupt & flag functions */ 684 /* get the clock stabilization and periphral reset flags */ 685 FlagStatus rcu_flag_get(rcu_flag_enum flag); 686 /* clear the reset flag */ 687 void rcu_all_reset_flag_clear(void); 688 /* get the clock stabilization interrupt and ckm flags */ 689 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 690 /* clear the interrupt flags */ 691 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); 692 /* enable the stabilization interrupt */ 693 void rcu_interrupt_enable(rcu_int_enum stab_int); 694 /* disable the stabilization interrupt */ 695 void rcu_interrupt_disable(rcu_int_enum stab_int); 696 697 /* oscillator configuration functions */ 698 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ 699 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 700 /* turn on the oscillator */ 701 void rcu_osci_on(rcu_osci_type_enum osci); 702 /* turn off the oscillator */ 703 void rcu_osci_off(rcu_osci_type_enum osci); 704 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 705 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 706 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 707 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 708 /* enable the HXTAL clock monitor */ 709 void rcu_hxtal_clock_monitor_enable(void); 710 /* disable the HXTAL clock monitor */ 711 void rcu_hxtal_clock_monitor_disable(void); 712 713 /* set the IRC8M adjust value */ 714 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); 715 /* set the deep sleep mode voltage */ 716 void rcu_deepsleep_voltage_set(uint32_t dsvol); 717 718 /* get the system clock, bus and peripheral clock frequency */ 719 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 720 721 #endif /* GD32VF103_RCU_H */ 722
