1 /*! 2 \file gd32vf103_pmu.h 3 \brief definitions for the PMU 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2020-08-04, V1.1.0, firmware for GD32VF103 7 */ 8 9 /* 10 Copyright (c) 2020, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32VF103_PMU_H 37 #define GD32VF103_PMU_H 38 39 #include "gd32vf103.h" 40 41 /* PMU definitions */ 42 #define PMU PMU_BASE /*!< PMU base address */ 43 44 /* registers definitions */ 45 #define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ 46 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ 47 48 /* bits definitions */ 49 /* PMU_CTL */ 50 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 51 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 52 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 53 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 54 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 55 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 56 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 57 58 /* PMU_CS */ 59 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 60 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 61 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 62 #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ 63 64 /* constants definitions */ 65 /* PMU low voltage detector threshold definitions */ 66 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval) << 5)) 67 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.2V */ 68 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ 69 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ 70 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.5V */ 71 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.6V */ 72 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.7V */ 73 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 2.8V */ 74 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 2.9V */ 75 76 /* PMU flag definitions */ 77 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 78 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 79 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 80 81 /* PMU ldo definitions */ 82 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ 83 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 84 85 /* PMU flag reset definitions */ 86 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 87 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 88 89 /* PMU command constants definitions */ 90 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 91 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 92 93 /* function declarations */ 94 /* reset PMU registers */ 95 void pmu_deinit(void); 96 97 /* select low voltage detector threshold */ 98 void pmu_lvd_select(uint32_t lvdt_n); 99 /* disable PMU lvd */ 100 void pmu_lvd_disable(void); 101 102 /* set PMU mode */ 103 /* PMU work at sleep mode */ 104 void pmu_to_sleepmode(uint8_t sleepmodecmd); 105 /* PMU work at deepsleep mode */ 106 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); 107 /* PMU work at standby mode */ 108 void pmu_to_standbymode(uint8_t standbymodecmd); 109 /* enable PMU wakeup pin */ 110 void pmu_wakeup_pin_enable(void); 111 /* disable PMU wakeup pin */ 112 void pmu_wakeup_pin_disable(void); 113 114 /* backup related functions */ 115 /* enable write access to the registers in backup domain */ 116 void pmu_backup_write_enable(void); 117 /* disable write access to the registers in backup domain */ 118 void pmu_backup_write_disable(void); 119 120 /* flag functions */ 121 /* get flag state */ 122 FlagStatus pmu_flag_get(uint32_t flag); 123 /* clear flag bit */ 124 void pmu_flag_clear(uint32_t flag_reset); 125 126 #endif /* GD32VF103_PMU_H */ 127
