1 /*!
2 \file gd32vf103_fwdgt.c
3 \brief FWDGT driver
4
5 \version 2019-06-05, V1.0.0, firmware for GD32VF103
6 \version 2020-08-04, V1.1.0, firmware for GD32VF103
7 */
8
9 /*
10 Copyright (c) 2020, GigaDevice Semiconductor Inc.
11
12 Redistribution and use in source and binary forms, with or without modification,
13 are permitted provided that the following conditions are met:
14
15 1. Redistributions of source code must retain the above copyright notice, this
16 list of conditions and the following disclaimer.
17 2. Redistributions in binary form must reproduce the above copyright notice,
18 this list of conditions and the following disclaimer in the documentation
19 and/or other materials provided with the distribution.
20 3. Neither the name of the copyright holder nor the names of its contributors
21 may be used to endorse or promote products derived from this software without
22 specific prior written permission.
23
24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
33 OF SUCH DAMAGE.
34 */
35
36 #include "gd32vf103_fwdgt.h"
37
38 /* write value to FWDGT_CTL_CMD bit field */
39 #define CTL_CMD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0))
40 /* write value to FWDGT_RLD_RLD bit field */
41 #define RLD_RLD(regval) (BITS(0,11) & ((uint32_t)(regval) << 0))
42
43 /*!
44 \brief enable write access to FWDGT_PSC and FWDGT_RLD
45 \param[in] none
46 \param[out] none
47 \retval none
48 */
fwdgt_write_enable(void)49 void fwdgt_write_enable(void)
50 {
51 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
52 }
53
54 /*!
55 \brief disable write access to FWDGT_PSC and FWDGT_RLD
56 \param[in] none
57 \param[out] none
58 \retval none
59 */
fwdgt_write_disable(void)60 void fwdgt_write_disable(void)
61 {
62 FWDGT_CTL = FWDGT_WRITEACCESS_DISABLE;
63 }
64
65 /*!
66 \brief start the free watchdog timer counter
67 \param[in] none
68 \param[out] none
69 \retval none
70 */
fwdgt_enable(void)71 void fwdgt_enable(void)
72 {
73 FWDGT_CTL = FWDGT_KEY_ENABLE;
74 }
75
76 /*!
77 \brief reload the counter of FWDGT
78 \param[in] none
79 \param[out] none
80 \retval none
81 */
fwdgt_counter_reload(void)82 void fwdgt_counter_reload(void)
83 {
84 FWDGT_CTL = FWDGT_KEY_RELOAD;
85 }
86
87 /*!
88 \brief configure counter reload value, and prescaler divider value
89 \param[in] reload_value: specify reload value(0x0000 - 0x0FFF)
90 \param[in] prescaler_div: FWDGT prescaler value
91 only one parameter can be selected which is shown as below:
92 \arg FWDGT_PSC_DIV4: FWDGT prescaler set to 4
93 \arg FWDGT_PSC_DIV8: FWDGT prescaler set to 8
94 \arg FWDGT_PSC_DIV16: FWDGT prescaler set to 16
95 \arg FWDGT_PSC_DIV32: FWDGT prescaler set to 32
96 \arg FWDGT_PSC_DIV64: FWDGT prescaler set to 64
97 \arg FWDGT_PSC_DIV128: FWDGT prescaler set to 128
98 \arg FWDGT_PSC_DIV256: FWDGT prescaler set to 256
99 \param[out] none
100 \retval ErrStatus: ERROR or SUCCESS
101 */
fwdgt_config(uint16_t reload_value,uint8_t prescaler_div)102 ErrStatus fwdgt_config(uint16_t reload_value, uint8_t prescaler_div)
103 {
104 uint32_t timeout = FWDGT_PSC_TIMEOUT;
105 uint32_t flag_status = RESET;
106
107 /* enable write access to FWDGT_PSC,and FWDGT_RLD */
108 FWDGT_CTL = FWDGT_WRITEACCESS_ENABLE;
109 /* wait until the PUD flag to be reset */
110 do{
111 flag_status = FWDGT_STAT & FWDGT_STAT_PUD;
112 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
113
114 if((uint32_t)RESET != flag_status){
115 return ERROR;
116 }
117 /* configure FWDGT */
118 FWDGT_PSC = (uint32_t)prescaler_div;
119
120 timeout = FWDGT_RLD_TIMEOUT;
121 /* wait until the RUD flag to be reset */
122 do{
123 flag_status = FWDGT_STAT & FWDGT_STAT_RUD;
124 }while((--timeout > 0U) && ((uint32_t)RESET != flag_status));
125
126 if((uint32_t)RESET != flag_status){
127 return ERROR;
128 }
129 FWDGT_RLD = RLD_RLD(reload_value);
130 /* reload the counter */
131 FWDGT_CTL = FWDGT_KEY_RELOAD;
132
133 return SUCCESS;
134 }
135
136 /*!
137 \brief get flag state of FWDGT
138 \param[in] flag: flag to get
139 only one parameter can be selected which is shown as below:
140 \arg FWDGT_FLAG_PUD: a write operation to FWDGT_PSC register is on going
141 \arg FWDGT_FLAG_RUD: a write operation to FWDGT_RLD register is on going
142 \param[out] none
143 \retval FlagStatus: SET or RESET
144 */
fwdgt_flag_get(uint16_t flag)145 FlagStatus fwdgt_flag_get(uint16_t flag)
146 {
147 if(FWDGT_STAT & flag){
148 return SET;
149 }
150
151 return RESET;
152 }
153
