1 /*! 2 \file gd32vf103_fmc.h 3 \brief definitions for the FMC 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2019-09-18, V1.0.1, firmware for GD32VF103 7 \version 2020-02-20, V1.0.2, firmware for GD32VF103 8 \version 2020-08-04, V1.1.0, firmware for GD32VF103 9 */ 10 11 /* 12 Copyright (c) 2020, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32VF103_FMC_H 39 #define GD32VF103_FMC_H 40 41 #include "gd32vf103.h" 42 43 /* FMC and option byte definition */ 44 #define FMC FMC_BASE /*!< FMC register base address */ 45 #define OB OB_BASE /*!< option bytes base address */ 46 47 /* registers definitions */ 48 #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ 49 #define FMC_KEY REG32((FMC) + 0x04U) /*!< FMC unlock key register */ 50 #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ 51 #define FMC_STAT REG32((FMC) + 0x0CU) /*!< FMC status register */ 52 #define FMC_CTL REG32((FMC) + 0x10U) /*!< FMC control register */ 53 #define FMC_ADDR REG32((FMC) + 0x14U) /*!< FMC address register */ 54 #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ 55 #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ 56 #define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ 57 58 #define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ 59 #define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ 60 #define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ 61 #define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ 62 #define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ 63 #define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ 64 65 /* bits definitions */ 66 /* FMC_WS */ 67 #define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ 68 69 /* FMC_KEY */ 70 #define FMC_KEY_KEY BITS(0,31) /*!< FMC_CTL unlock key bits */ 71 72 /* FMC_OBKEY */ 73 #define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ 74 75 /* FMC_STAT */ 76 #define FMC_STAT_BUSY BIT(0) /*!< flash busy flag bit */ 77 #define FMC_STAT_PGERR BIT(2) /*!< flash program error flag bit */ 78 #define FMC_STAT_WPERR BIT(4) /*!< erase/program protection error flag bit */ 79 #define FMC_STAT_ENDF BIT(5) /*!< end of operation flag bit */ 80 81 /* FMC_CTL */ 82 #define FMC_CTL_PG BIT(0) /*!< main flash program command bit */ 83 #define FMC_CTL_PER BIT(1) /*!< main flash page erase command bit */ 84 #define FMC_CTL_MER BIT(2) /*!< main flash mass erase command bit */ 85 #define FMC_CTL_OBPG BIT(4) /*!< option bytes program command bit */ 86 #define FMC_CTL_OBER BIT(5) /*!< option bytes erase command bit */ 87 #define FMC_CTL_START BIT(6) /*!< send erase command to FMC bit */ 88 #define FMC_CTL_LK BIT(7) /*!< FMC_CTL lock bit */ 89 #define FMC_CTL_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ 90 #define FMC_CTL_ERRIE BIT(10) /*!< error interrupt enable bit */ 91 #define FMC_CTL_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ 92 93 /* FMC_ADDR */ 94 #define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ 95 96 /* FMC_OBSTAT */ 97 #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ 98 #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ 99 #define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ 100 #define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ 101 102 /* FMC_WP */ 103 #define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ 104 105 /* FMC_WSEN */ 106 #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ 107 108 /* FMC_PID */ 109 #define FMC_PID_PID BITS(0,31) /*!< product ID bits */ 110 111 /* constants definitions */ 112 /* define the FMC bit position and its register index offset */ 113 #define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 114 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) 115 #define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 116 #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) 117 #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) 118 #define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) 119 #define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) 120 #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) 121 122 /* configuration register */ 123 #define FMC_STAT_REG_OFFSET 0x0CU /*!< status register offset */ 124 #define FMC_CTL_REG_OFFSET 0x10U /*!< control register offset */ 125 #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ 126 127 /* fmc state */ 128 typedef enum 129 { 130 FMC_READY, /*!< the operation has been completed */ 131 FMC_BUSY, /*!< the operation is in progress */ 132 FMC_PGERR, /*!< program error */ 133 FMC_WPERR, /*!< erase/program protection error */ 134 FMC_TOERR, /*!< timeout error */ 135 }fmc_state_enum; 136 137 /* FMC interrupt enable */ 138 typedef enum 139 { 140 FMC_INT_END = FMC_CTL_ENDIE, /*!< enable FMC end of program interrupt */ 141 FMC_INT_ERR = FMC_CTL_ERRIE, /*!< enable FMC error interrupt */ 142 }fmc_int_enum; 143 144 /* FMC flags */ 145 typedef enum 146 { 147 FMC_FLAG_BUSY = FMC_STAT_BUSY, /*!< FMC busy flag */ 148 FMC_FLAG_PGERR = FMC_STAT_PGERR, /*!< FMC operation error flag */ 149 FMC_FLAG_WPERR = FMC_STAT_WPERR, /*!< FMC erase/program protection error flag */ 150 FMC_FLAG_END = FMC_STAT_ENDF, /*!< FMC end of operation flag */ 151 }fmc_flag_enum; 152 153 /* FMC interrupt flags */ 154 typedef enum 155 { 156 FMC_INT_FLAG_PGERR = FMC_STAT_PGERR, /*!< FMC operation error interrupt flag */ 157 FMC_INT_FLAG_WPERR = FMC_STAT_WPERR, /*!< FMC erase/program protection error interrupt flag */ 158 FMC_INT_FLAG_END = FMC_STAT_ENDF, /*!< FMC end of operation interrupt flag */ 159 }fmc_interrupt_flag_enum; 160 161 /* unlock key */ 162 #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ 163 #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ 164 165 /* FMC wait state counter */ 166 #define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) 167 #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ 168 #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ 169 #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ 170 171 /* option bytes software/hardware free watch dog timer */ 172 #define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ 173 #define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ 174 175 /* option bytes reset or not entering deep sleep mode */ 176 #define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ 177 #define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ 178 179 /* option bytes reset or not entering standby mode */ 180 #define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ 181 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ 182 183 /* option bytes boot bank value */ 184 #define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ 185 186 #define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ 187 188 /* read protect configure */ 189 #define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ 190 #define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ 191 192 /* OB_SPC */ 193 #define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ 194 #define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ 195 196 /* OB_USER */ 197 #define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ 198 #define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ 199 200 /* OB_WP0 */ 201 #define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ 202 203 /* OB_WP1 */ 204 #define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ 205 206 /* OB_WP2 */ 207 #define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ 208 209 /* OB_WP3 */ 210 #define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ 211 212 /* option bytes write protection */ 213 #define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ 214 #define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ 215 #define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ 216 #define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ 217 #define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ 218 #define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ 219 #define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ 220 #define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ 221 #define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ 222 #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ 223 #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ 224 #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ 225 #define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ 226 #define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ 227 #define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ 228 #define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ 229 #define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ 230 #define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ 231 #define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ 232 #define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ 233 #define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ 234 #define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ 235 #define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ 236 #define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ 237 #define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ 238 #define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ 239 #define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ 240 #define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ 241 #define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ 242 #define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ 243 #define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ 244 #define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ 245 #define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ 246 247 /* FMC timeout */ 248 #define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ 249 250 /* FMC BANK address */ 251 #define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ 252 #define SRAM_SIZE (*(uint16_t *)0x1FFFF7E2U) /*!< SRAM size*/ 253 254 /* function declarations */ 255 /* FMC main memory programming functions */ 256 /* set the FMC wait state counter */ 257 void fmc_wscnt_set(uint32_t wscnt); 258 /* unlock the main FMC operation */ 259 void fmc_unlock(void); 260 /* lock the main FMC operation */ 261 void fmc_lock(void); 262 /* FMC erase page */ 263 fmc_state_enum fmc_page_erase(uint32_t page_address); 264 /* FMC erase whole chip */ 265 fmc_state_enum fmc_mass_erase(void); 266 /* FMC program a word at the corresponding address */ 267 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); 268 /* FMC program a half word at the corresponding address */ 269 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); 270 271 /* FMC option bytes programming functions */ 272 /* unlock the option byte operation */ 273 void ob_unlock(void); 274 /* lock the option byte operation */ 275 void ob_lock(void); 276 /* erase the FMC option byte */ 277 fmc_state_enum ob_erase(void); 278 /* enable write protection */ 279 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); 280 /* configure security protection */ 281 fmc_state_enum ob_security_protection_config(uint8_t ob_spc); 282 /* program the FMC user option byte */ 283 fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); 284 /* program the FMC data option byte */ 285 fmc_state_enum ob_data_program(uint32_t address, uint8_t data); 286 /* get OB_USER in register FMC_OBSTAT */ 287 uint8_t ob_user_get(void); 288 /* get OB_DATA in register FMC_OBSTAT */ 289 uint16_t ob_data_get(void); 290 /* get the FMC option byte write protection */ 291 uint32_t ob_write_protection_get(void); 292 /* get FMC option byte security protection state */ 293 FlagStatus ob_spc_get(void); 294 295 /* FMC interrupts and flags management functions */ 296 /* enable FMC interrupt */ 297 void fmc_interrupt_enable(fmc_int_enum interrupt); 298 /* disable FMC interrupt */ 299 void fmc_interrupt_disable(fmc_int_enum interrupt); 300 /* check flag is set or not */ 301 FlagStatus fmc_flag_get(fmc_flag_enum flag); 302 /* clear the FMC flag */ 303 void fmc_flag_clear(fmc_flag_enum flag); 304 /* get FMC interrupt flag state */ 305 FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); 306 /* clear FMC interrupt flag state */ 307 void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); 308 /* return the FMC state */ 309 fmc_state_enum fmc_state_get(void); 310 /* check FMC ready or not */ 311 fmc_state_enum fmc_ready_wait(uint32_t timeout); 312 313 #endif /* GD32VF103_FMC_H */ 314
