1 /*! 2 \file gd32l23x_wwdgt.h 3 \brief definitions for the WWDGT 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 36 #ifndef GD32L23X_WWDGT_H 37 #define GD32L23X_WWDGT_H 38 39 #include "gd32l23x.h" 40 41 /* WWDGT definitions */ 42 #define WWDGT WWDGT_BASE 43 44 /* registers definitions */ 45 #define WWDGT_CTL REG32((WWDGT) + 0x00000000U) /*!< WWDGT control register */ 46 #define WWDGT_CFG REG32((WWDGT) + 0x00000004U) /*!< WWDGT configuration register */ 47 #define WWDGT_STAT REG32((WWDGT) + 0x00000008U) /*!< WWDGT status register */ 48 49 /* bits definitions */ 50 /* WWDGT_CTL */ 51 #define WWDGT_CTL_CNT BITS(0,6) /*!< WWDGT counter value */ 52 #define WWDGT_CTL_WDGTEN BIT(7) /*!< WWDGT counter enable */ 53 54 /* WWDGT_CFG */ 55 #define WWDGT_CFG_WIN BITS(0,6) /*!< WWDGT counter window value */ 56 #define WWDGT_CFG_PSC_0_1 BITS(7,8) /*!< WWDGT prescaler divider value low bit */ 57 #define WWDGT_CFG_EWIE BIT(9) /*!< WWDGT early wakeup interrupt enable */ 58 #define WWDGT_CFG_PSC_2_3 BITS(16,17) /*!< WWDGT prescaler divider value high bit */ 59 60 /* WWDGT_STAT */ 61 #define WWDGT_STAT_EWIF BIT(0) /*!< WWDGT early wakeup interrupt flag */ 62 63 /* constants definitions */ 64 #define CFG_PSC(regval1, regval2) ((BITS(7,8) & ((uint32_t)(regval1) << 7U)) | (BITS(16, 17) & ((regval2) << 16))) 65 #define WWDGT_CFG_PSC_DIV1 ((uint32_t)CFG_PSC(0,0)) /*!< the time base of WWDGT = (PCLK1/4096)/1 */ 66 #define WWDGT_CFG_PSC_DIV2 ((uint32_t)CFG_PSC(1,0)) /*!< the time base of WWDGT = (PCLK1/4096)/2 */ 67 #define WWDGT_CFG_PSC_DIV4 ((uint32_t)CFG_PSC(2,0)) /*!< the time base of WWDGT = (PCLK1/4096)/4 */ 68 #define WWDGT_CFG_PSC_DIV8 ((uint32_t)CFG_PSC(3,0)) /*!< the time base of WWDGT = (PCLK1/4096)/8 */ 69 #define WWDGT_CFG_PSC_DIV16 ((uint32_t)CFG_PSC(0,1)) /*!< the time base of WWDGT = (PCLK1/4096)/16 */ 70 #define WWDGT_CFG_PSC_DIV32 ((uint32_t)CFG_PSC(1,1)) /*!< the time base of WWDGT = (PCLK1/4096)/32 */ 71 #define WWDGT_CFG_PSC_DIV64 ((uint32_t)CFG_PSC(2,1)) /*!< the time base of WWDGT = (PCLK1/4096)/64 */ 72 #define WWDGT_CFG_PSC_DIV128 ((uint32_t)CFG_PSC(3,1)) /*!< the time base of WWDGT = (PCLK1/4096)/128 */ 73 #define WWDGT_CFG_PSC_DIV256 ((uint32_t)CFG_PSC(0,2)) /*!< the time base of WWDGT = (PCLK1/4096)/256 */ 74 #define WWDGT_CFG_PSC_DIV512 ((uint32_t)CFG_PSC(1,2)) /*!< the time base of WWDGT = (PCLK1/4096)/512 */ 75 #define WWDGT_CFG_PSC_DIV1024 ((uint32_t)CFG_PSC(2,2)) /*!< the time base of WWDGT = (PCLK1/4096)/1024 */ 76 #define WWDGT_CFG_PSC_DIV2048 ((uint32_t)CFG_PSC(3,2)) /*!< the time base of WWDGT = (PCLK1/4096)/2048 */ 77 #define WWDGT_CFG_PSC_DIV4096 ((uint32_t)CFG_PSC(0,3)) /*!< the time base of WWDGT = (PCLK1/4096)/4096 */ 78 #define WWDGT_CFG_PSC_DIV8192 ((uint32_t)CFG_PSC(1,3)) /*!< the time base of WWDGT = (PCLK1/4096)/8192 */ 79 80 /* function declarations */ 81 /* reset the WWDGT configuration */ 82 void wwdgt_deinit(void); 83 /* start the WWDGT counter */ 84 void wwdgt_enable(void); 85 86 /* configure the WWDGT counter prescaler value */ 87 void wwdgt_prescaler_value_config(uint16_t prescaler); 88 /* configure the WWDGT counter window value */ 89 void wwdgt_window_value_config(uint16_t window); 90 /* configure the WWDGT counter value */ 91 void wwdgt_counter_update(uint16_t counter_value); 92 /* configure counter value, window value, and prescaler divider value */ 93 void wwdgt_config(uint16_t counter, uint16_t window, uint32_t prescaler); 94 95 /* enable early wakeup interrupt of WWDGT */ 96 void wwdgt_interrupt_enable(void); 97 /* check early wakeup interrupt state of WWDGT */ 98 FlagStatus wwdgt_flag_get(void); 99 /* clear early wakeup interrupt state of WWDGT */ 100 void wwdgt_flag_clear(void); 101 102 #endif /* GD32L23X_WWDGT_H */ 103
