1 /*! 2 \file gd32l23x_timer.h 3 \brief definitions for the TIMER 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_TIMER_H 36 #define GD32L23X_TIMER_H 37 38 #include "gd32l23x.h" 39 40 /* TIMERx(x=1,2,5,6,8,11) definitions */ 41 #define TIMER1 (TIMER_BASE + 0x00000000U) 42 #define TIMER2 (TIMER_BASE + 0x00000400U) 43 #define TIMER5 (TIMER_BASE + 0x00001000U) 44 #define TIMER6 (TIMER_BASE + 0x00001400U) 45 #define TIMER8 (TIMER_BASE + 0x00014C00U) 46 #define TIMER11 (TIMER_BASE + 0x00001800U) 47 48 /* registers definitions */ 49 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ 50 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ 51 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ 52 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ 53 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ 54 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ 55 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ 56 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ 57 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ 58 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ 59 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ 60 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ 61 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ 62 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ 63 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ 64 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ 65 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ 66 #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ 67 #define TIMER_IRMP(timerx) REG32((timerx) + 0x50U) /*!< TIMER channel input remap register */ 68 #define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ 69 70 /* bits definitions */ 71 /* TIMER_CTL0 */ 72 #define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ 73 #define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ 74 #define TIMER_CTL0_UPS BIT(2) /*!< update source */ 75 #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ 76 #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ 77 #define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ 78 #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ 79 #define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ 80 81 /* TIMER_CTL1 */ 82 #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ 83 #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ 84 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ 85 86 /* TIMER_SMCFG */ 87 #define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ 88 #define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ 89 #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ 90 #define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ 91 #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ 92 #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ 93 #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ 94 95 /* TIMER_DMAINTEN */ 96 #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ 97 #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ 98 #define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ 99 #define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ 100 #define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ 101 #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ 102 #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ 103 #define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ 104 #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ 105 #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ 106 #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ 107 #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ 108 109 /* TIMER_INTF */ 110 #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ 111 #define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ 112 #define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ 113 #define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ 114 #define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ 115 #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ 116 #define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 overcapture flag */ 117 #define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 overcapture flag */ 118 #define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 overcapture flag */ 119 #define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 overcapture flag */ 120 121 /* TIMER_SWEVG */ 122 #define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ 123 #define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ 124 #define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ 125 #define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ 126 #define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ 127 #define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ 128 129 /* TIMER_CHCTL0 */ 130 /* output compare mode */ 131 #define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ 132 #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ 133 #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ 134 #define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ 135 #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ 136 #define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ 137 #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ 138 #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ 139 #define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ 140 #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ 141 /* input capture mode */ 142 #define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ 143 #define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ 144 #define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ 145 #define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ 146 147 /* TIMER_CHCTL1 */ 148 /* output compare mode */ 149 #define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ 150 #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ 151 #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ 152 #define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ 153 #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ 154 #define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ 155 #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ 156 #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ 157 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ 158 #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ 159 /* input capture mode */ 160 #define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ 161 #define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ 162 #define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ 163 #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ 164 165 /* TIMER_CHCTL2 */ 166 #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ 167 #define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ 168 #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ 169 #define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ 170 #define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ 171 #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ 172 #define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ 173 #define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ 174 #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ 175 #define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ 176 #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ 177 #define TIMER_CHCTL2_CH3NP BIT(15) /*!< channel 3 complementary output polarity */ 178 179 /* TIMER_CNT */ 180 #define TIMER_CNT_CNT BITS(0,15) /*!< timer counter */ 181 182 /* TIMER_PSC */ 183 #define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ 184 185 /* TIMER_CAR */ 186 #define TIMER_CAR_CARL BITS(0,15) /*!< counter auto reload value */ 187 188 /* TIMER_CH0CV */ 189 #define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< capture/compare value of channel 0 */ 190 191 /* TIMER_CH1CV */ 192 #define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< capture/compare value of channel 1 */ 193 194 /* TIMER_CH2CV */ 195 #define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< capture/compare value of channel 2 */ 196 197 /* TIMER_CH3CV */ 198 #define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< capture/compare value of channel 3 */ 199 200 /* TIMER_DMACFG */ 201 #define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ 202 #define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ 203 204 /* TIMER_DMATB */ 205 #define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ 206 207 /* TIMER_CFG */ 208 #define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ 209 210 /* constants definitions */ 211 /* TIMER init parameter struct definitions */ 212 typedef struct { 213 uint16_t prescaler; /*!< prescaler value */ 214 uint16_t alignedmode; /*!< aligned mode */ 215 uint16_t counterdirection; /*!< counter direction */ 216 uint32_t period; /*!< period value */ 217 uint16_t clockdivision; /*!< clock division value */ 218 } timer_parameter_struct; 219 220 /* channel output parameter struct definitions */ 221 typedef struct { 222 uint32_t outputstate; /*!< channel output state */ 223 uint16_t ocpolarity; /*!< channel output polarity */ 224 } timer_oc_parameter_struct; 225 226 /* channel input parameter struct definitions */ 227 typedef struct { 228 uint16_t icpolarity; /*!< channel input polarity */ 229 uint16_t icselection; /*!< channel input mode selection */ 230 uint16_t icprescaler; /*!< channel input capture prescaler */ 231 uint16_t icfilter; /*!< channel input capture filter control */ 232 } timer_ic_parameter_struct; 233 234 /* TIMER interrupt enable or disable */ 235 #define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ 236 #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ 237 #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ 238 #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ 239 #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ 240 #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ 241 242 /* TIMER flag */ 243 #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ 244 #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ 245 #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ 246 #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ 247 #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ 248 #define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ 249 #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ 250 #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ 251 #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ 252 #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ 253 254 /* TIMER interrupt flag */ 255 #define TIMER_INT_FLAG_UP TIMER_INTF_UPIF /*!< update interrupt flag */ 256 #define TIMER_INT_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 interrupt flag */ 257 #define TIMER_INT_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 interrupt flag */ 258 #define TIMER_INT_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 interrupt flag */ 259 #define TIMER_INT_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 interrupt flag */ 260 #define TIMER_INT_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger interrupt flag */ 261 262 /* TIMER DMA source enable */ 263 #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ 264 #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ 265 #define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ 266 #define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ 267 #define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ 268 #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ 269 270 /* channel DMA request source selection */ 271 #define TIMER_DMAREQUEST_UPDATEEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel y is sent when update event occurs */ 272 #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000001U) /*!< DMA request of channel y is sent when channel y event occurs */ 273 274 /* DMA access base address */ 275 #define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) 276 #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ 277 #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ 278 #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ 279 #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ 280 #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ 281 #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ 282 #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ 283 #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ 284 #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ 285 #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ 286 #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ 287 #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ 288 #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ 289 #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ 290 #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ 291 #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ 292 293 /* DMA access burst length */ 294 #define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) 295 #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ 296 #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ 297 #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ 298 #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ 299 #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ 300 #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ 301 #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ 302 #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ 303 #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ 304 #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ 305 #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ 306 #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ 307 #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ 308 #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ 309 #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ 310 #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ 311 #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ 312 313 /* TIMER software event generation source */ 314 #define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ 315 #define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ 316 #define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ 317 #define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ 318 #define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ 319 #define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ 320 321 /* center-aligned mode selection */ 322 #define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) 323 #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ 324 #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ 325 #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ 326 #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ 327 328 /* TIMER prescaler reload mode */ 329 #define TIMER_PSC_RELOAD_NOW ((uint32_t)0x00000000U) /*!< the prescaler is loaded right now */ 330 #define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000001U) /*!< the prescaler is loaded at the next update event */ 331 332 /* count direction */ 333 #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ 334 #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ 335 336 /* specify division ratio between TIMER clock and dead-time and sampling clock */ 337 #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) 338 #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ 339 #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ 340 #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ 341 342 /* single pulse mode */ 343 #define TIMER_SP_MODE_SINGLE ((uint32_t)0x00000000U) /*!< single pulse mode */ 344 #define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000001U) /*!< repetitive pulse mode */ 345 346 /* update source */ 347 #define TIMER_UPDATE_SRC_REGULAR ((uint32_t)0x00000000U) /*!< update generate only by counter overflow/underflow */ 348 #define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000001U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ 349 350 /* TIMER channel n(n=0,1,2,3) */ 351 #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=1,2,8,11)) */ 352 #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=1,2,8,11)) */ 353 #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=1,2)) */ 354 #define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=1,2)) */ 355 356 /* channel enable state */ 357 #define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ 358 #define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ 359 360 /* channel output polarity */ 361 #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ 362 #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ 363 364 /* channel output compare mode */ 365 #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ 366 #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ 367 #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ 368 #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ 369 #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ 370 #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ 371 #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ 372 #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode*/ 373 374 /* channel output compare shadow enable */ 375 #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ 376 #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ 377 378 /* channel output compare fast enable */ 379 #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ 380 #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ 381 382 /* channel output compare clear enable */ 383 #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ 384 #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ 385 386 /* channel input capture polarity */ 387 #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ 388 #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ 389 #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge */ 390 391 /* TIMER input capture selection */ 392 #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel y is configured as input and icy is mapped on CIy */ 393 #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel y is configured as input and icy is mapped on opposite input */ 394 #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel y is configured as input and icy is mapped on ITS */ 395 396 /* channel input capture prescaler */ 397 #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ 398 #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ 399 #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ 400 #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ 401 402 /* trigger selection */ 403 #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) 404 #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ 405 #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ 406 #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ 407 #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ 408 #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ 409 #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ 410 #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ 411 412 /* master mode control */ 413 #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) 414 #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ 415 #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ 416 #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ 417 #define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ 418 #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ 419 #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ 420 #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ 421 #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ 422 423 /* slave mode control */ 424 #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) 425 #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ 426 #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ 427 #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ 428 #define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ 429 #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ 430 #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ 431 #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ 432 #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ 433 434 /* master slave mode selection */ 435 #define TIMER_MASTER_SLAVE_MODE_ENABLE ((uint32_t)0x00000000U) /*!< master slave mode enable */ 436 #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000001U) /*!< master slave mode disable */ 437 438 /* external trigger prescaler */ 439 #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) 440 #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ 441 #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ 442 #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ 443 #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ 444 445 /* external trigger polarity */ 446 #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ 447 #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ 448 449 /* channel 0 trigger input selection */ 450 #define TIMER_HALLINTERFACE_ENABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode enable */ 451 #define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000001U) /*!< TIMER hall sensor mode disable */ 452 453 /* TIMERx(x=1,2,8,11) write cc register selection */ 454 #define TIMER_CHVSEL_ENABLE ((uint16_t)0x0002U) /*!< write CHxVAL register selection enable */ 455 #define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ 456 457 #define TIMER8_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) 458 #define TIMER8_CI0_RMP_GPIO TIMER8_IRMP(0) /*!< timer8 channel 0 input is connected to GPIO(TIMER8_CH0) */ 459 #define TIMER8_CI0_RMP_LXTAL TIMER8_IRMP(1) /*!< timer8 channel 0 input is connected to the LXTAL */ 460 #define TIMER8_CI0_RMP_HXTAL_DIV32 TIMER8_IRMP(2) /*!< timer8 channel 0 input is connected to HXTAL/32 clock */ 461 #define TIMER8_CI0_RMP_CKOUTSEL TIMER8_IRMP(3) /*!< timer8 channel 0 input is connected to CKOUTSEL */ 462 463 #define TIMER11_IRMP(regval) (BITS(0, 1) & ((uint32_t)(regval) << 0U)) 464 #define TIMER11_CI0_RMP_GPIO TIMER8_IRMP(0) /*!< timer11 channel 0 input is connected to GPIO(TIMER11_CH0) */ 465 #define TIMER11_CI0_RMP_IRC32K TIMER8_IRMP(1) /*!< timer11 channel 0 input is connected to the IRC32K */ 466 #define TIMER11_CI0_RMP_LXTAL TIMER8_IRMP(2) /*!< timer11 channel 0 input is connected to LXTAL clock */ 467 #define TIMER11_CI0_RMP_RTC_OUT TIMER8_IRMP(3) /*!< timer11 channel 0 input is connected to RTC_OUT */ 468 469 /* function declarations */ 470 /* TIMER timebase */ 471 /* deinit a TIMER */ 472 void timer_deinit(uint32_t timer_periph); 473 /* initialize TIMER init parameter struct */ 474 void timer_struct_para_init(timer_parameter_struct *initpara); 475 /* initialize TIMER counter */ 476 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara); 477 /* enable a TIMER */ 478 void timer_enable(uint32_t timer_periph); 479 /* disable a TIMER */ 480 void timer_disable(uint32_t timer_periph); 481 /* enable the auto reload shadow function */ 482 void timer_auto_reload_shadow_enable(uint32_t timer_periph); 483 /* disable the auto reload shadow function */ 484 void timer_auto_reload_shadow_disable(uint32_t timer_periph); 485 /* enable the update event */ 486 void timer_update_event_enable(uint32_t timer_periph); 487 /* disable the update event */ 488 void timer_update_event_disable(uint32_t timer_periph); 489 /* set TIMER counter alignment mode */ 490 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); 491 /* set TIMER counter up direction */ 492 void timer_counter_up_direction(uint32_t timer_periph); 493 /* set TIMER counter down direction */ 494 void timer_counter_down_direction(uint32_t timer_periph); 495 496 /* configure TIMER prescaler */ 497 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); 498 /* configure TIMER autoreload register value */ 499 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload); 500 /* configure TIMER counter register value */ 501 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter); 502 /* read TIMER counter value */ 503 uint32_t timer_counter_read(uint32_t timer_periph); 504 /* read TIMER prescaler value */ 505 uint16_t timer_prescaler_read(uint32_t timer_periph); 506 /* configure TIMER single pulse mode */ 507 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); 508 /* configure TIMER update source */ 509 void timer_update_source_config(uint32_t timer_periph, uint32_t update); 510 511 /* TIMER DMA and event */ 512 /* enable the TIMER DMA */ 513 void timer_dma_enable(uint32_t timer_periph, uint16_t dma); 514 /* disable the TIMER DMA */ 515 void timer_dma_disable(uint32_t timer_periph, uint16_t dma); 516 /* channel DMA request source selection */ 517 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); 518 /* configure the TIMER DMA transfer */ 519 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); 520 /* software generate events */ 521 void timer_event_software_generate(uint32_t timer_periph, uint16_t event); 522 523 /* TIMER channel output */ 524 /* initialize TIMER channel output parameter struct */ 525 void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara); 526 /* configure TIMER channel output function */ 527 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara); 528 /* configure TIMER channel output compare mode */ 529 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); 530 /* configure TIMER channel output pulse value */ 531 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); 532 /* configure TIMER channel output shadow function */ 533 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); 534 /* configure TIMER channel output fast function */ 535 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); 536 /* configure TIMER channel output clear function */ 537 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); 538 /* configure TIMER channel output polarity */ 539 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); 540 /* configure TIMER channel enable state */ 541 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); 542 543 /* TIMER channel input */ 544 /* initialize TIMER channel input parameter struct */ 545 void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara); 546 /* configure TIMER input capture parameter */ 547 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara); 548 /* configure TIMER channel input capture prescaler value */ 549 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); 550 /* read TIMER channel capture compare register value */ 551 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); 552 /* configure TIMER input pwm capture function */ 553 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm); 554 /* configure TIMER hall sensor mode */ 555 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); 556 557 /* TIMER master and slave mode */ 558 /* select TIMER input trigger source */ 559 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); 560 /* select TIMER master mode output trigger source */ 561 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); 562 /* select TIMER slave mode */ 563 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); 564 /* configure TIMER master slave mode */ 565 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); 566 /* configure TIMER external trigger input */ 567 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 568 /* configure TIMER quadrature decoder mode */ 569 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); 570 /* configure TIMER the internal trigger as external clock input */ 571 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); 572 /* configure TIMER the external trigger as external clock input */ 573 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); 574 /* configure TIMER the external clock mode 0 */ 575 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 576 /* configure TIMER the external clock mode 1 */ 577 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 578 /* disable TIMER the external clock mode 1 */ 579 void timer_external_clock_mode1_disable(uint32_t timer_periph); 580 581 /* TIMER configure */ 582 /* configure TIMER write CHxVAL register selection */ 583 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); 584 585 /* TIMER interrupt and flag*/ 586 /* get TIMER flags */ 587 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); 588 /* clear TIMER flags */ 589 void timer_flag_clear(uint32_t timer_periph, uint32_t flag); 590 /* enable the TIMER interrupt */ 591 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); 592 /* disable the TIMER interrupt */ 593 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); 594 /* get timer interrupt flag */ 595 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t int_flag); 596 /* clear TIMER interrupt flag */ 597 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t int_flag); 598 599 #endif /* GD32L23X_TIMER_H */ 600
