1 /*! 2 \file gd32l23x_lpuart.h 3 \brief definitions for the LPUART 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_LPUART_H 36 #define GD32L23X_LPUART_H 37 38 #include "gd32l23x.h" 39 40 /* LPUART definitions */ 41 #define LPUART LPUART_BASE 42 43 /* registers definitions */ 44 #define LPUART_CTL0 REG32(LPUART + 0x00000000U) /*!< LPUART control register 0 */ 45 #define LPUART_CTL1 REG32(LPUART + 0x00000004U) /*!< LPUART control register 1 */ 46 #define LPUART_CTL2 REG32(LPUART + 0x00000008U) /*!< LPUART control register 2 */ 47 #define LPUART_BAUD REG32(LPUART + 0x0000000CU) /*!< LPUART baud rate register */ 48 #define LPUART_CMD REG32(LPUART + 0x00000018U) /*!< LPUART command register */ 49 #define LPUART_STAT REG32(LPUART + 0x0000001CU) /*!< LPUART status register */ 50 #define LPUART_INTC REG32(LPUART + 0x00000020U) /*!< LPUART status clear register */ 51 #define LPUART_RDATA REG32(LPUART + 0x00000024U) /*!< LPUART receive data register */ 52 #define LPUART_TDATA REG32(LPUART + 0x00000028U) /*!< LPUART transmit data register */ 53 #define LPUART_CHC REG32(LPUART + 0x000000C0U) /*!< LPUART coherence control register */ 54 55 /* bits definitions */ 56 /* LPUART CTL0 */ 57 #define LPUART_CTL0_UEN BIT(0) /*!< LPUART enable */ 58 #define LPUART_CTL0_UESM BIT(1) /*!< LPUART enable in deep-sleep mode */ 59 #define LPUART_CTL0_REN BIT(2) /*!< receiver enable */ 60 #define LPUART_CTL0_TEN BIT(3) /*!< transmitter enable */ 61 #define LPUART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 62 #define LPUART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 63 #define LPUART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 64 #define LPUART_CTL0_TBEIE BIT(7) /*!< transmitter register empty interrupt enable */ 65 #define LPUART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 66 #define LPUART_CTL0_PM BIT(9) /*!< parity mode */ 67 #define LPUART_CTL0_PCEN BIT(10) /*!< parity control enable */ 68 #define LPUART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 69 #define LPUART_CTL0_WL0 BIT(12) /*!< word length low bit*/ 70 #define LPUART_CTL0_MEN BIT(13) /*!< mute mode enable */ 71 #define LPUART_CTL0_AMIE BIT(14) /*!< address match interrupt enable */ 72 #define LPUART_CTL0_DED BITS(16,20) /*!< driver enable deassertion time */ 73 #define LPUART_CTL0_DEA BITS(21,25) /*!< driver enable assertion time */ 74 #define LPUART_CTL0_WL1 BIT(28) /*!< word length high bit*/ 75 76 /* LPUART CTL1 */ 77 #define LPUART_CTL1_ADDM BIT(4) /*!< address detection mode */ 78 #define LPUART_CTL1_STB BITS(12,13) /*!< stop bits length */ 79 #define LPUART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ 80 #define LPUART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ 81 #define LPUART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ 82 #define LPUART_CTL1_DINV BIT(18) /*!< data bit level inversion */ 83 #define LPUART_CTL1_MSBF BIT(19) /*!< most significant bit first */ 84 #define LPUART_CTL1_ADDR BITS(24,31) /*!< address of the LPUART terminal */ 85 86 /* LPUART CTL2 */ 87 #define LPUART_CTL2_ERRIE BIT(0) /*!< error interrupt enable in multibuffer communication */ 88 #define LPUART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 89 #define LPUART_CTL2_DENR BIT(6) /*!< DMA enable for reception */ 90 #define LPUART_CTL2_DENT BIT(7) /*!< DMA enable for transmission */ 91 #define LPUART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 92 #define LPUART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 93 #define LPUART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 94 #define LPUART_CTL2_OVRD BIT(12) /*!< overrun disable */ 95 #define LPUART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ 96 #define LPUART_CTL2_DEM BIT(14) /*!< driver enable mode */ 97 #define LPUART_CTL2_DEP BIT(15) /*!< driver enable polarity mode */ 98 #define LPUART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ 99 #define LPUART_CTL2_WUIE BIT(22) /*!< wakeup from deep-sleep mode interrupt enable */ 100 #define LPUART_CTL2_UCESM BIT(23) /*!< LPUART clock enable in Deep-sleep mode */ 101 102 /* LPUART BAUD */ 103 #define LPUART_BAUD_BRR BITS(0,19) /*!< baud-rate divider */ 104 105 /* LPUART CMD */ 106 #define LPUART_CMD_MMCMD BIT(2) /*!< mute mode command */ 107 #define LPUART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ 108 109 /* LPUART STAT */ 110 #define LPUART_STAT_PERR BIT(0) /*!< parity error flag */ 111 #define LPUART_STAT_FERR BIT(1) /*!< frame error flag */ 112 #define LPUART_STAT_NERR BIT(2) /*!< noise error flag */ 113 #define LPUART_STAT_ORERR BIT(3) /*!< overrun error */ 114 #define LPUART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ 115 #define LPUART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ 116 #define LPUART_STAT_TC BIT(6) /*!< transmission completed */ 117 #define LPUART_STAT_TBE BIT(7) /*!< transmit data register empty */ 118 #define LPUART_STAT_CTSF BIT(9) /*!< CTS change flag */ 119 #define LPUART_STAT_CTS BIT(10) /*!< CTS level */ 120 #define LPUART_STAT_BSY BIT(16) /*!< busy flag */ 121 #define LPUART_STAT_AMF BIT(17) /*!< address match flag */ 122 #define LPUART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ 123 #define LPUART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ 124 #define LPUART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ 125 #define LPUART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ 126 127 /* LPUART INTC */ 128 #define LPUART_INTC_PEC BIT(0) /*!< parity error clear */ 129 #define LPUART_INTC_FEC BIT(1) /*!< frame error flag clear */ 130 #define LPUART_INTC_NEC BIT(2) /*!< noise detected clear */ 131 #define LPUART_INTC_OREC BIT(3) /*!< overrun error clear */ 132 #define LPUART_INTC_IDLEC BIT(4) /*!< idle line detected clear */ 133 #define LPUART_INTC_TCC BIT(6) /*!< transmission complete clear */ 134 #define LPUART_INTC_CTSC BIT(9) /*!< CTS change clear */ 135 #define LPUART_INTC_AMC BIT(17) /*!< address match clear */ 136 #define LPUART_INTC_WUC BIT(20) /*!< wakeup from deep-sleep mode clear */ 137 138 /* LPUART RDATA */ 139 #define LPUART_RDATA_RDATA BITS(0,8) /*!< receive data value */ 140 141 /* LPUART TDATA */ 142 #define LPUART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ 143 144 /* LPUART CHC */ 145 #define LPUART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ 146 #define LPUART_CHC_EPERR BIT(8) /*!< early parity error flag */ 147 148 /* constants definitions */ 149 /* define the LPUART bit position and its register index offset */ 150 #define LPUART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 151 #define LPUART_REG_VAL(lpuart, offset) (REG32((lpuart) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 152 #define LPUART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 153 #define LPUART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 154 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 155 #define LPUART_REG_VAL2(lpuart, offset) (REG32((lpuart) + ((uint32_t)(offset) >> 22))) 156 #define LPUART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 157 158 /* register offset */ 159 #define LPUART_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ 160 #define LPUART_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ 161 #define LPUART_CTL2_REG_OFFSET ((uint32_t)0x00000008U) /*!< CTL2 register offset */ 162 #define LPUART_STAT_REG_OFFSET ((uint32_t)0x0000001CU) /*!< STAT register offset */ 163 #define LPUART_CHC_REG_OFFSET ((uint32_t)0x000000C0U) /*!< CHC register offset */ 164 165 /* LPUART flags */ 166 typedef enum { 167 /* flags in STAT register */ 168 LPUART_FLAG_REA = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ 169 LPUART_FLAG_TEA = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ 170 LPUART_FLAG_WU = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 20U), /*!< wakeup from Deep-sleep mode flag */ 171 LPUART_FLAG_RWU = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ 172 LPUART_FLAG_AM = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ 173 LPUART_FLAG_BSY = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 16U), /*!< busy flag */ 174 LPUART_FLAG_CTS = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 10U), /*!< CTS level */ 175 LPUART_FLAG_CTSF = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ 176 LPUART_FLAG_TBE = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 177 LPUART_FLAG_TC = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ 178 LPUART_FLAG_RBNE = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ 179 LPUART_FLAG_IDLE = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ 180 LPUART_FLAG_ORERR = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 3U), /*!< overrun error */ 181 LPUART_FLAG_NERR = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ 182 LPUART_FLAG_FERR = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ 183 LPUART_FLAG_PERR = LPUART_REGIDX_BIT(LPUART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ 184 /* flags in CHC register */ 185 LPUART_FLAG_EPERR = LPUART_REGIDX_BIT(LPUART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ 186 } lpuart_flag_enum; 187 188 /* LPUART interrupt flags */ 189 typedef enum { 190 /* interrupt flags in CTL0 register */ 191 LPUART_INT_FLAG_AM = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 14U, LPUART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ 192 LPUART_INT_FLAG_PERR = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 8U, LPUART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 193 LPUART_INT_FLAG_TBE = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 7U, LPUART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 194 LPUART_INT_FLAG_TC = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 6U, LPUART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 195 LPUART_INT_FLAG_RBNE = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 5U, LPUART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 196 LPUART_INT_FLAG_RBNE_ORERR = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 5U, LPUART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 197 LPUART_INT_FLAG_IDLE = LPUART_REGIDX_BIT2(LPUART_CTL0_REG_OFFSET, 4U, LPUART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 198 /* interrupt flags in CTL2 register */ 199 LPUART_INT_FLAG_WU = LPUART_REGIDX_BIT2(LPUART_CTL2_REG_OFFSET, 22U, LPUART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ 200 LPUART_INT_FLAG_CTS = LPUART_REGIDX_BIT2(LPUART_CTL2_REG_OFFSET, 10U, LPUART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 201 LPUART_INT_FLAG_ERR_NERR = LPUART_REGIDX_BIT2(LPUART_CTL2_REG_OFFSET, 0U, LPUART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 202 LPUART_INT_FLAG_ERR_ORERR = LPUART_REGIDX_BIT2(LPUART_CTL2_REG_OFFSET, 0U, LPUART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error flag */ 203 LPUART_INT_FLAG_ERR_FERR = LPUART_REGIDX_BIT2(LPUART_CTL2_REG_OFFSET, 0U, LPUART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 204 } lpuart_interrupt_flag_enum; 205 206 /* LPUART interrupt enable or disable */ 207 typedef enum { 208 /* interrupt in CTL0 register */ 209 LPUART_INT_AM = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ 210 LPUART_INT_PERR = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 211 LPUART_INT_TBE = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 212 LPUART_INT_TC = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 213 LPUART_INT_RBNE = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 214 LPUART_INT_IDLE = LPUART_REGIDX_BIT(LPUART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 215 /* interrupt in CTL2 register */ 216 LPUART_INT_WU = LPUART_REGIDX_BIT(LPUART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ 217 LPUART_INT_CTS = LPUART_REGIDX_BIT(LPUART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 218 LPUART_INT_ERR = LPUART_REGIDX_BIT(LPUART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 219 } lpuart_interrupt_enum; 220 221 /* LPUART invert configure */ 222 typedef enum { 223 /* data bit level inversion */ 224 LPUART_DINV_ENABLE = 0, /*!< data bit level inversion */ 225 LPUART_DINV_DISABLE, /*!< data bit level not inversion */ 226 /* TX pin level inversion */ 227 LPUART_TXPIN_ENABLE, /*!< TX pin level inversion */ 228 LPUART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 229 /* RX pin level inversion */ 230 LPUART_RXPIN_ENABLE, /*!< RX pin level inversion */ 231 LPUART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 232 /* swap TX/RX pins */ 233 LPUART_SWAP_ENABLE, /*!< swap TX/RX pins */ 234 LPUART_SWAP_DISABLE, /*!< not swap TX/RX pins */ 235 } lpuart_invert_enum; 236 237 /* LPUART receiver configure */ 238 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 239 #define LPUART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 240 #define LPUART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 241 242 /* LPUART transmitter configure */ 243 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 244 #define LPUART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 245 #define LPUART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 246 247 /* LPUART parity bits definitions */ 248 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 249 #define LPUART_PM_NONE CTL0_PM(0) /*!< no parity */ 250 #define LPUART_PM_EVEN CTL0_PM(2) /*!< even parity */ 251 #define LPUART_PM_ODD CTL0_PM(3) /*!< odd parity */ 252 253 /* LPUART wakeup method in mute mode */ 254 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 255 #define LPUART_WM_IDLE CTL0_WM(0) /*!< idle line */ 256 #define LPUART_WM_ADDR CTL0_WM(1) /*!< address match */ 257 258 /* LPUART word length definitions */ 259 #define CTL0_WL01(regval1, regval2) ((BIT(12) & ((uint32_t)(regval1) << 12))|(BIT(28) & ((uint32_t)(regval2) << 28))) 260 #define LPUART_WL_7BIT CTL0_WL01(0,1) /*!< 7 bits */ 261 #define LPUART_WL_8BIT CTL0_WL01(0,0) /*!< 8 bits */ 262 #define LPUART_WL_9BIT CTL0_WL01(1,0) /*!< 9 bits */ 263 264 /* LPUART address detection mode */ 265 #define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) 266 #define LPUART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ 267 #define LPUART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ 268 269 /* LPUART stop bits definitions */ 270 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 271 #define LPUART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 272 #define LPUART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 273 274 /* LPUART data is transmitted/received with the LSB/MSB first */ 275 #define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) 276 #define LPUART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ 277 #define LPUART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ 278 279 /* DMA enable for reception */ 280 #define CTL2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 281 #define LPUART_DENR_ENABLE CTL2_DENR(1) /*!< enable for reception */ 282 #define LPUART_DENR_DISABLE CTL2_DENR(0) /*!< disable for reception */ 283 284 /* DMA enable for transmission */ 285 #define CTL2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 286 #define LPUART_DENT_ENABLE CTL2_DENT(1) /*!< enable for transmission */ 287 #define LPUART_DENT_DISABLE CTL2_DENT(0) /*!< disable for transmission */ 288 289 /* LPUART RTS hardware flow control configure */ 290 #define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 291 #define LPUART_RTS_ENABLE CTL2_RTSEN(1) /*!< RTS hardware flow control enabled */ 292 #define LPUART_RTS_DISABLE CTL2_RTSEN(0) /*!< RTS hardware flow control disabled */ 293 294 /* LPUART CTS hardware flow control configure */ 295 #define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 296 #define LPUART_CTS_ENABLE CTL2_CTSEN(1) /*!< CTS hardware flow control enabled */ 297 #define LPUART_CTS_DISABLE CTL2_CTSEN(0) /*!< CTS hardware flow control disabled */ 298 299 /* LPUART driver enable polarity mode */ 300 #define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 301 #define LPUART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ 302 #define LPUART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ 303 304 /* LPUART wakeup mode from deep-sleep mode */ 305 #define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 306 #define LPUART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ 307 #define LPUART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ 308 #define LPUART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ 309 310 /* LPUART hardware flow control coherence mode */ 311 #define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) 312 #define LPUART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ 313 #define LPUART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ 314 315 /* function declarations */ 316 /* initialization functions */ 317 /* reset LPUART */ 318 void lpuart_deinit(void); 319 /* configure LPUART baud rate value */ 320 void lpuart_baudrate_set(uint32_t baudval); 321 /* configure LPUART parity */ 322 void lpuart_parity_config(uint32_t paritycfg); 323 /* configure LPUART word length */ 324 void lpuart_word_length_set(uint32_t wlen); 325 /* configure LPUART stop bit length */ 326 void lpuart_stop_bit_set(uint32_t stblen); 327 /* enable LPUART */ 328 void lpuart_enable(void); 329 /* disable LPUART */ 330 void lpuart_disable(void); 331 /* configure LPUART transmitter */ 332 void lpuart_transmit_config(uint32_t txconfig); 333 /* configure LPUART receiver */ 334 void lpuart_receive_config(uint32_t rxconfig); 335 336 /* LPUART normal mode communication */ 337 /* data is transmitted/received with the LSB/MSB first */ 338 void lpuart_data_first_config(uint32_t msbf); 339 /* configure LPUART inverted */ 340 void lpuart_invert_config(lpuart_invert_enum invertpara); 341 /* enable the LPUART overrun function */ 342 void lpuart_overrun_enable(void); 343 /* disable the LPUART overrun function */ 344 void lpuart_overrun_disable(void); 345 /* LPUART transmit data function */ 346 void lpuart_data_transmit(uint32_t data); 347 /* LPUART receive data function */ 348 uint16_t lpuart_data_receive(void); 349 /* enable LPUART command */ 350 void lpuart_command_enable(uint32_t cmdtype); 351 352 /* multi-processor communication */ 353 /* configure address of the LPUART */ 354 void lpuart_address_config(uint8_t addr); 355 /* configure address detection mode */ 356 void lpuart_address_detection_mode_config(uint32_t addmod); 357 /* enable mute mode */ 358 void lpuart_mute_mode_enable(void); 359 /* disable mute mode */ 360 void lpuart_mute_mode_disable(void); 361 /* configure wakeup method in mute mode */ 362 void lpuart_mute_mode_wakeup_config(uint32_t wmethod); 363 364 /* half-duplex communication */ 365 /* enable half-duplex mode */ 366 void lpuart_halfduplex_enable(void); 367 /* disable half-duplex mode */ 368 void lpuart_halfduplex_disable(void); 369 370 /* hardware flow communication */ 371 /* configure hardware flow control RTS */ 372 void lpuart_hardware_flow_rts_config(uint32_t rtsconfig); 373 /* configure hardware flow control CTS */ 374 void lpuart_hardware_flow_cts_config(uint32_t ctsconfig); 375 376 /* coherence control */ 377 /* configure hardware flow control coherence mode */ 378 void lpuart_hardware_flow_coherence_config(uint32_t hcm); 379 380 /* enable RS485 driver */ 381 void lpuart_rs485_driver_enable(void); 382 /* disable RS485 driver */ 383 void lpuart_rs485_driver_disable(void); 384 /* configure driver enable assertion time */ 385 void lpuart_driver_assertime_config(uint32_t deatime); 386 /* configure driver enable de-assertion time */ 387 void lpuart_driver_deassertime_config(uint32_t dedtime); 388 /* configure driver enable polarity mode */ 389 void lpuart_depolarity_config(uint32_t dep); 390 391 /* LPUART DMA */ 392 /* configure LPUART DMA for reception */ 393 void lpuart_dma_receive_config(uint32_t dmacmd); 394 /* configure LPUART DMA for transmission */ 395 void lpuart_dma_transmit_config(uint32_t dmacmd); 396 /* disable DMA on reception error */ 397 void lpuart_reception_error_dma_disable(void); 398 /* enable DMA on reception error */ 399 void lpuart_reception_error_dma_enable(void); 400 401 /* enable LPUART to wakeup the mcu from deep-sleep mode */ 402 void lpuart_wakeup_enable(void); 403 /* disable LPUART to wakeup the mcu from deep-sleep mode */ 404 void lpuart_wakeup_disable(void); 405 /* configure the LPUART wakeup mode from deep-sleep mode */ 406 void lpuart_wakeup_mode_config(uint32_t wum); 407 408 /* flag & interrupt functions */ 409 /* get flag in STAT/CHC register */ 410 FlagStatus lpuart_flag_get(lpuart_flag_enum flag); 411 /* clear LPUART status */ 412 void lpuart_flag_clear(lpuart_flag_enum flag); 413 /* enable LPUART interrupt */ 414 void lpuart_interrupt_enable(lpuart_interrupt_enum interrupt); 415 /* disable LPUART interrupt */ 416 void lpuart_interrupt_disable(lpuart_interrupt_enum interrupt); 417 /* get LPUART interrupt and flag status */ 418 FlagStatus lpuart_interrupt_flag_get(lpuart_interrupt_flag_enum int_flag); 419 /* clear LPUART interrupt flag */ 420 void lpuart_interrupt_flag_clear(lpuart_interrupt_flag_enum int_flag); 421 422 #endif /* GD32L23X_LPUART_H */ 423
