1 /*! 2 \file gd32l23x_lptimer.h 3 \brief definitions for the LPTIMER 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_LPTIMER_H 36 #define GD32L23X_LPTIMER_H 37 38 #include "gd32l23x.h" 39 40 /* LPTIMER definitions */ 41 #define LPTIMER LPTIMER_BASE 42 43 /* registers definitions */ 44 #define LPTIMER_INTF REG32(LPTIMER + 0x00U) /*!< interrupt flag register */ 45 #define LPTIMER_INTC REG32(LPTIMER + 0x04U) /*!< interrupt flag clear register */ 46 #define LPTIMER_INTEN REG32(LPTIMER + 0x08U) /*!< interrupt enable register */ 47 #define LPTIMER_CTL0 REG32(LPTIMER + 0x0CU) /*!< control register 0 */ 48 #define LPTIMER_CTL1 REG32(LPTIMER + 0x10U) /*!< control register 1 */ 49 #define LPTIMER_CMPV REG32(LPTIMER + 0x14U) /*!< compare value register */ 50 #define LPTIMER_CAR REG32(LPTIMER + 0x18U) /*!< counter auto reload register */ 51 #define LPTIMER_CNT REG32(LPTIMER + 0x1CU) /*!< counter register */ 52 #define LPTIMER_EIRMP REG32(LPTIMER + 0x20U) /*!< external input remap register */ 53 #define LPTIMER_INHLCMV REG32(LPTIMER + 0x24U) /*!< input high level counter max value register */ 54 55 /* bits definitions */ 56 /* LPTIMER_INTF */ 57 #define LPTIMER_INTF_CMPVMIF BIT(0) /*!< compare value register match interrupt flag */ 58 #define LPTIMER_INTF_CARMIF BIT(1) /*!< counter auto reload register match interrupt flag */ 59 #define LPTIMER_INTF_ETEDEVIF BIT(2) /*!< external trigger edge event interrupt flag */ 60 #define LPTIMER_INTF_CMPVUPIF BIT(3) /*!< compare value register update interrupt flag */ 61 #define LPTIMER_INTF_CARUPIF BIT(4) /*!< counter auto reload register update interrupt flag */ 62 #define LPTIMER_INTF_UPIF BIT(5) /*!< LPTIMER counter direction change down to up interrupt flag */ 63 #define LPTIMER_INTF_DOWNIF BIT(6) /*!< LPTIMER counter direction change up to down interrupt flag */ 64 #define LPTIMER_INTF_HLCMVUPIF BIT(26) /*!< input high level counter max value register update interrupt flag */ 65 #define LPTIMER_INTF_INHLCOIF BIT(27) /*!< LPTIMER_INx(x=0,1) high level counter overflow interrupt flag */ 66 #define LPTIMER_INTF_INHLOEIF BIT(28) /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag */ 67 #define LPTIMER_INTF_INRFOEIF BIT(29) /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag */ 68 #define LPTIMER_INTF_IN0EIF BIT(30) /*!< LPTIMER_IN0 error interrupt flag */ 69 #define LPTIMER_INTF_IN1EIF BIT(31) /*!< LPTIMER_IN1 error interrupt flag */ 70 71 /* LPTIMER_INTC */ 72 #define LPTIMER_INTC_CMPVMIC BIT(0) /*!< compare value register match interrupt flag clear bit */ 73 #define LPTIMER_INTC_CARMIC BIT(1) /*!< counter auto reload register match interrupt flag clear bit */ 74 #define LPTIMER_INTC_ETEDEVIC BIT(2) /*!< external trigger edge event interrupt flag clear bit */ 75 #define LPTIMER_INTC_CMPVUPIC BIT(3) /*!< compare value register update interrupt flag clear bit */ 76 #define LPTIMER_INTC_CARUPIC BIT(4) /*!< counter auto reload register update interrupt flag clear bit */ 77 #define LPTIMER_INTC_UPIC BIT(5) /*!< LPTIMER counter direction change down to up interrupt flag clear bit */ 78 #define LPTIMER_INTC_DOWNIC BIT(6) /*!< LPTIMER counter direction change up to down interrupt flag clear bit */ 79 #define LPTIMER_INTC_HLCMVUPIC BIT(26) /*!< input high level counter max value register update interrupt flag clear bit */ 80 #define LPTIMER_INTC_INHLCOIC BIT(27) /*!< LPTIMER_INx(x=0, 1) high level counter overflow interrupt flag clear bit */ 81 #define LPTIMER_INTC_INHLOEIC BIT(28) /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag clear bit */ 82 #define LPTIMER_INTC_INRFOEIC BIT(29) /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag clear bit */ 83 #define LPTIMER_INTC_IN0EIC BIT(30) /*!< LPTIMER_IN0 error interrupt flag clear bit */ 84 #define LPTIMER_INTC_IN1EIC BIT(31) /*!< LPTIMER_IN1 error interrupt flag clear bit */ 85 86 /* LPTIMER_INTEN */ 87 #define LPTIMER_INTEN_CMPVMIE BIT(0) /*!< compare value register match interrupt enable bit */ 88 #define LPTIMER_INTEN_CARMIE BIT(1) /*!< counter auto reload register match interrupt enable bit */ 89 #define LPTIMER_INTEN_ETEDEVIE BIT(2) /*!< external trigger edge event interrupt enable bit */ 90 #define LPTIMER_INTEN_CMPVUPIE BIT(3) /*!< compare value register update interrupt enable bit */ 91 #define LPTIMER_INTEN_CARUPIE BIT(4) /*!< counter auto reload register update interrupt enable bit */ 92 #define LPTIMER_INTEN_UPIE BIT(5) /*!< LPTIMER counter direction change down to up interrupt enable bit */ 93 #define LPTIMER_INTEN_DOWNIE BIT(6) /*!< LPTIMER counter direction change up to down interrupt enable bit */ 94 #define LPTIMER_INTEN_HLCMVUPIE BIT(26) /*!< input high level counter max value register update interrupt enable bit */ 95 #define LPTIMER_INTEN_INHLCOIE BIT(27) /*!< LPTIMER_INx(x=0,1) high level counter overflow interrupt enable bit */ 96 #define LPTIMER_INTEN_INHLOEIE BIT(28) /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit */ 97 #define LPTIMER_INTEN_INRFOEIE BIT(29) /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt enable bit */ 98 #define LPTIMER_INTEN_IN0EIE BIT(30) /*!< LPTIMER_IN0 error interrupt enable bit */ 99 #define LPTIMER_INTEN_IN1EIE BIT(31) /*!< LPTIMER_IN1 error interrupt enable bit */ 100 101 /* LPTIMER_CTL0 */ 102 #define LPTIMER_CTL0_CKSSEL BIT(0) /*!< clock source select */ 103 #define LPTIMER_CTL0_CKPSEL BITS(1, 2) /*!< clock polarity select */ 104 #define LPTIMER_CTL0_ECKFLT BITS(3, 4) /*!< external clock filter */ 105 #define LPTIMER_CTL0_TFLT BITS(6, 7) /*!< trigger filter */ 106 #define LPTIMER_CTL0_PSC BITS(9, 11) /*!< clock prescaler selection */ 107 #define LPTIMER_CTL0_ETSEL BITS(13, 15) /*!< external trigger select */ 108 #define LPTIMER_CTL0_ETMEN BITS(17, 18) /*!< external trigger mode enable */ 109 #define LPTIMER_CTL0_TIMEOUT BIT(19) /*!< timeout enable */ 110 #define LPTIMER_CTL0_OMSEL BIT(20) /*!< output mode select */ 111 #define LPTIMER_CTL0_OPSEL BIT(21) /*!< output polarity select */ 112 #define LPTIMER_CTL0_SHWEN BIT(22) /*!< LPTIMER_CAR and LPTIMER_CMPV shadow registers enable */ 113 #define LPTIMER_CTL0_CNTMEN BIT(23) /*!< counter mode select */ 114 #define LPTIMER_CTL0_DECMEN BIT(24) /*!< decoder mode enabled */ 115 #define LPTIMER_CTL0_DECMSEL BIT(25) /*!< decoder mode select */ 116 117 /* LPTIMER_CTL1 */ 118 #define LPTIMER_CTL1_LPTEN BIT(0) /*!< LPTIMER enable */ 119 #define LPTIMER_CTL1_SMST BIT(1) /*!< LPTIMER start in single counting mode */ 120 #define LPTIMER_CTL1_CTNMST BIT(2) /*!< LPTIMER start in continus counting mode */ 121 #define LPTIMER_CTL1_LPTENF BIT(30) /*!< LPTIMER enable from LPTIMER core */ 122 #define LPTIMER_CTL1_INHLCEN BIT(31) /*!< LPTIMER external input high level counter enable */ 123 124 /* LPTIMER_CMPV */ 125 #define LPTIMER_CMPV_CMPVAL BITS(0, 31) /*!< compare value */ 126 127 /* LPTIMER_CAR */ 128 #define LPTIMER_CAR_CARL BITS(0, 31) /*!< counter auto reload value */ 129 130 /* LPTIMER_CNT */ 131 #define LPTIMER_CNT_CNT BITS(0, 31) /*!< counter value */ 132 133 /* LPTIMER_EIRMP */ 134 #define LPTIMER_EIRMP_IN0RMP BIT(0) /*!< external input remap 1 */ 135 #define LPTIMER_EIRMP_IN1RMP BIT(1) /*!< external input remap 1 */ 136 137 /* LPTIMER_INHLCMV */ 138 #define LPTIMER_INHLCMV_INHLCMVAL BITS(0, 25) /*!< input high level counter max value */ 139 140 /* constants definitions */ 141 /* LPTIMER init parameter struct definitions */ 142 typedef struct { 143 uint32_t clocksource; /*!< clock source */ 144 uint32_t prescaler; /*!< counter clock prescaler */ 145 uint32_t extclockpolarity; /*!< external clock polarity of the active edge for the counter */ 146 uint32_t extclockfilter; /*!< external clock sampling time to configure the clock glitch filter */ 147 uint32_t triggermode; /*!< trigger mode */ 148 uint32_t extriggersource; /*!< external trigger source */ 149 uint32_t extriggerfilter; /*!< external trigger sampling time to configure the trigger glitch filter */ 150 uint32_t outputpolarity; /*!< output polarity */ 151 uint32_t outputmode; /*!< output mode */ 152 uint32_t countersource; /*!< whether the counter is incremented each internal event or each external event */ 153 } lptimer_parameter_struct; 154 155 /* clock source select */ 156 #define LPTIMER_INTERNALCLK ((uint32_t)0x00000000U) /*!< LPTIMER is clocked by internal clock source */ 157 #define LPTIMER_EXTERNALCLK LPTIMER_CTL0_CKSSEL /*!< LPTIMER is clocked by external clock source on the LPTIMER_IN0 */ 158 159 /* external clock polarity select */ 160 #define CTL0_CKPSEL(regval) (BITS(1, 2) & ((uint32_t)(regval) << 1U)) 161 #define LPTIMER_EXTERNALCLK_RISING CTL0_CKPSEL(0) /*!< the rising edge is the active edge used for counting */ 162 #define LPTIMER_EXTERNALCLK_FALLING CTL0_CKPSEL(1) /*!< the falling edge is the active edge used for counting */ 163 #define LPTIMER_EXTERNALCLK_BOTH CTL0_CKPSEL(2) /*!< both edges are the active edge used for counting */ 164 165 /* external clock filter select */ 166 #define CTL0_ECKFLT(regval) (BITS(3, 4) & ((uint32_t)(regval) << 3U)) 167 #define LPTIMER_EXTERNALCLK_FILTEROFF CTL0_ECKFLT(0) /*!< external clock filter disabled */ 168 #define LPTIMER_EXTERNALCLK_FILTER_2 CTL0_ECKFLT(1) /*!< the active level change of the external clock need to be maintained at least 2 clock periods */ 169 #define LPTIMER_EXTERNALCLK_FILTER_4 CTL0_ECKFLT(2) /*!< the active level change of the external clock need to be maintained at least 4 clock periods */ 170 #define LPTIMER_EXTERNALCLK_FILTER_8 CTL0_ECKFLT(3) /*!< the active level change of the external clock need to be maintained at least 8 clock periods */ 171 172 /* trigger filter select */ 173 #define CTL0_TFLT(regval) (BITS(6, 7) & ((uint32_t)(regval) << 6U)) 174 #define LPTIMER_TRIGGER_FILTEROFF CTL0_TFLT(0) /*!< trigger filter disabled */ 175 #define LPTIMER_TRIGGER_FILTER_2 CTL0_TFLT(1) /*!< the active level change of the trigger need to be maintained at least 2 clock periods */ 176 #define LPTIMER_TRIGGER_FILTER_4 CTL0_TFLT(2) /*!< the active level change of the trigger need to be maintained at least 4 clock periods */ 177 #define LPTIMER_TRIGGER_FILTER_8 CTL0_TFLT(3) /*!< the active level change of the trigger need to be maintained at least 8 clock periods */ 178 179 /* clock prescaler select */ 180 #define CTL0_CLKPSC(regval) (BITS(9, 11) & ((uint32_t)(regval) << 9U)) 181 #define LPTIMER_PSC_1 CTL0_CLKPSC(0) /*!< no prescaler */ 182 #define LPTIMER_PSC_2 CTL0_CLKPSC(1) /*!< divided by 2 */ 183 #define LPTIMER_PSC_4 CTL0_CLKPSC(2) /*!< divided by 4 */ 184 #define LPTIMER_PSC_8 CTL0_CLKPSC(3) /*!< divided by 8 */ 185 #define LPTIMER_PSC_16 CTL0_CLKPSC(4) /*!< divided by 16 */ 186 #define LPTIMER_PSC_32 CTL0_CLKPSC(5) /*!< divided by 32 */ 187 #define LPTIMER_PSC_64 CTL0_CLKPSC(6) /*!< divided by 64 */ 188 #define LPTIMER_PSC_128 CTL0_CLKPSC(7) /*!< divided by 128 */ 189 190 /* external trigger select */ 191 #define CTL0_ETSEL(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13U)) 192 #define LPTIMER_EXTRIGGER_GPIO CTL0_ETSEL(0) /*!< external trigger for GPIO */ 193 #define LPTIMER_EXTRIGGER_RTCALARM0 CTL0_ETSEL(1) /*!< external trigger for RTC Alarm 0 */ 194 #define LPTIMER_EXTRIGGER_RTCALARM1 CTL0_ETSEL(2) /*!< external trigger for RTC Alarm 1 */ 195 #define LPTIMER_EXTRIGGER_RTCTAMP0 CTL0_ETSEL(3) /*!< external trigger for RTC_TAMP0 input detection */ 196 #define LPTIMER_EXTRIGGER_RTCTAMP1 CTL0_ETSEL(4) /*!< external trigger for RTC_TAMP1 input detection */ 197 #define LPTIMER_EXTRIGGER_RTCTAMP2 CTL0_ETSEL(5) /*!< external trigger for RTC_TAMP2 input detection */ 198 #define LPTIMER_EXTRIGGER_CMP0_OUT CTL0_ETSEL(6) /*!< external trigger for CMP0_OUT */ 199 #define LPTIMER_EXTRIGGER_CMP1_OUT CTL0_ETSEL(7) /*!< external trigger for CMP1_OUT */ 200 201 /* trigger mode select */ 202 #define CTL0_ETMEN(regval) (BITS(17, 18) & ((uint32_t)(regval) << 17U)) 203 #define LPTIMER_TRIGGER_SOFTWARE CTL0_ETMEN(0) /*!< external trigger disable (software trigger) */ 204 #define LPTIMER_TRIGGER_EXTERNALRISING CTL0_ETMEN(1) /*!< rising edge of external trigger enable */ 205 #define LPTIMER_TRIGGER_EXTERNALFALLING CTL0_ETMEN(2) /*!< falling edge of external trigger enable */ 206 #define LPTIMER_TRIGGER_EXTERNALBOTH CTL0_ETMEN(3) /*!< rising and falling edges of external trigger enable */ 207 208 /* timeout select */ 209 #define LPTIMER_TIMEOUT_DISABLE ((uint32_t)0x00000000U) /*!< a new trigger event will be ignored after LPTIMER started */ 210 #define LPTIMER_TIMEOUT_ENABLE LPTIMER_CTL0_TIMEOUT /*!< a new trigger event will reset and restart the count after LPTIMER started */ 211 212 /* output mode select */ 213 #define LPTIMER_OUTPUT_PWMORSINGLE ((uint32_t)0x00000000U) /*!< PWM mode or single pulse mode */ 214 #define LPTIMER_OUTPUT_SET LPTIMER_CTL0_OMSEL /*!< set mode */ 215 216 /* clock polarity select */ 217 #define LPTIMER_OUTPUT_NOTINVERTED ((uint32_t)0x00000000U) /*!< the output is non-inverted */ 218 #define LPTIMER_OUTPUT_INVERTED LPTIMER_CTL0_OPSEL /*!< the output is inverted */ 219 220 /* CAR and CMPV shadow registers enable */ 221 #define LPTIMER_SHADOW_DISABLE ((uint32_t)0x00000000U) /*!< the shadow registers are disable */ 222 #define LPTIMER_SHADOW_ENABLE LPTIMER_CTL0_SHWEN /*!< the shadow registers are enable */ 223 224 /* counter mode select */ 225 #define LPTIMER_COUNTER_INTERNAL ((uint32_t)0x00000000U) /*!< the counter is count with each internal clock pulse */ 226 #define LPTIMER_COUNTER_EXTERNAL LPTIMER_CTL0_CNTMEN /*!< the counter is count with each active clock pulse on the LPTIMER_IN0 */ 227 228 /* external input remap */ 229 #define LPTIMER_INPUT0_GPIO ((uint32_t)0x00000000U) /*!< external input 0 is remaped to GPIO */ 230 #define LPTIMER_INPUT0_CMP0_OUT ((uint32_t)0x00000001U) /*!< external input 0 is remaped to CMP0_OUT */ 231 #define LPTIMER_INPUT1_GPIO ((uint32_t)0x00000000U) /*!< external input 1 is remaped to GPIO */ 232 #define LPTIMER_INPUT1_CMP1_OUT ((uint32_t)0x00000002U) /*!< external input 1 is remaped to CMP1_OUT */ 233 234 /* interrupt enable or disable */ 235 #define LPTIMER_INT_CMPVM LPTIMER_INTEN_CMPVMIE /*!< compare value register match interrupt */ 236 #define LPTIMER_INT_CARM LPTIMER_INTEN_CARMIE /*!< counter auto reload register match interrupt */ 237 #define LPTIMER_INT_ETEDEV LPTIMER_INTEN_ETEDEVIE /*!< external trigger edge event interrupt */ 238 #define LPTIMER_INT_CMPVUP LPTIMER_INTEN_CMPVUPIE /*!< compare value register update interrupt */ 239 #define LPTIMER_INT_CARUP LPTIMER_INTEN_CARUPIE /*!< counter auto reload register update interrupt */ 240 #define LPTIMER_INT_UP LPTIMER_INTEN_UPIE /*!< LPTIMER counter direction change down to up interrupt */ 241 #define LPTIMER_INT_DOWN LPTIMER_INTEN_DOWNIE /*!< LPTIMER counter direction change up to down interrupt */ 242 #define LPTIMER_INT_HLCMVUP LPTIMER_INTEN_HLCMVUPIE /*!< input high level counter max value register update interrupt */ 243 #define LPTIMER_INT_INHLCO LPTIMER_INTEN_INHLCOIE /*!< LPTIMER_INx(x=0,1) high level counter overflow interrupt */ 244 #define LPTIMER_INT_INHLOE LPTIMER_INTEN_INHLOEIE /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt */ 245 #define LPTIMER_INT_INRFOE LPTIMER_INTEN_INRFOEIE /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt */ 246 #define LPTIMER_INT_IN0E LPTIMER_INTEN_IN0EIE /*!< LPTIMER_IN0 error interrupt */ 247 #define LPTIMER_INT_IN1E LPTIMER_INTEN_IN1EIE /*!< LPTIMER_IN1 error interrupt */ 248 249 /* flag */ 250 #define LPTIMER_FLAG_CMPVM LPTIMER_INTF_CMPVMIF /*!< compare value register match flag */ 251 #define LPTIMER_FLAG_CARM LPTIMER_INTF_CARMIF /*!< counter auto reload register match flag */ 252 #define LPTIMER_FLAG_ETEDEV LPTIMER_INTF_ETEDEVIF /*!< external trigger edge event flag */ 253 #define LPTIMER_FLAG_CMPVUP LPTIMER_INTF_CMPVUPIF /*!< compare value register update flag */ 254 #define LPTIMER_FLAG_CARUP LPTIMER_INTF_CARUPIF /*!< counter auto reload register update flag */ 255 #define LPTIMER_FLAG_UP LPTIMER_INTF_UPIF /*!< LPTIMER counter direction change down to up flag */ 256 #define LPTIMER_FLAG_DOWN LPTIMER_INTF_DOWNIF /*!< LPTIMER counter direction change up to down flag */ 257 #define LPTIMER_FLAG_HLCMVUP LPTIMER_INTF_HLCMVUPIF /*!< input high level counter max value register update flag */ 258 #define LPTIMER_FLAG_INHLCO LPTIMER_INTF_INHLCOIF /*!< LPTIMER_INx(x=0,1) high level counter overflow flag */ 259 #define LPTIMER_FLAG_INHLOE LPTIMER_INTF_INHLOEIF /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error flag */ 260 #define LPTIMER_FLAG_INRFOE LPTIMER_INTF_INRFOEIF /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error flag */ 261 #define LPTIMER_FLAG_IN0E LPTIMER_INTF_IN0EIF /*!< LPTIMER_IN0 error flag */ 262 #define LPTIMER_FLAG_IN1E LPTIMER_INTF_IN1EIF /*!< LPTIMER_IN1 error flag */ 263 264 /* interrupt flag */ 265 #define LPTIMER_INT_FLAG_CMPVM LPTIMER_INTF_CMPVMIF /*!< compare value register match interrupt flag */ 266 #define LPTIMER_INT_FLAG_CARM LPTIMER_INTF_CARMIF /*!< counter auto reload register match interrupt flag */ 267 #define LPTIMER_INT_FLAG_ETEDEV LPTIMER_INTF_ETEDEVIF /*!< external trigger edge event interrupt flag */ 268 #define LPTIMER_INT_FLAG_CMPVUP LPTIMER_INTF_CMPVUPIF /*!< compare value register update interrupt flag */ 269 #define LPTIMER_INT_FLAG_CARUP LPTIMER_INTF_CARUPIF /*!< counter auto reload register update interrupt flag */ 270 #define LPTIMER_INT_FLAG_UP LPTIMER_INTF_UPIF /*!< LPTIMER counter direction change down to up interrupt flag */ 271 #define LPTIMER_INT_FLAG_DOWN LPTIMER_INTF_DOWNIF /*!< LPTIMER counter direction change up to down interrupt flag */ 272 #define LPTIMER_INT_FLAG_HLCMVUP LPTIMER_INTF_HLCMVUPIF /*!< input high level counter max value register update interrupt flag */ 273 #define LPTIMER_INT_FLAG_INHLCO LPTIMER_INTF_INHLCOIF /*!< LPTIMER_INx(x=0,1) high level counter overflow interrupt flag */ 274 #define LPTIMER_INT_FLAG_INHLOE LPTIMER_INTF_INHLOEIF /*!< the high level of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag */ 275 #define LPTIMER_INT_FLAG_INRFOE LPTIMER_INTF_INRFOEIF /*!< the falling and rising edges of LPTIMER_IN0 and LPTIMER_IN1 overlap error interrupt flag */ 276 #define LPTIMER_INT_FLAG_IN0E LPTIMER_INTF_IN0EIF /*!< LPTIMER_IN0 error interrupt flag */ 277 #define LPTIMER_INT_FLAG_IN1E LPTIMER_INTF_IN1EIF /*!< LPTIMER_IN1 error interrupt flag */ 278 279 /* function declarations */ 280 /* deinit the LPTIMER */ 281 void lptimer_deinit(void); 282 /* initialize LPTIMER init parameter struct with a default value */ 283 void lptimer_struct_para_init(lptimer_parameter_struct *initpara); 284 /* initialize LPTIMER counter */ 285 void lptimer_init(lptimer_parameter_struct *initpara); 286 /* configure external input remap */ 287 void lptimer_inputremap(uint32_t input0remap, uint32_t input1remap); 288 /* enable the LPTIMER_CAR and LPTIMER_CMPV registers shadow function */ 289 void lptimer_register_shadow_enable(void); 290 /* disable the LPTIMER_CAR and LPTIMER_CMPV registers shadow function */ 291 void lptimer_register_shadow_disable(void); 292 /* enable the LPTIMER TIMEOUT function */ 293 void lptimer_timeout_enable(void); 294 /* disable the LPTIMER TIMEOUT function */ 295 void lptimer_timeout_disable(void); 296 297 /* LPTIMER start and stop */ 298 /* LPTIMER start with countinue mode */ 299 void lptimer_countinue_start(uint32_t autoreload, uint32_t compare); 300 /* LPTIMER start with single mode */ 301 void lptimer_single_start(uint32_t autoreload, uint32_t compare); 302 /* stop LPTIMER */ 303 void lptimer_stop(void); 304 305 /* read and configure LPTIMER register value */ 306 /* read LPTIMER current counter value */ 307 uint32_t lptimer_counter_read(void); 308 /* read LPTIMER auto reload value */ 309 uint32_t lptimer_autoreload_read(void); 310 /* read the compare value */ 311 uint32_t lptimer_compare_read(void); 312 /* configure LPTIMER autoreload register value */ 313 void lptimer_autoreload_value_config(uint32_t autoreload); 314 /* configure LPTIMER compare value */ 315 void lptimer_compare_value_config(uint32_t compare); 316 317 /* LPTIMER decode mode */ 318 /* enable decode mode 0 */ 319 void lptimer_decodemode0_enable(void); 320 /* enable decode mode 1 */ 321 void lptimer_decodemode1_enable(void); 322 /* disable decode mode 0/1 */ 323 void lptimer_decodemode_disable(void); 324 325 /* LPTIMER input high level counter */ 326 /* enable external input high level counter */ 327 void lptimer_highlevelcounter_enable(uint32_t maxvalue); 328 /* disable external input high level counter */ 329 void lptimer_highlevelcounter_disable(void); 330 331 /* LPTIMER interrupt and flag */ 332 /* get LPTIMER flags */ 333 FlagStatus lptimer_flag_get(uint32_t flag); 334 /* clear LPTIMER flags */ 335 void lptimer_flag_clear(uint32_t flag); 336 /* enable the LPTIMER interrupt */ 337 void lptimer_interrupt_enable(uint32_t interrupt); 338 /* disable the LPTIMER interrupt */ 339 void lptimer_interrupt_disable(uint32_t interrupt); 340 /* get LPTIMER interrupt flag */ 341 FlagStatus lptimer_interrupt_flag_get(uint32_t int_flag); 342 /* clear LPTIMER interrupt flag */ 343 void lptimer_interrupt_flag_clear(uint32_t int_flag); 344 345 #endif /* GD32L23X_LPTIMER_H */ 346
