1 /*! 2 \file gd32l23x_i2c.h 3 \brief definitions for the I2C 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_I2C_H 36 #define GD32L23X_I2C_H 37 38 #include "gd32l23x.h" 39 40 /* I2Cx(x=0,1,2) definitions */ 41 #define I2C0 I2C_BASE /*!< I2C0 base address */ 42 #define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ 43 #define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */ 44 45 /* registers definitions */ 46 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ 47 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ 48 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ 49 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1*/ 50 #define I2C_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */ 51 #define I2C_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */ 52 #define I2C_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */ 53 #define I2C_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */ 54 #define I2C_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */ 55 #define I2C_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */ 56 #define I2C_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */ 57 #define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C control register 2 */ 58 59 /* bits definitions */ 60 /* I2Cx_CTL0 */ 61 #define I2C_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */ 62 #define I2C_CTL0_TIE BIT(1) /*!< transmit interrupt enable */ 63 #define I2C_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */ 64 #define I2C_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */ 65 #define I2C_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */ 66 #define I2C_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */ 67 #define I2C_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */ 68 #define I2C_CTL0_ERRIE BIT(7) /*!< error interrupt enable */ 69 #define I2C_CTL0_DNF BITS(8,11) /*!< digital noise filter */ 70 #define I2C_CTL0_ANOFF BIT(12) /*!< analog noise filter */ 71 #define I2C_CTL0_DENT BIT(14) /*!< DMA enable for transmission */ 72 #define I2C_CTL0_DENR BIT(15) /*!< DMA enable for reception */ 73 #define I2C_CTL0_SBCTL BIT(16) /*!< slave byte control */ 74 #define I2C_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */ 75 #define I2C_CTL0_WUEN BIT(18) /*!< wakeup from deep-sleep mode enable */ 76 #define I2C_CTL0_GCEN BIT(19) /*!< whether or not to response to a general call (0x00) */ 77 #define I2C_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */ 78 #define I2C_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */ 79 #define I2C_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */ 80 #define I2C_CTL0_PECEN BIT(23) /*!< PEC calculation switch */ 81 82 /* I2Cx_CTL1 */ 83 #define I2C_CTL1_SADDRESS BITS(0,9) /*!< received slave address */ 84 #define I2C_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */ 85 #define I2C_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */ 86 #define I2C_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */ 87 #define I2C_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */ 88 #define I2C_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */ 89 #define I2C_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */ 90 #define I2C_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */ 91 #define I2C_CTL1_RELOAD BIT(24) /*!< reload mode enable */ 92 #define I2C_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */ 93 #define I2C_CTL1_PECTRANS BIT(26) /*!< PEC transfer */ 94 95 /* I2Cx_SADDR0 */ 96 #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ 97 #define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ 98 #define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ 99 #define I2C_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */ 100 #define I2C_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */ 101 102 /* I2Cx_SADDR1 */ 103 #define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */ 104 #define I2C_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */ 105 #define I2C_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */ 106 107 /* I2Cx_TIMING */ 108 #define I2C_TIMING_SCLL BITS(0,7) /*!< SCL low period */ 109 #define I2C_TIMING_SCLH BITS(8,15) /*!< SCL high period */ 110 #define I2C_TIMING_SDADELY BITS(16,19) /*!< data hold time */ 111 #define I2C_TIMING_SCLDELY BITS(20,23) /*!< data setup time */ 112 #define I2C_TIMING_PSC BITS(28,31) /*!< timing prescaler */ 113 114 /* I2Cx_TIMEOUT */ 115 #define I2C_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */ 116 #define I2C_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */ 117 #define I2C_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */ 118 #define I2C_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */ 119 #define I2C_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */ 120 121 /* I2Cx_STAT */ 122 #define I2C_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */ 123 #define I2C_STAT_TI BIT(1) /*!< transmit interrupt */ 124 #define I2C_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */ 125 #define I2C_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */ 126 #define I2C_STAT_NACK BIT(4) /*!< not acknowledge flag */ 127 #define I2C_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */ 128 #define I2C_STAT_TC BIT(6) /*!< transfer complete in master mode */ 129 #define I2C_STAT_TCR BIT(7) /*!< transfer complete reload */ 130 #define I2C_STAT_BERR BIT(8) /*!< bus error */ 131 #define I2C_STAT_LOSTARB BIT(9) /*!< arbitration lost */ 132 #define I2C_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */ 133 #define I2C_STAT_PECERR BIT(11) /*!< PEC error */ 134 #define I2C_STAT_TIMEOUT BIT(12) /*!< timeout flag */ 135 #define I2C_STAT_SMBALT BIT(13) /*!< SMBus Alert */ 136 #define I2C_STAT_I2CBSY BIT(15) /*!< busy flag */ 137 #define I2C_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */ 138 #define I2C_STAT_READDR BITS(17,23) /*!< received match address in slave mode */ 139 140 /* I2Cx_STATC */ 141 #define I2C_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */ 142 #define I2C_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */ 143 #define I2C_STATC_STPDETC BIT(5) /*!< STPDET flag clear */ 144 #define I2C_STATC_BERRC BIT(8) /*!< bus error flag clear */ 145 #define I2C_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */ 146 #define I2C_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */ 147 #define I2C_STATC_PECERRC BIT(11) /*!< PEC error flag clear */ 148 #define I2C_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */ 149 #define I2C_STATC_SMBALTC BIT(13) /*!< SMBus Alert flag clear */ 150 151 /* I2Cx_PEC */ 152 #define I2C_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */ 153 154 /* I2Cx_RDATA */ 155 #define I2C_RDATA_RDATA BITS(0,7) /*!< receive data value */ 156 157 /* I2Cx_TDATA */ 158 #define I2C_TDATA_TDATA BITS(0,7) /*!< transmit data value */ 159 160 /* I2Cx_CTL2 */ 161 #define I2C_CTL2_ADDM BITS(9,15) /*!< address bit compare select */ 162 163 /* constants definitions */ 164 /* define the I2C bit position and its register index offset */ 165 #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 166 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 167 #define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 168 #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 169 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 170 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) 171 #define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 172 173 /* register offset */ 174 #define I2C_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ 175 #define I2C_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */ 176 177 /* I2C interrupt flags */ 178 typedef enum { 179 I2C_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 1U, I2C_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */ 180 I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 2U, I2C_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */ 181 I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 3U, I2C_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */ 182 I2C_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 4U, I2C_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */ 183 I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 5U, I2C_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */ 184 I2C_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */ 185 I2C_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 6U, I2C_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */ 186 I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */ 187 I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */ 188 I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */ 189 I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */ 190 I2C_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */ 191 I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL0_REG_OFFSET, 7U, I2C_STAT_REG_OFFSET, 13U) /*!< SMBus Alert interrupt flag */ 192 } i2c_interrupt_flag_enum; 193 194 /* I2C DMA constants definitions */ 195 #define I2C_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */ 196 #define I2C_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */ 197 198 /* I2C interrupt enable or disable */ 199 #define I2C_INT_ERR I2C_CTL0_ERRIE /*!< error interrupt enable */ 200 #define I2C_INT_TC I2C_CTL0_TCIE /*!< transfer complete interrupt enable */ 201 #define I2C_INT_STPDET I2C_CTL0_STPDETIE /*!< stop detection interrupt enable */ 202 #define I2C_INT_NACK I2C_CTL0_NACKIE /*!< not acknowledge received interrupt enable */ 203 #define I2C_INT_ADDM I2C_CTL0_ADDMIE /*!< address match interrupt enable */ 204 #define I2C_INT_RBNE I2C_CTL0_RBNEIE /*!< receive interrupt enable */ 205 #define I2C_INT_TI I2C_CTL0_TIE /*!< transmit interrupt enable */ 206 207 /* I2C transfer direction in master mode */ 208 #define I2C_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */ 209 #define I2C_MASTER_RECEIVE I2C_CTL1_TRDIR /*!< I2C master receive */ 210 211 /* address mode for the I2C slave */ 212 #define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ 213 #define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ 214 215 /* the length of filter spikes */ 216 #define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */ 217 #define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */ 218 #define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */ 219 #define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */ 220 #define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */ 221 #define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */ 222 #define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */ 223 #define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */ 224 #define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */ 225 #define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */ 226 #define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */ 227 #define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */ 228 #define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */ 229 #define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */ 230 #define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */ 231 #define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */ 232 233 /* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */ 234 #define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */ 235 #define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */ 236 #define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */ 237 #define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */ 238 #define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */ 239 #define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */ 240 #define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */ 241 242 /* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don��t care) */ 243 #define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */ 244 #define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */ 245 #define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */ 246 #define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */ 247 #define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */ 248 #define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */ 249 #define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */ 250 #define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */ 251 252 /* idle clock timeout detection */ 253 #define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */ 254 #define BUSTOA_DETECT_IDLE I2C_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */ 255 256 /* I2C flag definitions */ 257 #define I2C_FLAG_TBE I2C_STAT_TBE /*!< I2C_TDATA is empty during transmitting */ 258 #define I2C_FLAG_TI I2C_STAT_TI /*!< transmit interrupt */ 259 #define I2C_FLAG_RBNE I2C_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */ 260 #define I2C_FLAG_ADDSEND I2C_STAT_ADDSEND /*!< address received matches in slave mode */ 261 #define I2C_FLAG_NACK I2C_STAT_NACK /*!< not acknowledge flag */ 262 #define I2C_FLAG_STPDET I2C_STAT_STPDET /*!< STOP condition detected in slave mode */ 263 #define I2C_FLAG_TC I2C_STAT_TC /*!< transfer complete in master mode */ 264 #define I2C_FLAG_TCR I2C_STAT_TCR /*!< transfer complete reload */ 265 #define I2C_FLAG_BERR I2C_STAT_BERR /*!< bus error */ 266 #define I2C_FLAG_LOSTARB I2C_STAT_LOSTARB /*!< arbitration lost */ 267 #define I2C_FLAG_OUERR I2C_STAT_OUERR /*!< overrun/underrun error in slave mode */ 268 #define I2C_FLAG_PECERR I2C_STAT_PECERR /*!< PEC error */ 269 #define I2C_FLAG_TIMEOUT I2C_STAT_TIMEOUT /*!< timeout flag */ 270 #define I2C_FLAG_SMBALT I2C_STAT_SMBALT /*!< SMBus Alert */ 271 #define I2C_FLAG_I2CBSY I2C_STAT_I2CBSY /*!< busy flag */ 272 #define I2C_FLAG_TR I2C_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */ 273 274 /* function declarations */ 275 /* initialization functions */ 276 /* reset I2C */ 277 void i2c_deinit(uint32_t i2c_periph); 278 /* configure the timing parameters */ 279 void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely); 280 /* configure digital noise filter */ 281 void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length); 282 /* enable analog noise filter */ 283 void i2c_analog_noise_filter_enable(uint32_t i2c_periph); 284 /* disable analog noise filter */ 285 void i2c_analog_noise_filter_disable(uint32_t i2c_periph); 286 /* configure the SCL high and low period of clock in master mode */ 287 void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll); 288 /* configure i2c slave address and transfer direction in master mode */ 289 void i2c_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction); 290 291 /* application function declarations */ 292 /* 10-bit address header executes read direction only in master receive mode */ 293 void i2c_address10_header_enable(uint32_t i2c_periph); 294 /* 10-bit address header executes complete sequence in master receive mode */ 295 void i2c_address10_header_disable(uint32_t i2c_periph); 296 /* enable 10-bit addressing mode in master mode */ 297 void i2c_address10_enable(uint32_t i2c_periph); 298 /* disable 10-bit addressing mode in master mode */ 299 void i2c_address10_disable(uint32_t i2c_periph); 300 /* enable I2C automatic end mode in master mode */ 301 void i2c_automatic_end_enable(uint32_t i2c_periph); 302 /* disable I2C automatic end mode in master mode */ 303 void i2c_automatic_end_disable(uint32_t i2c_periph); 304 /* enable the response to a general call */ 305 void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph); 306 /* disable the response to a general call */ 307 void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph); 308 /* enable to stretch SCL low when data is not ready in slave mode */ 309 void i2c_stretch_scl_low_enable(uint32_t i2c_periph); 310 /* disable to stretch SCL low when data is not ready in slave mode */ 311 void i2c_stretch_scl_low_disable(uint32_t i2c_periph); 312 /* configure i2c slave address */ 313 void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format); 314 /* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */ 315 void i2c_address_bit_compare_config(uint32_t i2c_periph, uint32_t compare_bits); 316 /* disable i2c address in slave mode */ 317 void i2c_address_disable(uint32_t i2c_periph); 318 /* configure i2c second slave address */ 319 void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask); 320 /* disable i2c second address in slave mode */ 321 void i2c_second_address_disable(uint32_t i2c_periph); 322 /* get received match address in slave mode */ 323 uint32_t i2c_recevied_address_get(uint32_t i2c_periph); 324 /* enable slave byte control */ 325 void i2c_slave_byte_control_enable(uint32_t i2c_periph); 326 /* disable slave byte control */ 327 void i2c_slave_byte_control_disable(uint32_t i2c_periph); 328 /* generate a NACK in slave mode */ 329 void i2c_nack_enable(uint32_t i2c_periph); 330 /* generate an ACK in slave mode */ 331 void i2c_nack_disable(uint32_t i2c_periph); 332 /* enable wakeup from deep-sleep mode */ 333 void i2c_wakeup_from_deepsleep_enable(uint32_t i2c_periph); 334 /* disable wakeup from deep-sleep mode */ 335 void i2c_wakeup_from_deepsleep_disable(uint32_t i2c_periph); 336 /* enable I2C */ 337 void i2c_enable(uint32_t i2c_periph); 338 /* disable I2C */ 339 void i2c_disable(uint32_t i2c_periph); 340 /* generate a START condition on I2C bus */ 341 void i2c_start_on_bus(uint32_t i2c_periph); 342 /* generate a STOP condition on I2C bus */ 343 void i2c_stop_on_bus(uint32_t i2c_periph); 344 /* I2C transmit data */ 345 void i2c_data_transmit(uint32_t i2c_periph, uint32_t data); 346 /* I2C receive data */ 347 uint32_t i2c_data_receive(uint32_t i2c_periph); 348 /* enable I2C reload mode */ 349 void i2c_reload_enable(uint32_t i2c_periph); 350 /* disable I2C reload mode */ 351 void i2c_reload_disable(uint32_t i2c_periph); 352 /* configure number of bytes to be transferred */ 353 void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number); 354 /* enable I2C DMA for transmission or reception */ 355 void i2c_dma_enable(uint32_t i2c_periph, uint8_t dma); 356 /* disable I2C DMA for transmission or reception */ 357 void i2c_dma_disable(uint32_t i2c_periph, uint8_t dma); 358 /* I2C transfers PEC value */ 359 void i2c_pec_transfer(uint32_t i2c_periph); 360 /* enable I2C PEC calculation */ 361 void i2c_pec_enable(uint32_t i2c_periph); 362 /* disable I2C PEC calculation */ 363 void i2c_pec_disable(uint32_t i2c_periph); 364 /* get packet error checking value */ 365 uint32_t i2c_pec_value_get(uint32_t i2c_periph); 366 /* enable SMBus alert */ 367 void i2c_smbus_alert_enable(uint32_t i2c_periph); 368 /* disable SMBus alert */ 369 void i2c_smbus_alert_disable(uint32_t i2c_periph); 370 /* enable SMBus device default address */ 371 void i2c_smbus_default_addr_enable(uint32_t i2c_periph); 372 /* disable SMBus device default address */ 373 void i2c_smbus_default_addr_disable(uint32_t i2c_periph); 374 /* enable SMBus host address */ 375 void i2c_smbus_host_addr_enable(uint32_t i2c_periph); 376 /* disable SMBus host address */ 377 void i2c_smbus_host_addr_disable(uint32_t i2c_periph); 378 /* enable extended clock timeout detection */ 379 void i2c_extented_clock_timeout_enable(uint32_t i2c_periph); 380 /* disable extended clock timeout detection */ 381 void i2c_extented_clock_timeout_disable(uint32_t i2c_periph); 382 /* enable clock timeout detection */ 383 void i2c_clock_timeout_enable(uint32_t i2c_periph); 384 /* disable clock timeout detection */ 385 void i2c_clock_timeout_disable(uint32_t i2c_periph); 386 /* configure bus timeout B */ 387 void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout); 388 /* configure bus timeout A */ 389 void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout); 390 /* configure idle clock timeout detection */ 391 void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout); 392 393 /* interrupt & flag functions */ 394 /* get I2C flag status */ 395 FlagStatus i2c_flag_get(uint32_t i2c_periph, uint32_t flag); 396 /* clear I2C flag status */ 397 void i2c_flag_clear(uint32_t i2c_periph, uint32_t flag); 398 /* enable I2C interrupt */ 399 void i2c_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt); 400 /* disable I2C interrupt */ 401 void i2c_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt); 402 /* get I2C interrupt flag status */ 403 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 404 /* clear I2C interrupt flag status */ 405 void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 406 407 #endif /* GD32L23X_I2C_H */ 408
