1 /*! 2 \file gd32l23x_adc.h 3 \brief definitions for the ADC 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_ADC_H 36 #define GD32L23X_ADC_H 37 38 #include "gd32l23x.h" 39 40 /* ADC definitions */ 41 #define ADC ADC_BASE 42 43 /* registers definitions */ 44 #define ADC_STAT REG32(ADC + 0x00000000U) /*!< ADC status register */ 45 #define ADC_CTL0 REG32(ADC + 0x00000004U) /*!< ADC control register 0 */ 46 #define ADC_CTL1 REG32(ADC + 0x00000008U) /*!< ADC control register 1 */ 47 #define ADC_SAMPT0 REG32(ADC + 0x0000000CU) /*!< ADC sample time register 0 */ 48 #define ADC_SAMPT1 REG32(ADC + 0x00000010U) /*!< ADC sample time register 1 */ 49 #define ADC_IOFF0 REG32(ADC + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ 50 #define ADC_IOFF1 REG32(ADC + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ 51 #define ADC_IOFF2 REG32(ADC + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ 52 #define ADC_IOFF3 REG32(ADC + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ 53 #define ADC_WDHT REG32(ADC + 0x00000024U) /*!< ADC watchdog high threshold register */ 54 #define ADC_WDLT REG32(ADC + 0x00000028U) /*!< ADC watchdog low threshold register */ 55 #define ADC_RSQ0 REG32(ADC + 0x0000002CU) /*!< ADC regular sequence register 0 */ 56 #define ADC_RSQ1 REG32(ADC + 0x00000030U) /*!< ADC regular sequence register 1 */ 57 #define ADC_RSQ2 REG32(ADC + 0x00000034U) /*!< ADC regular sequence register 2 */ 58 #define ADC_ISQ REG32(ADC + 0x00000038U) /*!< ADC inserted sequence register */ 59 #define ADC_IDATA0 REG32(ADC + 0x0000003CU) /*!< ADC inserted data register 0 */ 60 #define ADC_IDATA1 REG32(ADC + 0x00000040U) /*!< ADC inserted data register 1 */ 61 #define ADC_IDATA2 REG32(ADC + 0x00000044U) /*!< ADC inserted data register 2 */ 62 #define ADC_IDATA3 REG32(ADC + 0x00000048U) /*!< ADC inserted data register 3 */ 63 #define ADC_RDATA REG32(ADC + 0x0000004CU) /*!< ADC regular data register */ 64 #define ADC_OVSAMPCTL REG32(ADC + 0x00000080U) /*!< ADC oversampling control register */ 65 #define ADC_CCTL REG32(ADC + 0x000000C0U) /*!< ADC charge control register */ 66 67 /* bits definitions */ 68 /* ADC_STAT */ 69 #define ADC_STAT_WDE BIT(0) /*!< analog watchdog event flag */ 70 #define ADC_STAT_EOC BIT(1) /*!< end of conversion */ 71 #define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ 72 #define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ 73 #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ 74 75 /* ADC_CTL0 */ 76 #define ADC_CTL0_WDCHSEL BITS(0, 4) /*!< analog watchdog channel select bits */ 77 #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ 78 #define ADC_CTL0_WDEIE BIT(6) /*!< analog watchdog interrupt enable */ 79 #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ 80 #define ADC_CTL0_SM BIT(8) /*!< scan mode */ 81 #define ADC_CTL0_WDSC BIT(9) /*!< when in scan mode, analog watchdog is effective on a single channel */ 82 #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ 83 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ 84 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ 85 #define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */ 86 #define ADC_CTL0_IWDEN BIT(22) /*!< analog watchdog enable on inserted channels */ 87 #define ADC_CTL0_RWDEN BIT(23) /*!< analog watchdog enable on regular channels */ 88 #define ADC_CTL0_DRES BITS(24, 25) /*!< ADC resolution */ 89 90 /* ADC_CTL1 */ 91 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ 92 #define ADC_CTL1_CTN BIT(1) /*!< continuous mode */ 93 #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ 94 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ 95 #define ADC_CTL1_DMA BIT(8) /*!< dma request enable */ 96 #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ 97 #define ADC_CTL1_ETSIC BITS(12, 14) /*!< external trigger select for inserted channel */ 98 #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ 99 #define ADC_CTL1_ETSRC BITS(17, 19) /*!< external trigger select for regular channel */ 100 #define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ 101 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channels */ 102 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channels */ 103 #define ADC_CTL1_TSVEN BIT(23) /*!< channel 16(temperature sensor)enable of ADC */ 104 #define ADC_CTL1_INREFEN BIT(24) /*!< channel 17(internal reference voltage)enable of ADC */ 105 #define ADC_CTL1_VBATEN BIT(25) /*!< channel 18(1/3 voltage of external battery)enable of ADC */ 106 #define ADC_CTL1_VSLCDEN BIT(26) /*!< channel 19(1/3 voltage of VSLCD)enable of ADC */ 107 108 /* ADC_SAMPTx x=0..1 */ 109 #define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n(n=0..19) sampling time selection */ 110 111 /* ADC_IOFFx x=0..3 */ 112 #define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */ 113 114 /* ADC_WDHT */ 115 #define ADC_WDHT_WDHT BITS(0, 11) /*!< analog watchdog high threshold */ 116 117 /* ADC_WDLT */ 118 #define ADC_WDLT_WDLT BITS(0, 11) /*!< analog watchdog low threshold */ 119 120 /* ADC_RSQx */ 121 #define ADC_RSQX_RSQN BITS(0, 4) /*!< x(x = 0..15) conversion in regular sequence */ 122 #define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */ 123 124 /* ADC_ISQ */ 125 #define ADC_ISQ_ISQN BITS(0, 4) /*!< x conversion in inserted sequence */ 126 #define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */ 127 128 /* ADC_IDATAx x=0..3*/ 129 #define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted channel x conversion data */ 130 131 /* ADC_RDATA */ 132 #define ADC_RDATA_RDATA BITS(0, 15) /*!< regular channel data */ 133 134 /* ADC_OVSAMPCTL */ 135 #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ 136 #define ADC_OVSAMPCTL_OVSR BITS(2, 4) /*!< oversampling ratio */ 137 #define ADC_OVSAMPCTL_OVSS BITS(5, 8) /*!< oversampling shift */ 138 #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ 139 140 /* ADC_CCTL */ 141 #define ADC_CCTL_CCNT BITS(0, 11) /*!< ADC charge pulse width counter */ 142 #define ADC_CCTL_CHARGE BIT(16) /*!< ADC charge status */ 143 144 /* constants definitions */ 145 /* ADC flag definitions */ 146 #define ADC_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event flag */ 147 #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ 148 #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ 149 #define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ 150 #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ 151 #define ADC_FLAG_CHARGE ADC_CCTL_CHARGE /*!< ADC charge flag */ 152 153 /* ADC_CTL0 register value */ 154 #define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ 155 156 /* ADC special function definitions */ 157 #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ 158 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ 159 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ 160 161 /* temperature sensor channel, internal reference voltage channel, VBAT channel and VSLCD channel */ 162 #define ADC_TEMP_CHANNEL_SWITCH ADC_CTL1_TSVEN /*!< temperature channel */ 163 #define ADC_INTERNAL_CHANNEL_SWITCH ADC_CTL1_INREFEN /*!< internal Vref channel */ 164 #define ADC_VBAT_CHANNEL_SWITCH ADC_CTL1_VBATEN /*!< VBAT channel */ 165 #define ADC_VSLCD_CHANNEL_SWITCH ADC_CTL1_VSLCDEN /*!< VSLCD channel */ 166 167 /* ADC data alignment */ 168 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ 169 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ 170 171 /* ADC external trigger select for regular channel */ 172 #define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) 173 #define ADC_EXTTRIG_REGULAR_T8_CH0 CTL1_ETSRC(0) /*!< TIMER8 CH0 event select */ 174 #define ADC_EXTTRIG_REGULAR_T8_CH1 CTL1_ETSRC(1) /*!< TIMER8 CH1 event select */ 175 #define ADC_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ 176 #define ADC_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ 177 #define ADC_EXTTRIG_REGULAR_T11_CH0 CTL1_ETSRC(5) /*!< TIMER11 CH0 event select */ 178 #define ADC_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 select */ 179 #define ADC_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger select */ 180 181 /* ADC external trigger select for inserted channel */ 182 #define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) 183 #define ADC_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ 184 #define ADC_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ 185 #define ADC_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ 186 #define ADC_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ 187 #define ADC_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger select */ 188 189 /* ADC channel sample time */ 190 #define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ 191 #define ADC_SAMPLETIME_2POINT5 SAMPTX_SPT(0) /*!< 2.5 sampling cycles */ 192 #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ 193 #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ 194 #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ 195 #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ 196 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ 197 #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ 198 #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ 199 200 /* ADC_IOFFX register value */ 201 #define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_IOFFX_IOFF bit field */ 202 203 /* ADC_WDHT register value */ 204 #define WDHT_WDHT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDHT_WDHT bit field */ 205 206 /* ADC_WDLT register value */ 207 #define WDLT_WDLT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_WDLT_WDLT bit field */ 208 209 /* ADC_RSQX register value */ 210 #define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_RSQ0_RL bit field */ 211 212 /* ADC_ISQ register value */ 213 #define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) /*!< write value to ADC_ISQ_IL bit field */ 214 215 /* ADC_CCTL register value */ 216 #define CCTL_CCNT(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_CCTL_CCNT bit field */ 217 218 /* ADC_OVSAMPCTL register value */ 219 /* ADC resolution configure */ 220 #define CTL0_DRES(regval) (BITS(24, 25) & ((uint32_t)(regval) << 24)) 221 #define ADC_RESOLUTION_12B CTL0_DRES(0) /*!< 12-bit ADC resolution */ 222 #define ADC_RESOLUTION_10B CTL0_DRES(1) /*!< 10-bit ADC resolution */ 223 #define ADC_RESOLUTION_8B CTL0_DRES(2) /*!< 8-bit ADC resolution */ 224 #define ADC_RESOLUTION_6B CTL0_DRES(3) /*!< 6-bit ADC resolution */ 225 226 /* oversampling shift */ 227 #define OVSAMPCTL_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ 228 #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ 229 #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ 230 #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ 231 #define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ 232 #define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ 233 #define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ 234 #define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ 235 #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ 236 #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ 237 238 /* oversampling ratio */ 239 #define OVSAMPCTL_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ 240 #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ 241 #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ 242 #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ 243 #define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ 244 #define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ 245 #define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ 246 #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ 247 #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ 248 249 /* triggered oversampling */ 250 #define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ 251 #define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ 252 253 /* ADC channel group definitions */ 254 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ 255 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ 256 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ 257 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ 258 259 /* ADC inserted channel definitions */ 260 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ 261 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ 262 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ 263 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ 264 265 /* ADC channel definitions */ 266 #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ 267 #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ 268 #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ 269 #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ 270 #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ 271 #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ 272 #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ 273 #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ 274 #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ 275 #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ 276 #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ 277 #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ 278 #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ 279 #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ 280 #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ 281 #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ 282 #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ 283 #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ 284 #define ADC_CHANNEL_18 ((uint8_t)0x12U) /*!< ADC channel 18 */ 285 #define ADC_CHANNEL_19 ((uint8_t)0x13U) /*!< ADC channel 19 */ 286 287 /* ADC interrupt definitions */ 288 #define ADC_INT_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ 289 #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ 290 #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ 291 292 /* ADC interrupt flag */ 293 #define ADC_INT_FLAG_WDE ADC_STAT_WDE /*!< analog watchdog event interrupt */ 294 #define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ 295 #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ 296 297 /* function declarations */ 298 /* ADC deinitialization and initialization functions */ 299 /* reset ADC */ 300 void adc_deinit(void); 301 /* enable ADC interface */ 302 void adc_enable(void); 303 /* disable ADC interface */ 304 void adc_disable(void); 305 306 /* ADC calibration and DMA functions */ 307 /* ADC calibration and reset calibration */ 308 void adc_calibration_enable(void); 309 /* enable DMA request */ 310 void adc_dma_mode_enable(void); 311 /* disable DMA request */ 312 void adc_dma_mode_disable(void); 313 314 /* ADC special function functions */ 315 /* configure ADC discontinuous mode */ 316 void adc_discontinuous_mode_config(uint8_t adc_channel_group, uint8_t length); 317 /* configure ADC special function */ 318 void adc_special_function_config(uint32_t function, ControlStatus newvalue); 319 /* configure temperature sensor, internal reference voltage channel, VBAT channel or VSLCD channel */ 320 void adc_channel_16_to_19(uint32_t function, ControlStatus newvalue); 321 322 /* ADC channel configuration functions */ 323 /* configure ADC data alignment */ 324 void adc_data_alignment_config(uint32_t data_alignment); 325 /* configure the length of regular channel group or inserted channel group */ 326 void adc_channel_length_config(uint8_t adc_channel_group, uint32_t length); 327 /* configure ADC regular channel */ 328 void adc_regular_channel_config(uint8_t rank, uint8_t adc_channel, uint32_t sample_time); 329 /* configure ADC inserted channel */ 330 void adc_inserted_channel_config(uint8_t rank, uint8_t adc_channel, uint32_t sample_time); 331 /* configure ADC inserted channel offset */ 332 void adc_inserted_channel_offset_config(uint8_t inserted_channel, uint16_t offset); 333 334 /* ADC external trigger functions */ 335 /* configure ADC external trigger */ 336 void adc_external_trigger_config(uint8_t adc_channel_group, ControlStatus newvalue); 337 /* configure ADC external trigger source */ 338 void adc_external_trigger_source_config(uint8_t adc_channel_group, uint32_t external_trigger_source); 339 /* enable ADC software trigger */ 340 void adc_software_trigger_enable(uint8_t adc_channel_group); 341 342 /* ADC data read functions */ 343 /* read ADC regular group data register */ 344 uint16_t adc_regular_data_read(void); 345 /* read ADC inserted group data register */ 346 uint16_t adc_inserted_data_read(uint8_t inserted_channel); 347 348 /* ADC analog watchdog functions */ 349 /* enable ADC analog watchdog single channel */ 350 void adc_watchdog_single_channel_enable(uint8_t adc_channel); 351 /* enable ADC analog watchdog group channel */ 352 void adc_watchdog_group_channel_enable(uint8_t adc_channel_group); 353 /* disable ADC analog watchdog */ 354 void adc_watchdog_disable(void); 355 /* configure ADC analog watchdog threshold */ 356 void adc_watchdog_threshold_config(uint16_t low_threshold, uint16_t high_threshold); 357 358 /* ADC resolution and oversample functions */ 359 /* configure ADC resolution */ 360 void adc_resolution_config(uint32_t resolution); 361 /* configure ADC oversample mode */ 362 void adc_oversample_mode_config(uint32_t mode, uint16_t shift, uint8_t ratio); 363 /* enable ADC oversample mode */ 364 void adc_oversample_mode_enable(void); 365 /* disable ADC oversample mode */ 366 void adc_oversample_mode_disable(void); 367 368 /* ADC charge control functions */ 369 /* configure ADC charge pulse width counter */ 370 void adc_charge_pulse_width_counter(uint32_t value); 371 /* get the ADC charge flag */ 372 FlagStatus adc_charge_flag_get(uint32_t flag); 373 374 /* flag and interrupt functions */ 375 /* get the flag of ADC regular channel software start conversion */ 376 FlagStatus adc_regular_software_startconv_flag_get(void); 377 /* get the flag of ADC inserted channel software start conversion */ 378 FlagStatus adc_inserted_software_startconv_flag_get(void); 379 /* get ADC flag */ 380 FlagStatus adc_flag_get(uint32_t flag); 381 /* clear ADC flag */ 382 void adc_flag_clear(uint32_t flag); 383 /* enable ADC interrupt */ 384 void adc_interrupt_enable(uint32_t interrupt); 385 /* disable ADC interrupt */ 386 void adc_interrupt_disable(uint32_t interrupt); 387 /* get ADC interrupt flag */ 388 FlagStatus adc_interrupt_flag_get(uint32_t int_flag); 389 /* clear ADC interrupt flag */ 390 void adc_interrupt_flag_clear(uint32_t int_flag); 391 392 #endif /* GD32L23X_ADC_H */ 393
