1 /*!
2 \file gd32f4xx_timer.c
3 \brief TIMER driver
4
5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
9 */
10
11 /*
12 Copyright (c) 2022, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38
39 #include "gd32f4xx_timer.h"
40
41 /*!
42 \brief deinit a TIMER
43 \param[in] timer_periph: TIMERx(x=0..13)
44 \param[out] none
45 \retval none
46 */
timer_deinit(uint32_t timer_periph)47 void timer_deinit(uint32_t timer_periph)
48 {
49 switch(timer_periph) {
50 case TIMER0:
51 /* reset TIMER0 */
52 rcu_periph_reset_enable(RCU_TIMER0RST);
53 rcu_periph_reset_disable(RCU_TIMER0RST);
54 break;
55 case TIMER1:
56 /* reset TIMER1 */
57 rcu_periph_reset_enable(RCU_TIMER1RST);
58 rcu_periph_reset_disable(RCU_TIMER1RST);
59 break;
60 case TIMER2:
61 /* reset TIMER2 */
62 rcu_periph_reset_enable(RCU_TIMER2RST);
63 rcu_periph_reset_disable(RCU_TIMER2RST);
64 break;
65 case TIMER3:
66 /* reset TIMER3 */
67 rcu_periph_reset_enable(RCU_TIMER3RST);
68 rcu_periph_reset_disable(RCU_TIMER3RST);
69 break;
70 case TIMER4:
71 /* reset TIMER4 */
72 rcu_periph_reset_enable(RCU_TIMER4RST);
73 rcu_periph_reset_disable(RCU_TIMER4RST);
74 break;
75 case TIMER5:
76 /* reset TIMER5 */
77 rcu_periph_reset_enable(RCU_TIMER5RST);
78 rcu_periph_reset_disable(RCU_TIMER5RST);
79 break;
80 case TIMER6:
81 /* reset TIMER6 */
82 rcu_periph_reset_enable(RCU_TIMER6RST);
83 rcu_periph_reset_disable(RCU_TIMER6RST);
84 break;
85 case TIMER7:
86 /* reset TIMER7 */
87 rcu_periph_reset_enable(RCU_TIMER7RST);
88 rcu_periph_reset_disable(RCU_TIMER7RST);
89 break;
90 case TIMER8:
91 /* reset TIMER8 */
92 rcu_periph_reset_enable(RCU_TIMER8RST);
93 rcu_periph_reset_disable(RCU_TIMER8RST);
94 break;
95 case TIMER9:
96 /* reset TIMER9 */
97 rcu_periph_reset_enable(RCU_TIMER9RST);
98 rcu_periph_reset_disable(RCU_TIMER9RST);
99 break;
100 case TIMER10:
101 /* reset TIMER10 */
102 rcu_periph_reset_enable(RCU_TIMER10RST);
103 rcu_periph_reset_disable(RCU_TIMER10RST);
104 break;
105 case TIMER11:
106 /* reset TIMER11 */
107 rcu_periph_reset_enable(RCU_TIMER11RST);
108 rcu_periph_reset_disable(RCU_TIMER11RST);
109 break;
110 case TIMER12:
111 /* reset TIMER12 */
112 rcu_periph_reset_enable(RCU_TIMER12RST);
113 rcu_periph_reset_disable(RCU_TIMER12RST);
114 break;
115 case TIMER13:
116 /* reset TIMER13 */
117 rcu_periph_reset_enable(RCU_TIMER13RST);
118 rcu_periph_reset_disable(RCU_TIMER13RST);
119 break;
120 default:
121 break;
122 }
123 }
124
125 /*!
126 \brief initialize TIMER init parameter struct with a default value
127 \param[in] initpara: init parameter struct
128 \param[out] none
129 \retval none
130 */
timer_struct_para_init(timer_parameter_struct * initpara)131 void timer_struct_para_init(timer_parameter_struct *initpara)
132 {
133 /* initialize the init parameter struct member with the default value */
134 initpara->prescaler = 0U;
135 initpara->alignedmode = TIMER_COUNTER_EDGE;
136 initpara->counterdirection = TIMER_COUNTER_UP;
137 initpara->period = 65535U;
138 initpara->clockdivision = TIMER_CKDIV_DIV1;
139 initpara->repetitioncounter = 0U;
140 }
141
142 /*!
143 \brief initialize TIMER counter
144 \param[in] timer_periph: TIMERx(x=0..13)
145 \param[in] initpara: init parameter struct
146 prescaler: prescaler value of the counter clock,0~65535
147 alignedmode: TIMER_COUNTER_EDGE,TIMER_COUNTER_CENTER_DOWN,TIMER_COUNTER_CENTER_UP,TIMER_COUNTER_CENTER_BOTH
148 counterdirection: TIMER_COUNTER_UP,TIMER_COUNTER_DOWN
149 period: counter auto reload value,(TIMER1,TIMER4,32 bit)
150 clockdivision: TIMER_CKDIV_DIV1,TIMER_CKDIV_DIV2,TIMER_CKDIV_DIV4
151 repetitioncounter: counter repetition value,0~255
152 \param[out] none
153 \retval none
154 */
gd32_timer_init(uint32_t timer_periph,timer_parameter_struct * initpara)155 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct *initpara)
156 {
157 /* configure the counter prescaler value */
158 TIMER_PSC(timer_periph) = (uint16_t)initpara->prescaler;
159
160 /* configure the counter direction and aligned mode */
161 if((TIMER0 == timer_periph) || (TIMER1 == timer_periph) || (TIMER2 == timer_periph)
162 || (TIMER3 == timer_periph) || (TIMER4 == timer_periph) || (TIMER7 == timer_periph)) {
163 TIMER_CTL0(timer_periph) &= ~(uint32_t)(TIMER_CTL0_DIR | TIMER_CTL0_CAM);
164 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->alignedmode;
165 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->counterdirection;
166 }
167
168 /* configure the autoreload value */
169 TIMER_CAR(timer_periph) = (uint32_t)initpara->period;
170
171 if((TIMER5 != timer_periph) && (TIMER6 != timer_periph)) {
172 /* reset the CKDIV bit */
173 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CKDIV;
174 TIMER_CTL0(timer_periph) |= (uint32_t)initpara->clockdivision;
175 }
176
177 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) {
178 /* configure the repetition counter value */
179 TIMER_CREP(timer_periph) = (uint32_t)initpara->repetitioncounter;
180 }
181
182 /* generate an update event */
183 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
184 }
185
186 /*!
187 \brief enable a TIMER
188 \param[in] timer_periph: TIMERx(x=0..13)
189 \param[out] none
190 \retval none
191 */
timer_enable(uint32_t timer_periph)192 void timer_enable(uint32_t timer_periph)
193 {
194 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_CEN;
195 }
196
197 /*!
198 \brief disable a TIMER
199 \param[in] timer_periph: TIMERx(x=0..13)
200 \param[out] none
201 \retval none
202 */
timer_disable(uint32_t timer_periph)203 void timer_disable(uint32_t timer_periph)
204 {
205 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CEN;
206 }
207
208 /*!
209 \brief enable the auto reload shadow function
210 \param[in] timer_periph: TIMERx(x=0..13)
211 \param[out] none
212 \retval none
213 */
timer_auto_reload_shadow_enable(uint32_t timer_periph)214 void timer_auto_reload_shadow_enable(uint32_t timer_periph)
215 {
216 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_ARSE;
217 }
218
219 /*!
220 \brief disable the auto reload shadow function
221 \param[in] timer_periph: TIMERx(x=0..13)
222 \param[out] none
223 \retval none
224 */
timer_auto_reload_shadow_disable(uint32_t timer_periph)225 void timer_auto_reload_shadow_disable(uint32_t timer_periph)
226 {
227 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_ARSE;
228 }
229
230 /*!
231 \brief enable the update event
232 \param[in] timer_periph: TIMERx(x=0..13)
233 \param[out] none
234 \retval none
235 */
timer_update_event_enable(uint32_t timer_periph)236 void timer_update_event_enable(uint32_t timer_periph)
237 {
238 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPDIS;
239 }
240
241 /*!
242 \brief disable the update event
243 \param[in] timer_periph: TIMERx(x=0..13)
244 \param[out] none
245 \retval none
246 */
timer_update_event_disable(uint32_t timer_periph)247 void timer_update_event_disable(uint32_t timer_periph)
248 {
249 TIMER_CTL0(timer_periph) |= (uint32_t) TIMER_CTL0_UPDIS;
250 }
251
252 /*!
253 \brief set TIMER counter alignment mode
254 \param[in] timer_periph: TIMERx(x=0..4,7)
255 \param[in] aligned:
256 only one parameter can be selected which is shown as below:
257 \arg TIMER_COUNTER_EDGE: edge-aligned mode
258 \arg TIMER_COUNTER_CENTER_DOWN: center-aligned and counting down assert mode
259 \arg TIMER_COUNTER_CENTER_UP: center-aligned and counting up assert mode
260 \arg TIMER_COUNTER_CENTER_BOTH: center-aligned and counting up/down assert mode
261 \param[out] none
262 \retval none
263 */
timer_counter_alignment(uint32_t timer_periph,uint16_t aligned)264 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned)
265 {
266 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_CAM;
267 TIMER_CTL0(timer_periph) |= (uint32_t)aligned;
268 }
269
270 /*!
271 \brief set TIMER counter up direction
272 \param[in] timer_periph: TIMERx(x=0..4,7)
273 \param[out] none
274 \retval none
275 */
timer_counter_up_direction(uint32_t timer_periph)276 void timer_counter_up_direction(uint32_t timer_periph)
277 {
278 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_DIR;
279 }
280
281 /*!
282 \brief set TIMER counter down direction
283 \param[in] timer_periph: TIMERx(x=0..4,7)
284 \param[out] none
285 \retval none
286 */
timer_counter_down_direction(uint32_t timer_periph)287 void timer_counter_down_direction(uint32_t timer_periph)
288 {
289 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_DIR;
290 }
291
292 /*!
293 \brief configure TIMER prescaler
294 \param[in] timer_periph: TIMERx(x=0..13)
295 \param[in] prescaler: prescaler value,0~65535
296 \param[in] pscreload: prescaler reload mode
297 only one parameter can be selected which is shown as below:
298 \arg TIMER_PSC_RELOAD_NOW: the prescaler is loaded right now
299 \arg TIMER_PSC_RELOAD_UPDATE: the prescaler is loaded at the next update event
300 \param[out] none
301 \retval none
302 */
timer_prescaler_config(uint32_t timer_periph,uint16_t prescaler,uint8_t pscreload)303 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint8_t pscreload)
304 {
305 TIMER_PSC(timer_periph) = (uint32_t)prescaler;
306
307 if(TIMER_PSC_RELOAD_NOW == pscreload) {
308 TIMER_SWEVG(timer_periph) |= (uint32_t)TIMER_SWEVG_UPG;
309 }
310 }
311
312 /*!
313 \brief configure TIMER repetition register value
314 \param[in] timer_periph: TIMERx(x=0,7)
315 \param[in] repetition: the counter repetition value,0~255
316 \param[out] none
317 \retval none
318 */
timer_repetition_value_config(uint32_t timer_periph,uint16_t repetition)319 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition)
320 {
321 TIMER_CREP(timer_periph) = (uint32_t)repetition;
322 }
323
324 /*!
325 \brief configure TIMER autoreload register value
326 \param[in] timer_periph: TIMERx(x=0..13)
327 \param[in] autoreload: the counter auto-reload value
328 \param[out] none
329 \retval none
330 */
timer_autoreload_value_config(uint32_t timer_periph,uint32_t autoreload)331 void timer_autoreload_value_config(uint32_t timer_periph, uint32_t autoreload)
332 {
333 TIMER_CAR(timer_periph) = (uint32_t)autoreload;
334 }
335
336 /*!
337 \brief configure TIMER counter register value
338 \param[in] timer_periph: TIMERx(x=0..13)
339 \param[in] counter: the counter value,0~65535
340 \param[out] none
341 \retval none
342 */
timer_counter_value_config(uint32_t timer_periph,uint32_t counter)343 void timer_counter_value_config(uint32_t timer_periph, uint32_t counter)
344 {
345 TIMER_CNT(timer_periph) = (uint32_t)counter;
346 }
347
348 /*!
349 \brief read TIMER counter value
350 \param[in] timer_periph: TIMERx(x=0..13)
351 \param[out] none
352 \retval counter value
353 */
timer_counter_read(uint32_t timer_periph)354 uint32_t timer_counter_read(uint32_t timer_periph)
355 {
356 uint32_t count_value = 0U;
357 count_value = TIMER_CNT(timer_periph);
358 return (count_value);
359 }
360
361 /*!
362 \brief read TIMER prescaler value
363 \param[in] timer_periph: TIMERx(x=0..13)
364 \param[out] none
365 \retval prescaler register value
366 */
timer_prescaler_read(uint32_t timer_periph)367 uint16_t timer_prescaler_read(uint32_t timer_periph)
368 {
369 uint16_t prescaler_value = 0U;
370 prescaler_value = (uint16_t)(TIMER_PSC(timer_periph));
371 return (prescaler_value);
372 }
373
374 /*!
375 \brief configure TIMER single pulse mode
376 \param[in] timer_periph: TIMERx(x=0..8,11)
377 \param[in] spmode:
378 only one parameter can be selected which is shown as below:
379 \arg TIMER_SP_MODE_SINGLE: single pulse mode
380 \arg TIMER_SP_MODE_REPETITIVE: repetitive pulse mode
381 \param[out] none
382 \retval none
383 */
timer_single_pulse_mode_config(uint32_t timer_periph,uint32_t spmode)384 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode)
385 {
386 if(TIMER_SP_MODE_SINGLE == spmode) {
387 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_SPM;
388 } else if(TIMER_SP_MODE_REPETITIVE == spmode) {
389 TIMER_CTL0(timer_periph) &= ~((uint32_t)TIMER_CTL0_SPM);
390 } else {
391 /* illegal parameters */
392 }
393 }
394
395 /*!
396 \brief configure TIMER update source
397 \param[in] timer_periph: TIMERx(x=0..13)
398 \param[in] update:
399 only one parameter can be selected which is shown as below:
400 \arg TIMER_UPDATE_SRC_GLOBAL: update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger
401 \arg TIMER_UPDATE_SRC_REGULAR: update generate only by counter overflow/underflow
402 \param[out] none
403 \retval none
404 */
timer_update_source_config(uint32_t timer_periph,uint32_t update)405 void timer_update_source_config(uint32_t timer_periph, uint32_t update)
406 {
407 if(TIMER_UPDATE_SRC_REGULAR == update) {
408 TIMER_CTL0(timer_periph) |= (uint32_t)TIMER_CTL0_UPS;
409 } else if(TIMER_UPDATE_SRC_GLOBAL == update) {
410 TIMER_CTL0(timer_periph) &= ~(uint32_t)TIMER_CTL0_UPS;
411 } else {
412 /* illegal parameters */
413 }
414 }
415
416 /*!
417 \brief enable the TIMER DMA
418 \param[in] timer_periph: please refer to the following parameters
419 \param[in] dma: specify which DMA to enable
420 one or more parameters can be selected which is shown as below:
421 \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7)
422 \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7)
423 \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7)
424 \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7)
425 \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7)
426 \arg TIMER_DMA_CMTD: commutation DMA request,TIMERx(x=0,7)
427 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7)
428 \param[out] none
429 \retval none
430 */
timer_dma_enable(uint32_t timer_periph,uint16_t dma)431 void timer_dma_enable(uint32_t timer_periph, uint16_t dma)
432 {
433 TIMER_DMAINTEN(timer_periph) |= (uint32_t) dma;
434 }
435
436 /*!
437 \brief disable the TIMER DMA
438 \param[in] timer_periph: please refer to the following parameters
439 \param[in] dma: specify which DMA to disable
440 one or more parameters can be selected which are shown as below:
441 \arg TIMER_DMA_UPD: update DMA,TIMERx(x=0..7)
442 \arg TIMER_DMA_CH0D: channel 0 DMA request,TIMERx(x=0..4,7)
443 \arg TIMER_DMA_CH1D: channel 1 DMA request,TIMERx(x=0..4,7)
444 \arg TIMER_DMA_CH2D: channel 2 DMA request,TIMERx(x=0..4,7)
445 \arg TIMER_DMA_CH3D: channel 3 DMA request,TIMERx(x=0..4,7)
446 \arg TIMER_DMA_CMTD: commutation DMA request ,TIMERx(x=0,7)
447 \arg TIMER_DMA_TRGD: trigger DMA request,TIMERx(x=0..4,7)
448 \param[out] none
449 \retval none
450 */
timer_dma_disable(uint32_t timer_periph,uint16_t dma)451 void timer_dma_disable(uint32_t timer_periph, uint16_t dma)
452 {
453 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)(dma));
454 }
455
456 /*!
457 \brief channel DMA request source selection
458 \param[in] timer_periph: TIMERx(x=0..4,7)
459 \param[in] dma_request: channel DMA request source selection
460 only one parameter can be selected which is shown as below:
461 \arg TIMER_DMAREQUEST_CHANNELEVENT: DMA request of channel y is sent when channel y event occurs
462 \arg TIMER_DMAREQUEST_UPDATEEVENT: DMA request of channel y is sent when update event occurs
463 \param[out] none
464 \retval none
465 */
timer_channel_dma_request_source_select(uint32_t timer_periph,uint8_t dma_request)466 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint8_t dma_request)
467 {
468 if(TIMER_DMAREQUEST_UPDATEEVENT == dma_request) {
469 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_DMAS;
470 } else if(TIMER_DMAREQUEST_CHANNELEVENT == dma_request) {
471 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_DMAS;
472 } else {
473 /* illegal parameters */
474 }
475 }
476
477 /*!
478 \brief configure the TIMER DMA transfer
479 \param[in] timer_periph: please refer to the following parameters
480 \param[in] dma_baseaddr:
481 only one parameter can be selected which is shown as below:
482 \arg TIMER_DMACFG_DMATA_CTL0: DMA transfer address is TIMER_CTL0,TIMERx(x=0..4,7)
483 \arg TIMER_DMACFG_DMATA_CTL1: DMA transfer address is TIMER_CTL1,TIMERx(x=0..4,7)
484 \arg TIMER_DMACFG_DMATA_SMCFG: DMA transfer address is TIMER_SMCFG,TIMERx(x=0..4,7)
485 \arg TIMER_DMACFG_DMATA_DMAINTEN: DMA transfer address is TIMER_DMAINTEN,TIMERx(x=0..4,7)
486 \arg TIMER_DMACFG_DMATA_INTF: DMA transfer address is TIMER_INTF,TIMERx(x=0..4,7)
487 \arg TIMER_DMACFG_DMATA_SWEVG: DMA transfer address is TIMER_SWEVG,TIMERx(x=0..4,7)
488 \arg TIMER_DMACFG_DMATA_CHCTL0: DMA transfer address is TIMER_CHCTL0,TIMERx(x=0..4,7)
489 \arg TIMER_DMACFG_DMATA_CHCTL1: DMA transfer address is TIMER_CHCTL1,TIMERx(x=0..4,7)
490 \arg TIMER_DMACFG_DMATA_CHCTL2: DMA transfer address is TIMER_CHCTL2,TIMERx(x=0..4,7)
491 \arg TIMER_DMACFG_DMATA_CNT: DMA transfer address is TIMER_CNT,TIMERx(x=0..4,7)
492 \arg TIMER_DMACFG_DMATA_PSC: DMA transfer address is TIMER_PSC,TIMERx(x=0..4,7)
493 \arg TIMER_DMACFG_DMATA_CAR: DMA transfer address is TIMER_CAR,TIMERx(x=0..4,7)
494 \arg TIMER_DMACFG_DMATA_CREP: DMA transfer address is TIMER_CREP,TIMERx(x=0,7)
495 \arg TIMER_DMACFG_DMATA_CH0CV: DMA transfer address is TIMER_CH0CV,TIMERx(x=0..4,7)
496 \arg TIMER_DMACFG_DMATA_CH1CV: DMA transfer address is TIMER_CH1CV,TIMERx(x=0..4,7)
497 \arg TIMER_DMACFG_DMATA_CH2CV: DMA transfer address is TIMER_CH2CV,TIMERx(x=0..4,7)
498 \arg TIMER_DMACFG_DMATA_CH3CV: DMA transfer address is TIMER_CH3CV,TIMERx(x=0..4,7)
499 \arg TIMER_DMACFG_DMATA_CCHP: DMA transfer address is TIMER_CCHP,TIMERx(x=0..4,7)
500 \arg TIMER_DMACFG_DMATA_DMACFG: DMA transfer address is TIMER_DMACFG,TIMERx(x=0..4,7)
501 \arg TIMER_DMACFG_DMATA_DMATB: DMA transfer address is TIMER_DMATB,TIMERx(x=0..4,7)
502 \param[in] dma_lenth:
503 only one parameter can be selected which is shown as below:
504 \arg TIMER_DMACFG_DMATC_xTRANSFER(x=1..18): DMA transfer x time
505 \param[out] none
506 \retval none
507 */
timer_dma_transfer_config(uint32_t timer_periph,uint32_t dma_baseaddr,uint32_t dma_lenth)508 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth)
509 {
510 TIMER_DMACFG(timer_periph) &= (~(uint32_t)(TIMER_DMACFG_DMATA | TIMER_DMACFG_DMATC));
511 TIMER_DMACFG(timer_periph) |= (uint32_t)(dma_baseaddr | dma_lenth);
512 }
513
514 /*!
515 \brief software generate events
516 \param[in] timer_periph: please refer to the following parameters
517 \param[in] event: the timer software event generation sources
518 one or more parameters can be selected which are shown as below:
519 \arg TIMER_EVENT_SRC_UPG: update event,TIMERx(x=0..13)
520 \arg TIMER_EVENT_SRC_CH0G: channel 0 capture or compare event generation,TIMERx(x=0..4,7..13)
521 \arg TIMER_EVENT_SRC_CH1G: channel 1 capture or compare event generation,TIMERx(x=0..4,7,8,11)
522 \arg TIMER_EVENT_SRC_CH2G: channel 2 capture or compare event generation,TIMERx(x=0..4,7)
523 \arg TIMER_EVENT_SRC_CH3G: channel 3 capture or compare event generation,TIMERx(x=0..4,7)
524 \arg TIMER_EVENT_SRC_CMTG: channel commutation event generation,TIMERx(x=0,7)
525 \arg TIMER_EVENT_SRC_TRGG: trigger event generation,TIMERx(x=0..4,7,8,11)
526 \arg TIMER_EVENT_SRC_BRKG: break event generation,TIMERx(x=0,7)
527 \param[out] none
528 \retval none
529 */
timer_event_software_generate(uint32_t timer_periph,uint16_t event)530 void timer_event_software_generate(uint32_t timer_periph, uint16_t event)
531 {
532 TIMER_SWEVG(timer_periph) |= (uint32_t)event;
533 }
534
535 /*!
536 \brief initialize TIMER break parameter struct
537 \param[in] breakpara: TIMER break parameter struct
538 \param[out] none
539 \retval none
540 */
timer_break_struct_para_init(timer_break_parameter_struct * breakpara)541 void timer_break_struct_para_init(timer_break_parameter_struct *breakpara)
542 {
543 /* initialize the break parameter struct member with the default value */
544 breakpara->runoffstate = TIMER_ROS_STATE_DISABLE;
545 breakpara->ideloffstate = TIMER_IOS_STATE_DISABLE;
546 breakpara->deadtime = 0U;
547 breakpara->breakpolarity = TIMER_BREAK_POLARITY_LOW;
548 breakpara->outputautostate = TIMER_OUTAUTO_DISABLE;
549 breakpara->protectmode = TIMER_CCHP_PROT_OFF;
550 breakpara->breakstate = TIMER_BREAK_DISABLE;
551 }
552
553 /*!
554 \brief configure TIMER break function
555 \param[in] timer_periph: TIMERx(x=0,7)
556 \param[in] breakpara: TIMER break parameter struct
557 runoffstate: TIMER_ROS_STATE_ENABLE,TIMER_ROS_STATE_DISABLE
558 ideloffstate: TIMER_IOS_STATE_ENABLE,TIMER_IOS_STATE_DISABLE
559 deadtime: 0~255
560 breakpolarity: TIMER_BREAK_POLARITY_LOW,TIMER_BREAK_POLARITY_HIGH
561 outputautostate: TIMER_OUTAUTO_ENABLE,TIMER_OUTAUTO_DISABLE
562 protectmode: TIMER_CCHP_PROT_OFF,TIMER_CCHP_PROT_0,TIMER_CCHP_PROT_1,TIMER_CCHP_PROT_2
563 breakstate: TIMER_BREAK_ENABLE,TIMER_BREAK_DISABLE
564 \param[out] none
565 \retval none
566 */
timer_break_config(uint32_t timer_periph,timer_break_parameter_struct * breakpara)567 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct *breakpara)
568 {
569 TIMER_CCHP(timer_periph) = (uint32_t)(((uint32_t)(breakpara->runoffstate)) |
570 ((uint32_t)(breakpara->ideloffstate)) |
571 ((uint32_t)(breakpara->deadtime)) |
572 ((uint32_t)(breakpara->breakpolarity)) |
573 ((uint32_t)(breakpara->outputautostate)) |
574 ((uint32_t)(breakpara->protectmode)) |
575 ((uint32_t)(breakpara->breakstate))) ;
576 }
577
578 /*!
579 \brief enable TIMER break function
580 \param[in] timer_periph: TIMERx(x=0,7)
581 \param[out] none
582 \retval none
583 */
timer_break_enable(uint32_t timer_periph)584 void timer_break_enable(uint32_t timer_periph)
585 {
586 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_BRKEN;
587 }
588
589 /*!
590 \brief disable TIMER break function
591 \param[in] timer_periph: TIMERx(x=0,7)
592 \param[out] none
593 \retval none
594 */
timer_break_disable(uint32_t timer_periph)595 void timer_break_disable(uint32_t timer_periph)
596 {
597 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_BRKEN;
598 }
599
600 /*!
601 \brief enable TIMER output automatic function
602 \param[in] timer_periph: TIMERx(x=0,7)
603 \param[out] none
604 \retval none
605 */
timer_automatic_output_enable(uint32_t timer_periph)606 void timer_automatic_output_enable(uint32_t timer_periph)
607 {
608 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_OAEN;
609 }
610
611 /*!
612 \brief disable TIMER output automatic function
613 \param[in] timer_periph: TIMERx(x=0,7)
614 \param[out] none
615 \retval none
616 */
timer_automatic_output_disable(uint32_t timer_periph)617 void timer_automatic_output_disable(uint32_t timer_periph)
618 {
619 TIMER_CCHP(timer_periph) &= ~(uint32_t)TIMER_CCHP_OAEN;
620 }
621
622 /*!
623 \brief configure TIMER primary output function
624 \param[in] timer_periph: TIMERx(x=0,7)
625 \param[in] newvalue: ENABLE or DISABLE
626 \param[out] none
627 \retval none
628 */
timer_primary_output_config(uint32_t timer_periph,ControlStatus newvalue)629 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue)
630 {
631 if(ENABLE == newvalue) {
632 TIMER_CCHP(timer_periph) |= (uint32_t)TIMER_CCHP_POEN;
633 } else {
634 TIMER_CCHP(timer_periph) &= (~(uint32_t)TIMER_CCHP_POEN);
635 }
636 }
637
638 /*!
639 \brief enable or disable channel capture/compare control shadow register
640 \param[in] timer_periph: TIMERx(x=0,7)
641 \param[in] newvalue: ENABLE or DISABLE
642 \param[out] none
643 \retval none
644 */
timer_channel_control_shadow_config(uint32_t timer_periph,ControlStatus newvalue)645 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue)
646 {
647 if(ENABLE == newvalue) {
648 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCSE;
649 } else {
650 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCSE);
651 }
652 }
653
654 /*!
655 \brief configure TIMER channel control shadow register update control
656 \param[in] timer_periph: TIMERx(x=0,7)
657 \param[in] ccuctl: channel control shadow register update control
658 only one parameter can be selected which is shown as below:
659 \arg TIMER_UPDATECTL_CCU: the shadow registers update by when CMTG bit is set
660 \arg TIMER_UPDATECTL_CCUTRI: the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs
661 \param[out] none
662 \retval none
663 */
timer_channel_control_shadow_update_config(uint32_t timer_periph,uint8_t ccuctl)664 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint8_t ccuctl)
665 {
666 if(TIMER_UPDATECTL_CCU == ccuctl) {
667 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_CCUC);
668 } else if(TIMER_UPDATECTL_CCUTRI == ccuctl) {
669 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_CCUC;
670 } else {
671 /* illegal parameters */
672 }
673 }
674
675 /*!
676 \brief initialize TIMER channel output parameter struct with a default value
677 \param[in] ocpara: TIMER channel n output parameter struct
678 \param[out] none
679 \retval none
680 */
timer_channel_output_struct_para_init(timer_oc_parameter_struct * ocpara)681 void timer_channel_output_struct_para_init(timer_oc_parameter_struct *ocpara)
682 {
683 /* initialize the channel output parameter struct member with the default value */
684 ocpara->outputstate = (uint16_t)TIMER_CCX_DISABLE;
685 ocpara->outputnstate = TIMER_CCXN_DISABLE;
686 ocpara->ocpolarity = TIMER_OC_POLARITY_HIGH;
687 ocpara->ocnpolarity = TIMER_OCN_POLARITY_HIGH;
688 ocpara->ocidlestate = TIMER_OC_IDLE_STATE_LOW;
689 ocpara->ocnidlestate = TIMER_OCN_IDLE_STATE_LOW;
690 }
691
692 /*!
693 \brief configure TIMER channel output function
694 \param[in] timer_periph: please refer to the following parameters
695 \param[in] channel:
696 only one parameter can be selected which is shown as below:
697 \arg TIMER_CH_0: TIMER channel 0(TIMERx(x=0..4,7..13))
698 \arg TIMER_CH_1: TIMER channel 1(TIMERx(x=0..4,7,8,11))
699 \arg TIMER_CH_2: TIMER channel 2(TIMERx(x=0..4,7))
700 \arg TIMER_CH_3: TIMER channel 3(TIMERx(x=0..4,7))
701 \param[in] ocpara: TIMER channeln output parameter struct
702 outputstate: TIMER_CCX_ENABLE,TIMER_CCX_DISABLE
703 outputnstate: TIMER_CCXN_ENABLE,TIMER_CCXN_DISABLE
704 ocpolarity: TIMER_OC_POLARITY_HIGH,TIMER_OC_POLARITY_LOW
705 ocnpolarity: TIMER_OCN_POLARITY_HIGH,TIMER_OCN_POLARITY_LOW
706 ocidlestate: TIMER_OC_IDLE_STATE_LOW,TIMER_OC_IDLE_STATE_HIGH
707 ocnidlestate: TIMER_OCN_IDLE_STATE_LOW,TIMER_OCN_IDLE_STATE_HIGH
708 \param[out] none
709 \retval none
710 */
timer_channel_output_config(uint32_t timer_periph,uint16_t channel,timer_oc_parameter_struct * ocpara)711 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct *ocpara)
712 {
713 switch(channel) {
714 /* configure TIMER_CH_0 */
715 case TIMER_CH_0:
716 /* reset the CH0EN bit */
717 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
718 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH0MS;
719 /* set the CH0EN bit */
720 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputstate;
721 /* reset the CH0P bit */
722 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
723 /* set the CH0P bit */
724 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocpolarity;
725
726 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) {
727 /* reset the CH0NEN bit */
728 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
729 /* set the CH0NEN bit */
730 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->outputnstate;
731 /* reset the CH0NP bit */
732 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
733 /* set the CH0NP bit */
734 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpara->ocnpolarity;
735 /* reset the ISO0 bit */
736 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0);
737 /* set the ISO0 bit */
738 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocidlestate;
739 /* reset the ISO0N bit */
740 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO0N);
741 /* set the ISO0N bit */
742 TIMER_CTL1(timer_periph) |= (uint32_t)ocpara->ocnidlestate;
743 }
744 break;
745 /* configure TIMER_CH_1 */
746 case TIMER_CH_1:
747 /* reset the CH1EN bit */
748 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
749 TIMER_CHCTL0(timer_periph) &= ~(uint32_t)TIMER_CHCTL0_CH1MS;
750 /* set the CH1EN bit */
751 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 4U);
752 /* reset the CH1P bit */
753 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
754 /* set the CH1P bit */
755 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 4U);
756
757 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) {
758 /* reset the CH1NEN bit */
759 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
760 /* set the CH1NEN bit */
761 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 4U);
762 /* reset the CH1NP bit */
763 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
764 /* set the CH1NP bit */
765 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 4U);
766 /* reset the ISO1 bit */
767 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1);
768 /* set the ISO1 bit */
769 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 2U);
770 /* reset the ISO1N bit */
771 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO1N);
772 /* set the ISO1N bit */
773 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 2U);
774 }
775 break;
776 /* configure TIMER_CH_2 */
777 case TIMER_CH_2:
778 /* reset the CH2EN bit */
779 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
780 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH2MS;
781 /* set the CH2EN bit */
782 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 8U);
783 /* reset the CH2P bit */
784 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
785 /* set the CH2P bit */
786 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 8U);
787
788 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) {
789 /* reset the CH2NEN bit */
790 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
791 /* set the CH2NEN bit */
792 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->outputnstate) << 8U);
793 /* reset the CH2NP bit */
794 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
795 /* set the CH2NP bit */
796 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnpolarity) << 8U);
797 /* reset the ISO2 bit */
798 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2);
799 /* set the ISO2 bit */
800 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 4U);
801 /* reset the ISO2N bit */
802 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO2N);
803 /* set the ISO2N bit */
804 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocnidlestate) << 4U);
805 }
806 break;
807 /* configure TIMER_CH_3 */
808 case TIMER_CH_3:
809 /* reset the CH3EN bit */
810 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
811 TIMER_CHCTL1(timer_periph) &= ~(uint32_t)TIMER_CHCTL1_CH3MS;
812 /* set the CH3EN bit */
813 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpara->outputstate << 12U);
814 /* reset the CH3P bit */
815 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
816 /* set the CH3P bit */
817 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocpolarity) << 12U);
818
819 if((TIMER0 == timer_periph) || (TIMER7 == timer_periph)) {
820 /* reset the ISO3 bit */
821 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_ISO3);
822 /* set the ISO3 bit */
823 TIMER_CTL1(timer_periph) |= (uint32_t)((uint32_t)(ocpara->ocidlestate) << 6U);
824 }
825 break;
826 default:
827 break;
828 }
829 }
830
831 /*!
832 \brief configure TIMER channel output compare mode
833 \param[in] timer_periph: please refer to the following parameters
834 \param[in] channel:
835 only one parameter can be selected which is shown as below:
836 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
837 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
838 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
839 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
840 \param[in] ocmode: channel output compare mode
841 only one parameter can be selected which is shown as below:
842 \arg TIMER_OC_MODE_TIMING: timing mode
843 \arg TIMER_OC_MODE_ACTIVE: active mode
844 \arg TIMER_OC_MODE_INACTIVE: inactive mode
845 \arg TIMER_OC_MODE_TOGGLE: toggle mode
846 \arg TIMER_OC_MODE_LOW: force low mode
847 \arg TIMER_OC_MODE_HIGH: force high mode
848 \arg TIMER_OC_MODE_PWM0: PWM0 mode
849 \arg TIMER_OC_MODE_PWM1: PWM1 mode
850 \param[out] none
851 \retval none
852 */
timer_channel_output_mode_config(uint32_t timer_periph,uint16_t channel,uint16_t ocmode)853 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode)
854 {
855 switch(channel) {
856 /* configure TIMER_CH_0 */
857 case TIMER_CH_0:
858 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCTL);
859 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocmode;
860 break;
861 /* configure TIMER_CH_1 */
862 case TIMER_CH_1:
863 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCTL);
864 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
865 break;
866 /* configure TIMER_CH_2 */
867 case TIMER_CH_2:
868 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCTL);
869 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocmode;
870 break;
871 /* configure TIMER_CH_3 */
872 case TIMER_CH_3:
873 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCTL);
874 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocmode) << 8U);
875 break;
876 default:
877 break;
878 }
879 }
880
881 /*!
882 \brief configure TIMER channel output pulse value
883 \param[in] timer_periph: please refer to the following parameters
884 \param[in] channel:
885 only one parameter can be selected which is shown as below:
886 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
887 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
888 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
889 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
890 \param[in] pulse: channel output pulse value,0~65535
891 \param[out] none
892 \retval none
893 */
timer_channel_output_pulse_value_config(uint32_t timer_periph,uint16_t channel,uint32_t pulse)894 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse)
895 {
896 switch(channel) {
897 /* configure TIMER_CH_0 */
898 case TIMER_CH_0:
899 TIMER_CH0CV(timer_periph) = (uint32_t)pulse;
900 break;
901 /* configure TIMER_CH_1 */
902 case TIMER_CH_1:
903 TIMER_CH1CV(timer_periph) = (uint32_t)pulse;
904 break;
905 /* configure TIMER_CH_2 */
906 case TIMER_CH_2:
907 TIMER_CH2CV(timer_periph) = (uint32_t)pulse;
908 break;
909 /* configure TIMER_CH_3 */
910 case TIMER_CH_3:
911 TIMER_CH3CV(timer_periph) = (uint32_t)pulse;
912 break;
913 default:
914 break;
915 }
916 }
917
918 /*!
919 \brief configure TIMER channel output shadow function
920 \param[in] timer_periph: please refer to the following parameters
921 \param[in] channel:
922 only one parameter can be selected which is shown as below:
923 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
924 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
925 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
926 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
927 \param[in] ocshadow: channel output shadow state
928 only one parameter can be selected which is shown as below:
929 \arg TIMER_OC_SHADOW_ENABLE: channel output shadow state enable
930 \arg TIMER_OC_SHADOW_DISABLE: channel output shadow state disable
931 \param[out] none
932 \retval none
933 */
timer_channel_output_shadow_config(uint32_t timer_periph,uint16_t channel,uint16_t ocshadow)934 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow)
935 {
936 switch(channel) {
937 /* configure TIMER_CH_0 */
938 case TIMER_CH_0:
939 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMSEN);
940 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocshadow;
941 break;
942 /* configure TIMER_CH_1 */
943 case TIMER_CH_1:
944 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMSEN);
945 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
946 break;
947 /* configure TIMER_CH_2 */
948 case TIMER_CH_2:
949 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMSEN);
950 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocshadow;
951 break;
952 /* configure TIMER_CH_3 */
953 case TIMER_CH_3:
954 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMSEN);
955 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(ocshadow) << 8U);
956 break;
957 default:
958 break;
959 }
960 }
961
962 /*!
963 \brief configure TIMER channel output fast function
964 \param[in] timer_periph: please refer to the following parameters
965 \param[in] channel:
966 only one parameter can be selected which is shown as below:
967 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
968 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
969 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
970 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
971 \param[in] ocfast: channel output fast function
972 only one parameter can be selected which is shown as below:
973 \arg TIMER_OC_FAST_ENABLE: channel output fast function enable
974 \arg TIMER_OC_FAST_DISABLE: channel output fast function disable
975 \param[out] none
976 \retval none
977 */
timer_channel_output_fast_config(uint32_t timer_periph,uint16_t channel,uint16_t ocfast)978 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast)
979 {
980 switch(channel) {
981 /* configure TIMER_CH_0 */
982 case TIMER_CH_0:
983 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMFEN);
984 TIMER_CHCTL0(timer_periph) |= (uint32_t)ocfast;
985 break;
986 /* configure TIMER_CH_1 */
987 case TIMER_CH_1:
988 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMFEN);
989 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
990 break;
991 /* configure TIMER_CH_2 */
992 case TIMER_CH_2:
993 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMFEN);
994 TIMER_CHCTL1(timer_periph) |= (uint32_t)ocfast;
995 break;
996 /* configure TIMER_CH_3 */
997 case TIMER_CH_3:
998 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMFEN);
999 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)ocfast << 8U);
1000 break;
1001 default:
1002 break;
1003 }
1004 }
1005
1006 /*!
1007 \brief configure TIMER channel output clear function
1008 \param[in] timer_periph: please refer to the following parameters
1009 \param[in] channel:
1010 only one parameter can be selected which is shown as below:
1011 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7))
1012 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7))
1013 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1014 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1015 \param[in] occlear: channel output clear function
1016 only one parameter can be selected which is shown as below:
1017 \arg TIMER_OC_CLEAR_ENABLE: channel output clear function enable
1018 \arg TIMER_OC_CLEAR_DISABLE: channel output clear function disable
1019 \param[out] none
1020 \retval none
1021 */
timer_channel_output_clear_config(uint32_t timer_periph,uint16_t channel,uint16_t occlear)1022 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear)
1023 {
1024 switch(channel) {
1025 /* configure TIMER_CH_0 */
1026 case TIMER_CH_0:
1027 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0COMCEN);
1028 TIMER_CHCTL0(timer_periph) |= (uint32_t)occlear;
1029 break;
1030 /* configure TIMER_CH_1 */
1031 case TIMER_CH_1:
1032 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1COMCEN);
1033 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1034 break;
1035 /* configure TIMER_CH_2 */
1036 case TIMER_CH_2:
1037 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2COMCEN);
1038 TIMER_CHCTL1(timer_periph) |= (uint32_t)occlear;
1039 break;
1040 /* configure TIMER_CH_3 */
1041 case TIMER_CH_3:
1042 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3COMCEN);
1043 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)occlear << 8U);
1044 break;
1045 default:
1046 break;
1047 }
1048 }
1049
1050 /*!
1051 \brief configure TIMER channel output polarity
1052 \param[in] timer_periph: please refer to the following parameters
1053 \param[in] channel:
1054 only one parameter can be selected which is shown as below:
1055 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1056 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1057 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1058 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1059 \param[in] ocpolarity: channel output polarity
1060 only one parameter can be selected which is shown as below:
1061 \arg TIMER_OC_POLARITY_HIGH: channel output polarity is high
1062 \arg TIMER_OC_POLARITY_LOW: channel output polarity is low
1063 \param[out] none
1064 \retval none
1065 */
timer_channel_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocpolarity)1066 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity)
1067 {
1068 switch(channel) {
1069 /* configure TIMER_CH_0 */
1070 case TIMER_CH_0:
1071 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0P);
1072 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocpolarity;
1073 break;
1074 /* configure TIMER_CH_1 */
1075 case TIMER_CH_1:
1076 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1P);
1077 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 4U);
1078 break;
1079 /* configure TIMER_CH_2 */
1080 case TIMER_CH_2:
1081 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2P);
1082 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 8U);
1083 break;
1084 /* configure TIMER_CH_3 */
1085 case TIMER_CH_3:
1086 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3P);
1087 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocpolarity << 12U);
1088 break;
1089 default:
1090 break;
1091 }
1092 }
1093
1094 /*!
1095 \brief configure TIMER channel complementary output polarity
1096 \param[in] timer_periph: please refer to the following parameters
1097 \param[in] channel:
1098 only one parameter can be selected which is shown as below:
1099 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1100 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1101 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1102 \param[in] ocnpolarity: channel complementary output polarity
1103 only one parameter can be selected which is shown as below:
1104 \arg TIMER_OCN_POLARITY_HIGH: channel complementary output polarity is high
1105 \arg TIMER_OCN_POLARITY_LOW: channel complementary output polarity is low
1106 \param[out] none
1107 \retval none
1108 */
timer_channel_complementary_output_polarity_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnpolarity)1109 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity)
1110 {
1111 switch(channel) {
1112 /* configure TIMER_CH_0 */
1113 case TIMER_CH_0:
1114 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NP);
1115 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnpolarity;
1116 break;
1117 /* configure TIMER_CH_1 */
1118 case TIMER_CH_1:
1119 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NP);
1120 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 4U);
1121 break;
1122 /* configure TIMER_CH_2 */
1123 case TIMER_CH_2:
1124 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NP);
1125 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnpolarity << 8U);
1126 break;
1127 default:
1128 break;
1129 }
1130 }
1131
1132 /*!
1133 \brief configure TIMER channel enable state
1134 \param[in] timer_periph: please refer to the following parameters
1135 \param[in] channel:
1136 only one parameter can be selected which is shown as below:
1137 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1138 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1139 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1140 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1141 \param[in] state: TIMER channel enable state
1142 only one parameter can be selected which is shown as below:
1143 \arg TIMER_CCX_ENABLE: channel enable
1144 \arg TIMER_CCX_DISABLE: channel disable
1145 \param[out] none
1146 \retval none
1147 */
timer_channel_output_state_config(uint32_t timer_periph,uint16_t channel,uint32_t state)1148 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state)
1149 {
1150 switch(channel) {
1151 /* configure TIMER_CH_0 */
1152 case TIMER_CH_0:
1153 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1154 TIMER_CHCTL2(timer_periph) |= (uint32_t)state;
1155 break;
1156 /* configure TIMER_CH_1 */
1157 case TIMER_CH_1:
1158 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1159 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 4U);
1160 break;
1161 /* configure TIMER_CH_2 */
1162 case TIMER_CH_2:
1163 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1164 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 8U);
1165 break;
1166 /* configure TIMER_CH_3 */
1167 case TIMER_CH_3:
1168 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1169 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)state << 12U);
1170 break;
1171 default:
1172 break;
1173 }
1174 }
1175
1176 /*!
1177 \brief configure TIMER channel complementary output enable state
1178 \param[in] timer_periph: TIMERx(x=0,7)
1179 \param[in] channel:
1180 only one parameter can be selected which is shown as below:
1181 \arg TIMER_CH_0: TIMER channel0
1182 \arg TIMER_CH_1: TIMER channel1
1183 \arg TIMER_CH_2: TIMER channel2
1184 \param[in] ocnstate: TIMER channel complementary output enable state
1185 only one parameter can be selected which is shown as below:
1186 \arg TIMER_CCXN_ENABLE: channel complementary enable
1187 \arg TIMER_CCXN_DISABLE: channel complementary disable
1188 \param[out] none
1189 \retval none
1190 */
timer_channel_complementary_output_state_config(uint32_t timer_periph,uint16_t channel,uint16_t ocnstate)1191 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate)
1192 {
1193 switch(channel) {
1194 /* configure TIMER_CH_0 */
1195 case TIMER_CH_0:
1196 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0NEN);
1197 TIMER_CHCTL2(timer_periph) |= (uint32_t)ocnstate;
1198 break;
1199 /* configure TIMER_CH_1 */
1200 case TIMER_CH_1:
1201 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1NEN);
1202 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 4U);
1203 break;
1204 /* configure TIMER_CH_2 */
1205 case TIMER_CH_2:
1206 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2NEN);
1207 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)ocnstate << 8U);
1208 break;
1209 default:
1210 break;
1211 }
1212 }
1213
1214 /*!
1215 \brief initialize TIMER channel input parameter struct
1216 \param[in] icpara: TIMER channel intput parameter struct
1217 \param[out] none
1218 \retval none
1219 */
timer_channel_input_struct_para_init(timer_ic_parameter_struct * icpara)1220 void timer_channel_input_struct_para_init(timer_ic_parameter_struct *icpara)
1221 {
1222 /* initialize the channel input parameter struct member with the default value */
1223 icpara->icpolarity = TIMER_IC_POLARITY_RISING;
1224 icpara->icselection = TIMER_IC_SELECTION_DIRECTTI;
1225 icpara->icprescaler = TIMER_IC_PSC_DIV1;
1226 icpara->icfilter = 0U;
1227 }
1228
1229 /*!
1230 \brief configure TIMER input capture parameter
1231 \param[in] timer_periph: please refer to the following parameters
1232 \param[in] channel:
1233 only one parameter can be selected which is shown as below:
1234 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1235 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1236 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1237 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1238 \param[in] icpara: TIMER channel intput parameter struct
1239 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING,TIMER_IC_POLARITY_BOTH_EDGE
1240 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI,TIMER_IC_SELECTION_ITS
1241 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1242 icfilter: 0~15
1243 \param[out] none
1244 \retval none
1245 */
timer_input_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpara)1246 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpara)
1247 {
1248 switch(channel) {
1249 /* configure TIMER_CH_0 */
1250 case TIMER_CH_0:
1251 /* reset the CH0EN bit */
1252 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1253
1254 /* reset the CH0P and CH0NP bits */
1255 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1256 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpara->icpolarity);
1257 /* reset the CH0MS bit */
1258 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1259 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpara->icselection);
1260 /* reset the CH0CAPFLT bit */
1261 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1262 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1263
1264 /* set the CH0EN bit */
1265 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1266 break;
1267
1268 /* configure TIMER_CH_1 */
1269 case TIMER_CH_1:
1270 /* reset the CH1EN bit */
1271 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1272
1273 /* reset the CH1P and CH1NP bits */
1274 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1275 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 4U);
1276 /* reset the CH1MS bit */
1277 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1278 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1279 /* reset the CH1CAPFLT bit */
1280 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1281 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1282
1283 /* set the CH1EN bit */
1284 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1285 break;
1286 /* configure TIMER_CH_2 */
1287 case TIMER_CH_2:
1288 /* reset the CH2EN bit */
1289 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH2EN);
1290
1291 /* reset the CH2P and CH2NP bits */
1292 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH2P | TIMER_CHCTL2_CH2NP));
1293 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 8U);
1294
1295 /* reset the CH2MS bit */
1296 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2MS);
1297 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection));
1298
1299 /* reset the CH2CAPFLT bit */
1300 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPFLT);
1301 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 4U);
1302
1303 /* set the CH2EN bit */
1304 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH2EN;
1305 break;
1306 /* configure TIMER_CH_3 */
1307 case TIMER_CH_3:
1308 /* reset the CH3EN bit */
1309 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH3EN);
1310
1311 /* reset the CH3P bits */
1312 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH3P));
1313 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpara->icpolarity) << 12U);
1314
1315 /* reset the CH3MS bit */
1316 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3MS);
1317 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icselection) << 8U);
1318
1319 /* reset the CH3CAPFLT bit */
1320 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPFLT);
1321 TIMER_CHCTL1(timer_periph) |= (uint32_t)((uint32_t)(icpara->icfilter) << 12U);
1322
1323 /* set the CH3EN bit */
1324 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH3EN;
1325 break;
1326 default:
1327 break;
1328 }
1329 /* configure TIMER channel input capture prescaler value */
1330 timer_channel_input_capture_prescaler_config(timer_periph, channel, (uint16_t)(icpara->icprescaler));
1331 }
1332
1333 /*!
1334 \brief configure TIMER channel input capture prescaler value
1335 \param[in] timer_periph: please refer to the following parameters
1336 \param[in] channel:
1337 only one parameter can be selected which is shown as below:
1338 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1339 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1340 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1341 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1342 \param[in] prescaler: channel input capture prescaler value
1343 only one parameter can be selected which is shown as below:
1344 \arg TIMER_IC_PSC_DIV1: no prescaler
1345 \arg TIMER_IC_PSC_DIV2: divided by 2
1346 \arg TIMER_IC_PSC_DIV4: divided by 4
1347 \arg TIMER_IC_PSC_DIV8: divided by 8
1348 \param[out] none
1349 \retval none
1350 */
timer_channel_input_capture_prescaler_config(uint32_t timer_periph,uint16_t channel,uint16_t prescaler)1351 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler)
1352 {
1353 switch(channel) {
1354 /* configure TIMER_CH_0 */
1355 case TIMER_CH_0:
1356 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPPSC);
1357 TIMER_CHCTL0(timer_periph) |= (uint32_t)prescaler;
1358 break;
1359 /* configure TIMER_CH_1 */
1360 case TIMER_CH_1:
1361 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPPSC);
1362 TIMER_CHCTL0(timer_periph) |= ((uint32_t)prescaler << 8U);
1363 break;
1364 /* configure TIMER_CH_2 */
1365 case TIMER_CH_2:
1366 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH2CAPPSC);
1367 TIMER_CHCTL1(timer_periph) |= (uint32_t)prescaler;
1368 break;
1369 /* configure TIMER_CH_3 */
1370 case TIMER_CH_3:
1371 TIMER_CHCTL1(timer_periph) &= (~(uint32_t)TIMER_CHCTL1_CH3CAPPSC);
1372 TIMER_CHCTL1(timer_periph) |= ((uint32_t)prescaler << 8U);
1373 break;
1374 default:
1375 break;
1376 }
1377 }
1378
1379 /*!
1380 \brief read TIMER channel capture compare register value
1381 \param[in] timer_periph: please refer to the following parameters
1382 \param[in] channel:
1383 only one parameter can be selected which is shown as below:
1384 \arg TIMER_CH_0: TIMER channel0(TIMERx(x=0..4,7..13))
1385 \arg TIMER_CH_1: TIMER channel1(TIMERx(x=0..4,7,8,11))
1386 \arg TIMER_CH_2: TIMER channel2(TIMERx(x=0..4,7))
1387 \arg TIMER_CH_3: TIMER channel3(TIMERx(x=0..4,7))
1388 \param[out] none
1389 \retval channel capture compare register value
1390 */
timer_channel_capture_value_register_read(uint32_t timer_periph,uint16_t channel)1391 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel)
1392 {
1393 uint32_t count_value = 0U;
1394
1395 switch(channel) {
1396 /* read TIMER channel 0 capture compare register value */
1397 case TIMER_CH_0:
1398 count_value = TIMER_CH0CV(timer_periph);
1399 break;
1400 /* read TIMER channel 1 capture compare register value */
1401 case TIMER_CH_1:
1402 count_value = TIMER_CH1CV(timer_periph);
1403 break;
1404 /* read TIMER channel 2 capture compare register value */
1405 case TIMER_CH_2:
1406 count_value = TIMER_CH2CV(timer_periph);
1407 break;
1408 /* read TIMER channel 3 capture compare register value */
1409 case TIMER_CH_3:
1410 count_value = TIMER_CH3CV(timer_periph);
1411 break;
1412 default:
1413 break;
1414 }
1415 return (count_value);
1416 }
1417
1418 /*!
1419 \brief configure TIMER input pwm capture function
1420 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1421 \param[in] channel:
1422 only one parameter can be selected which is shown as below:
1423 \arg TIMER_CH_0: TIMER channel0
1424 \arg TIMER_CH_1: TIMER channel1
1425 \param[in] icpwm:TIMER channel intput pwm parameter struct
1426 icpolarity: TIMER_IC_POLARITY_RISING,TIMER_IC_POLARITY_FALLING
1427 icselection: TIMER_IC_SELECTION_DIRECTTI,TIMER_IC_SELECTION_INDIRECTTI
1428 icprescaler: TIMER_IC_PSC_DIV1,TIMER_IC_PSC_DIV2,TIMER_IC_PSC_DIV4,TIMER_IC_PSC_DIV8
1429 icfilter: 0~15
1430 \param[out] none
1431 \retval none
1432 */
timer_input_pwm_capture_config(uint32_t timer_periph,uint16_t channel,timer_ic_parameter_struct * icpwm)1433 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct *icpwm)
1434 {
1435 uint16_t icpolarity = 0x0U;
1436 uint16_t icselection = 0x0U;
1437
1438 /* Set channel input polarity */
1439 if(TIMER_IC_POLARITY_RISING == icpwm->icpolarity) {
1440 icpolarity = TIMER_IC_POLARITY_FALLING;
1441 } else {
1442 icpolarity = TIMER_IC_POLARITY_RISING;
1443 }
1444
1445 /* Set channel input mode selection */
1446 if(TIMER_IC_SELECTION_DIRECTTI == icpwm->icselection) {
1447 icselection = TIMER_IC_SELECTION_INDIRECTTI;
1448 } else {
1449 icselection = TIMER_IC_SELECTION_DIRECTTI;
1450 }
1451
1452 if(TIMER_CH_0 == channel) {
1453 /* reset the CH0EN bit */
1454 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1455 /* reset the CH0P and CH0NP bits */
1456 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1457 /* set the CH0P and CH0NP bits */
1458 TIMER_CHCTL2(timer_periph) |= (uint32_t)(icpwm->icpolarity);
1459 /* reset the CH0MS bit */
1460 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1461 /* set the CH0MS bit */
1462 TIMER_CHCTL0(timer_periph) |= (uint32_t)(icpwm->icselection);
1463 /* reset the CH0CAPFLT bit */
1464 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1465 /* set the CH0CAPFLT bit */
1466 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1467 /* set the CH0EN bit */
1468 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1469 /* configure TIMER channel input capture prescaler value */
1470 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1471
1472 /* reset the CH1EN bit */
1473 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1474 /* reset the CH1P and CH1NP bits */
1475 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1476 /* set the CH1P and CH1NP bits */
1477 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)icpolarity << 4U);
1478 /* reset the CH1MS bit */
1479 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1480 /* set the CH1MS bit */
1481 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)icselection << 8U);
1482 /* reset the CH1CAPFLT bit */
1483 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1484 /* set the CH1CAPFLT bit */
1485 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1486 /* set the CH1EN bit */
1487 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1488 /* configure TIMER channel input capture prescaler value */
1489 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1490 } else {
1491 /* reset the CH1EN bit */
1492 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1493 /* reset the CH1P and CH1NP bits */
1494 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1495 /* set the CH1P and CH1NP bits */
1496 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icpolarity) << 4U);
1497 /* reset the CH1MS bit */
1498 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1499 /* set the CH1MS bit */
1500 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icselection) << 8U);
1501 /* reset the CH1CAPFLT bit */
1502 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1503 /* set the CH1CAPFLT bit */
1504 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)(icpwm->icfilter) << 12U);
1505 /* set the CH1EN bit */
1506 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1507 /* configure TIMER channel input capture prescaler value */
1508 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_1, (uint16_t)(icpwm->icprescaler));
1509
1510 /* reset the CH0EN bit */
1511 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1512 /* reset the CH0P and CH0NP bits */
1513 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1514 /* set the CH0P and CH0NP bits */
1515 TIMER_CHCTL2(timer_periph) |= (uint32_t)icpolarity;
1516 /* reset the CH0MS bit */
1517 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1518 /* set the CH0MS bit */
1519 TIMER_CHCTL0(timer_periph) |= (uint32_t)icselection;
1520 /* reset the CH0CAPFLT bit */
1521 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1522 /* set the CH0CAPFLT bit */
1523 TIMER_CHCTL0(timer_periph) |= ((uint32_t)(icpwm->icfilter) << 4U);
1524 /* set the CH0EN bit */
1525 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1526 /* configure TIMER channel input capture prescaler value */
1527 timer_channel_input_capture_prescaler_config(timer_periph, TIMER_CH_0, (uint16_t)(icpwm->icprescaler));
1528 }
1529 }
1530
1531 /*!
1532 \brief configure TIMER hall sensor mode
1533 \param[in] timer_periph: TIMERx(x=0..4,7)
1534 \param[in] hallmode:
1535 only one parameter can be selected which is shown as below:
1536 \arg TIMER_HALLINTERFACE_ENABLE: TIMER hall sensor mode enable
1537 \arg TIMER_HALLINTERFACE_DISABLE: TIMER hall sensor mode disable
1538 \param[out] none
1539 \retval none
1540 */
timer_hall_mode_config(uint32_t timer_periph,uint32_t hallmode)1541 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode)
1542 {
1543 if(TIMER_HALLINTERFACE_ENABLE == hallmode) {
1544 TIMER_CTL1(timer_periph) |= (uint32_t)TIMER_CTL1_TI0S;
1545 } else if(TIMER_HALLINTERFACE_DISABLE == hallmode) {
1546 TIMER_CTL1(timer_periph) &= ~(uint32_t)TIMER_CTL1_TI0S;
1547 } else {
1548 /* illegal parameters */
1549 }
1550 }
1551
1552 /*!
1553 \brief select TIMER input trigger source
1554 \param[in] timer_periph: please refer to the following parameters
1555 \param[in] intrigger:
1556 only one parameter can be selected which is shown as below:
1557 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0(TIMERx(x=0..4,7,8,11))
1558 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1(TIMERx(x=0..4,7,8,11))
1559 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2(TIMERx(x=0..4,7,8,11))
1560 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3(TIMERx(x=0..4,7,8,11))
1561 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector(TIMERx(x=0..4,7,8,11))
1562 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0(TIMERx(x=0..4,7,8,11))
1563 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1(TIMERx(x=0..4,7,8,11))
1564 \arg TIMER_SMCFG_TRGSEL_ETIFP: external trigger(TIMERx(x=0..4,7,8,11))
1565 \param[out] none
1566 \retval none
1567 */
timer_input_trigger_source_select(uint32_t timer_periph,uint32_t intrigger)1568 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger)
1569 {
1570 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_TRGS);
1571 TIMER_SMCFG(timer_periph) |= (uint32_t)intrigger;
1572 }
1573
1574 /*!
1575 \brief select TIMER master mode output trigger source
1576 \param[in] timer_periph: TIMERx(x=0..7)
1577 \param[in] outrigger:
1578 only one parameter can be selected which is shown as below:
1579 \arg TIMER_TRI_OUT_SRC_RESET: the UPG bit as trigger output(TIMERx(x=0..7,9,10,12,13))
1580 \arg TIMER_TRI_OUT_SRC_ENABLE: the counter enable signal TIMER_CTL0_CEN as trigger output(TIMERx(x=0..7,9,10,12,13))
1581 \arg TIMER_TRI_OUT_SRC_UPDATE: update event as trigger output(TIMERx(x=0..7,9,10,12,13))
1582 \arg TIMER_TRI_OUT_SRC_CH0: a capture or a compare match occurred in channal0 as trigger output TRGO(TIMERx(x=0..4,7,9,10,12,13))
1583 \arg TIMER_TRI_OUT_SRC_O0CPRE: O0CPRE as trigger output(TIMERx(x=0..4,7,9,10,12,13))
1584 \arg TIMER_TRI_OUT_SRC_O1CPRE: O1CPRE as trigger output(TIMERx(x=0..4,7))
1585 \arg TIMER_TRI_OUT_SRC_O2CPRE: O2CPRE as trigger output(TIMERx(x=0..4,7))
1586 \arg TIMER_TRI_OUT_SRC_O3CPRE: O3CPRE as trigger output(TIMERx(x=0..4,7))
1587 \param[out] none
1588 \retval none
1589 */
timer_master_output_trigger_source_select(uint32_t timer_periph,uint32_t outrigger)1590 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger)
1591 {
1592 TIMER_CTL1(timer_periph) &= (~(uint32_t)TIMER_CTL1_MMC);
1593 TIMER_CTL1(timer_periph) |= (uint32_t)outrigger;
1594 }
1595
1596 /*!
1597 \brief select TIMER slave mode
1598 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1599 \param[in] slavemode:
1600 only one parameter can be selected which is shown as below:
1601 \arg TIMER_SLAVE_MODE_DISABLE: slave mode disable(TIMERx(x=0..4,7,8,11))
1602 \arg TIMER_ENCODER_MODE0: encoder mode 0(TIMERx(x=0..4,7))
1603 \arg TIMER_ENCODER_MODE1: encoder mode 1(TIMERx(x=0..4,7))
1604 \arg TIMER_ENCODER_MODE2: encoder mode 2(TIMERx(x=0..4,7))
1605 \arg TIMER_SLAVE_MODE_RESTART: restart mode(TIMERx(x=0..4,7,8,11))
1606 \arg TIMER_SLAVE_MODE_PAUSE: pause mode(TIMERx(x=0..4,7,8,11))
1607 \arg TIMER_SLAVE_MODE_EVENT: event mode(TIMERx(x=0..4,7,8,11))
1608 \arg TIMER_SLAVE_MODE_EXTERNAL0: external clock mode 0.(TIMERx(x=0..4,7,8,11))
1609 \param[out] none
1610 \retval none
1611 */
1612
timer_slave_mode_select(uint32_t timer_periph,uint32_t slavemode)1613 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode)
1614 {
1615 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1616
1617 TIMER_SMCFG(timer_periph) |= (uint32_t)slavemode;
1618 }
1619
1620 /*!
1621 \brief configure TIMER master slave mode
1622 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1623 \param[in] masterslave:
1624 only one parameter can be selected which is shown as below:
1625 \arg TIMER_MASTER_SLAVE_MODE_ENABLE: master slave mode enable
1626 \arg TIMER_MASTER_SLAVE_MODE_DISABLE: master slave mode disable
1627 \param[out] none
1628 \retval none
1629 */
timer_master_slave_mode_config(uint32_t timer_periph,uint32_t masterslave)1630 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave)
1631 {
1632 if(TIMER_MASTER_SLAVE_MODE_ENABLE == masterslave) {
1633 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_MSM;
1634 } else if(TIMER_MASTER_SLAVE_MODE_DISABLE == masterslave) {
1635 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_MSM;
1636 } else {
1637 /* illegal parameters */
1638 }
1639 }
1640
1641 /*!
1642 \brief configure TIMER external trigger input
1643 \param[in] timer_periph: TIMERx(x=0..4,7)
1644 \param[in] extprescaler:
1645 only one parameter can be selected which is shown as below:
1646 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1647 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1648 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1649 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1650 \param[in] extpolarity:
1651 only one parameter can be selected which is shown as below:
1652 \arg TIMER_ETP_FALLING: active low or falling edge active
1653 \arg TIMER_ETP_RISING: active high or rising edge active
1654 \param[in] extfilter: a value between 0 and 15
1655 \param[out] none
1656 \retval none
1657 */
timer_external_trigger_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1658 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler,
1659 uint32_t extpolarity, uint32_t extfilter)
1660 {
1661 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_ETP | TIMER_SMCFG_ETPSC | TIMER_SMCFG_ETFC));
1662 TIMER_SMCFG(timer_periph) |= (uint32_t)(extprescaler | extpolarity);
1663 TIMER_SMCFG(timer_periph) |= (uint32_t)(extfilter << 8U);
1664 }
1665
1666 /*!
1667 \brief configure TIMER quadrature decoder mode
1668 \param[in] timer_periph: TIMERx(x=0..4,7)
1669 \param[in] decomode:
1670 only one parameter can be selected which is shown as below:
1671 \arg TIMER_ENCODER_MODE0: counter counts on CI0FE0 edge depending on CI1FE1 level
1672 \arg TIMER_ENCODER_MODE1: counter counts on CI1FE1 edge depending on CI0FE0 level
1673 \arg TIMER_ENCODER_MODE2: counter counts on both CI0FE0 and CI1FE1 edges depending on the level of the other input
1674 \param[in] ic0polarity:
1675 only one parameter can be selected which is shown as below:
1676 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1677 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1678 \param[in] ic1polarity:
1679 only one parameter can be selected which is shown as below:
1680 \arg TIMER_IC_POLARITY_RISING: capture rising edge
1681 \arg TIMER_IC_POLARITY_FALLING: capture falling edge
1682 \param[out] none
1683 \retval none
1684 */
timer_quadrature_decoder_mode_config(uint32_t timer_periph,uint32_t decomode,uint16_t ic0polarity,uint16_t ic1polarity)1685 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode,
1686 uint16_t ic0polarity, uint16_t ic1polarity)
1687 {
1688 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1689 TIMER_SMCFG(timer_periph) |= (uint32_t)decomode;
1690
1691 TIMER_CHCTL0(timer_periph) &= (uint32_t)(((~(uint32_t)TIMER_CHCTL0_CH0MS)) & ((~(uint32_t)TIMER_CHCTL0_CH1MS)));
1692 TIMER_CHCTL0(timer_periph) |= (uint32_t)(TIMER_IC_SELECTION_DIRECTTI | ((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U));
1693
1694 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1695 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1696 TIMER_CHCTL2(timer_periph) |= ((uint32_t)ic0polarity | ((uint32_t)ic1polarity << 4U));
1697 }
1698
1699 /*!
1700 \brief configure TIMER internal clock mode
1701 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1702 \param[out] none
1703 \retval none
1704 */
timer_internal_clock_config(uint32_t timer_periph)1705 void timer_internal_clock_config(uint32_t timer_periph)
1706 {
1707 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1708 }
1709
1710 /*!
1711 \brief configure TIMER the internal trigger as external clock input
1712 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1713 \param[in] intrigger:
1714 only one parameter can be selected which is shown as below:
1715 \arg TIMER_SMCFG_TRGSEL_ITI0: internal trigger 0
1716 \arg TIMER_SMCFG_TRGSEL_ITI1: internal trigger 1
1717 \arg TIMER_SMCFG_TRGSEL_ITI2: internal trigger 2
1718 \arg TIMER_SMCFG_TRGSEL_ITI3: internal trigger 3
1719 \param[out] none
1720 \retval none
1721 */
timer_internal_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t intrigger)1722 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger)
1723 {
1724 timer_input_trigger_source_select(timer_periph, intrigger);
1725 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC;
1726 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1727 }
1728
1729 /*!
1730 \brief configure TIMER the external trigger as external clock input
1731 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1732 \param[in] extrigger:
1733 only one parameter can be selected which is shown as below:
1734 \arg TIMER_SMCFG_TRGSEL_CI0F_ED: TI0 edge detector
1735 \arg TIMER_SMCFG_TRGSEL_CI0FE0: filtered TIMER input 0
1736 \arg TIMER_SMCFG_TRGSEL_CI1FE1: filtered TIMER input 1
1737 \param[in] extpolarity:
1738 only one parameter can be selected which is shown as below:
1739 \arg TIMER_IC_POLARITY_RISING: active high or rising edge active
1740 \arg TIMER_IC_POLARITY_FALLING: active low or falling edge active
1741 \param[in] extfilter: a value between 0 and 15
1742 \param[out] none
1743 \retval none
1744 */
timer_external_trigger_as_external_clock_config(uint32_t timer_periph,uint32_t extrigger,uint16_t extpolarity,uint32_t extfilter)1745 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger,
1746 uint16_t extpolarity, uint32_t extfilter)
1747 {
1748 if(TIMER_SMCFG_TRGSEL_CI1FE1 == extrigger) {
1749 /* reset the CH1EN bit */
1750 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH1EN);
1751 /* reset the CH1NP bit */
1752 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH1P | TIMER_CHCTL2_CH1NP));
1753 /* set the CH1NP bit */
1754 TIMER_CHCTL2(timer_periph) |= (uint32_t)((uint32_t)extpolarity << 4U);
1755 /* reset the CH1MS bit */
1756 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1MS);
1757 /* set the CH1MS bit */
1758 TIMER_CHCTL0(timer_periph) |= (uint32_t)((uint32_t)TIMER_IC_SELECTION_DIRECTTI << 8U);
1759 /* reset the CH1CAPFLT bit */
1760 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH1CAPFLT);
1761 /* set the CH1CAPFLT bit */
1762 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 12U);
1763 /* set the CH1EN bit */
1764 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH1EN;
1765 } else {
1766 /* reset the CH0EN bit */
1767 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)TIMER_CHCTL2_CH0EN);
1768 /* reset the CH0P and CH0NP bits */
1769 TIMER_CHCTL2(timer_periph) &= (~(uint32_t)(TIMER_CHCTL2_CH0P | TIMER_CHCTL2_CH0NP));
1770 /* set the CH0P and CH0NP bits */
1771 TIMER_CHCTL2(timer_periph) |= (uint32_t)extpolarity;
1772 /* reset the CH0MS bit */
1773 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0MS);
1774 /* set the CH0MS bit */
1775 TIMER_CHCTL0(timer_periph) |= (uint32_t)TIMER_IC_SELECTION_DIRECTTI;
1776 /* reset the CH0CAPFLT bit */
1777 TIMER_CHCTL0(timer_periph) &= (~(uint32_t)TIMER_CHCTL0_CH0CAPFLT);
1778 /* reset the CH0CAPFLT bit */
1779 TIMER_CHCTL0(timer_periph) |= (uint32_t)(extfilter << 4U);
1780 /* set the CH0EN bit */
1781 TIMER_CHCTL2(timer_periph) |= (uint32_t)TIMER_CHCTL2_CH0EN;
1782 }
1783 /* select TIMER input trigger source */
1784 timer_input_trigger_source_select(timer_periph, extrigger);
1785 /* reset the SMC bit */
1786 TIMER_SMCFG(timer_periph) &= (~(uint32_t)TIMER_SMCFG_SMC);
1787 /* set the SMC bit */
1788 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SLAVE_MODE_EXTERNAL0;
1789 }
1790
1791 /*!
1792 \brief configure TIMER the external clock mode0
1793 \param[in] timer_periph: TIMERx(x=0..4,7,8,11)
1794 \param[in] extprescaler:
1795 only one parameter can be selected which is shown as below:
1796 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1797 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1798 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1799 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1800 \param[in] extpolarity:
1801 only one parameter can be selected which is shown as below:
1802 \arg TIMER_ETP_FALLING: active low or falling edge active
1803 \arg TIMER_ETP_RISING: active high or rising edge active
1804 \param[in] extfilter: a value between 0 and 15
1805 \param[out] none
1806 \retval none
1807 */
timer_external_clock_mode0_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1808 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler,
1809 uint32_t extpolarity, uint32_t extfilter)
1810 {
1811 /* configure TIMER external trigger input */
1812 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1813
1814 /* reset the SMC bit,TRGS bit */
1815 TIMER_SMCFG(timer_periph) &= (~(uint32_t)(TIMER_SMCFG_SMC | TIMER_SMCFG_TRGS));
1816 /* set the SMC bit,TRGS bit */
1817 TIMER_SMCFG(timer_periph) |= (uint32_t)(TIMER_SLAVE_MODE_EXTERNAL0 | TIMER_SMCFG_TRGSEL_ETIFP);
1818 }
1819
1820 /*!
1821 \brief configure TIMER the external clock mode1
1822 \param[in] timer_periph: TIMERx(x=0..4,7)
1823 \param[in] extprescaler:
1824 only one parameter can be selected which is shown as below:
1825 \arg TIMER_EXT_TRI_PSC_OFF: no divided
1826 \arg TIMER_EXT_TRI_PSC_DIV2: divided by 2
1827 \arg TIMER_EXT_TRI_PSC_DIV4: divided by 4
1828 \arg TIMER_EXT_TRI_PSC_DIV8: divided by 8
1829 \param[in] extpolarity:
1830 only one parameter can be selected which is shown as below:
1831 \arg TIMER_ETP_FALLING: active low or falling edge active
1832 \arg TIMER_ETP_RISING: active high or rising edge active
1833 \param[in] extfilter: a value between 0 and 15
1834 \param[out] none
1835 \retval none
1836 */
timer_external_clock_mode1_config(uint32_t timer_periph,uint32_t extprescaler,uint32_t extpolarity,uint32_t extfilter)1837 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler,
1838 uint32_t extpolarity, uint32_t extfilter)
1839 {
1840 /* configure TIMER external trigger input */
1841 timer_external_trigger_config(timer_periph, extprescaler, extpolarity, extfilter);
1842
1843 TIMER_SMCFG(timer_periph) |= (uint32_t)TIMER_SMCFG_SMC1;
1844 }
1845
1846 /*!
1847 \brief disable TIMER the external clock mode1
1848 \param[in] timer_periph: TIMERx(x=0..4,7)
1849 \param[out] none
1850 \retval none
1851 */
timer_external_clock_mode1_disable(uint32_t timer_periph)1852 void timer_external_clock_mode1_disable(uint32_t timer_periph)
1853 {
1854 TIMER_SMCFG(timer_periph) &= ~(uint32_t)TIMER_SMCFG_SMC1;
1855 }
1856
1857 /*!
1858 \brief configure TIMER channel remap function
1859 \param[in] timer_periph: TIMERx(x=1,4,10)
1860 \param[in] remap:
1861 only one parameter can be selected which is shown as below:
1862 \arg TIMER1_ITI1_RMP_TIMER7_TRGO: timer1 internal trigger input1 remap to TIMER7_TRGO
1863 \arg TIMER1_ITI1_RMP_ETHERNET_PTP: timer1 internal trigger input1 remap to ethernet PTP
1864 \arg TIMER1_ITI1_RMP_USB_FS_SOF: timer1 internal trigger input1 remap to USB FS SOF
1865 \arg TIMER1_ITI1_RMP_USB_HS_SOF: timer1 internal trigger input1 remap to USB HS SOF
1866 \arg TIMER4_CI3_RMP_GPIO: timer4 channel 3 input remap to GPIO pin
1867 \arg TIMER4_CI3_RMP_IRC32K: timer4 channel 3 input remap to IRC32K
1868 \arg TIMER4_CI3_RMP_LXTAL: timer4 channel 3 input remap to LXTAL
1869 \arg TIMER4_CI3_RMP_RTC_WAKEUP_INT: timer4 channel 3 input remap to RTC wakeup interrupt
1870 \arg TIMER10_ITI1_RMP_GPIO: timer10 internal trigger input1 remap based on GPIO setting
1871 \arg TIMER10_ITI1_RMP_RTC_HXTAL_DIV: timer10 internal trigger input1 remap HXTAL _DIV(clock used for RTC which is HXTAL clock divided by RTCDIV bits in RCU_CFG0 register)
1872 \param[out] none
1873 \retval none
1874 */
timer_channel_remap_config(uint32_t timer_periph,uint32_t remap)1875 void timer_channel_remap_config(uint32_t timer_periph, uint32_t remap)
1876 {
1877 TIMER_IRMP(timer_periph) = (uint32_t)remap;
1878 }
1879
1880 /*!
1881 \brief configure TIMER write CHxVAL register selection
1882 \param[in] timer_periph: TIMERx(x=0,1,2,13,14,15,16)
1883 \param[in] ccsel:
1884 only one parameter can be selected which is shown as below:
1885 \arg TIMER_CHVSEL_DISABLE: no effect
1886 \arg TIMER_CHVSEL_ENABLE: when write the CHxVAL register, if the write value is same as the CHxVAL value, the write access is ignored
1887 \param[out] none
1888 \retval none
1889 */
timer_write_chxval_register_config(uint32_t timer_periph,uint16_t ccsel)1890 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel)
1891 {
1892 if(TIMER_CHVSEL_ENABLE == ccsel) {
1893 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_CHVSEL;
1894 } else if(TIMER_CHVSEL_DISABLE == ccsel) {
1895 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_CHVSEL;
1896 } else {
1897 /* illegal parameters */
1898 }
1899 }
1900
1901 /*!
1902 \brief configure TIMER output value selection
1903 \param[in] timer_periph: TIMERx(x=0,7)
1904 \param[in] outsel:
1905 only one parameter can be selected which is shown as below:
1906 \arg TIMER_OUTSEL_DISABLE: no effect
1907 \arg TIMER_OUTSEL_ENABLE: if POEN and IOS is 0, the output disabled
1908 \param[out] none
1909 \retval none
1910 */
timer_output_value_selection_config(uint32_t timer_periph,uint16_t outsel)1911 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel)
1912 {
1913 if(TIMER_OUTSEL_ENABLE == outsel) {
1914 TIMER_CFG(timer_periph) |= (uint32_t)TIMER_CFG_OUTSEL;
1915 } else if(TIMER_OUTSEL_DISABLE == outsel) {
1916 TIMER_CFG(timer_periph) &= ~(uint32_t)TIMER_CFG_OUTSEL;
1917 } else {
1918 /* illegal parameters */
1919 }
1920 }
1921
1922 /*!
1923 \brief get TIMER flags
1924 \param[in] timer_periph: please refer to the following parameters
1925 \param[in] flag: the timer interrupt flags
1926 only one parameter can be selected which is shown as below:
1927 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
1928 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
1929 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
1930 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
1931 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
1932 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
1933 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
1934 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
1935 \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
1936 \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
1937 \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7)
1938 \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7)
1939 \param[out] none
1940 \retval FlagStatus: SET or RESET
1941 */
timer_flag_get(uint32_t timer_periph,uint32_t flag)1942 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag)
1943 {
1944 if(RESET != (TIMER_INTF(timer_periph) & flag)) {
1945 return SET;
1946 } else {
1947 return RESET;
1948 }
1949 }
1950
1951 /*!
1952 \brief clear TIMER flags
1953 \param[in] timer_periph: please refer to the following parameters
1954 \param[in] flag: the timer interrupt flags
1955 only one parameter can be selected which is shown as below:
1956 \arg TIMER_FLAG_UP: update flag,TIMERx(x=0..13)
1957 \arg TIMER_FLAG_CH0: channel 0 flag,TIMERx(x=0..4,7..13)
1958 \arg TIMER_FLAG_CH1: channel 1 flag,TIMERx(x=0..4,7,8,11)
1959 \arg TIMER_FLAG_CH2: channel 2 flag,TIMERx(x=0..4,7)
1960 \arg TIMER_FLAG_CH3: channel 3 flag,TIMERx(x=0..4,7)
1961 \arg TIMER_FLAG_CMT: channel control update flag,TIMERx(x=0,7)
1962 \arg TIMER_FLAG_TRG: trigger flag,TIMERx(x=0,7,8,11)
1963 \arg TIMER_FLAG_BRK: break flag,TIMERx(x=0,7)
1964 \arg TIMER_FLAG_CH0OF: channel 0 overcapture flag,TIMERx(x=0..4,7..11)
1965 \arg TIMER_FLAG_CH1OF: channel 1 overcapture flag,TIMERx(x=0..4,7,8,11)
1966 \arg TIMER_FLAG_CH2OF: channel 2 overcapture flag,TIMERx(x=0..4,7)
1967 \arg TIMER_FLAG_CH3OF: channel 3 overcapture flag,TIMERx(x=0..4,7)
1968 \param[out] none
1969 \retval none
1970 */
timer_flag_clear(uint32_t timer_periph,uint32_t flag)1971 void timer_flag_clear(uint32_t timer_periph, uint32_t flag)
1972 {
1973 TIMER_INTF(timer_periph) = (~(uint32_t)flag);
1974 }
1975
1976 /*!
1977 \brief enable the TIMER interrupt
1978 \param[in] timer_periph: please refer to the following parameters
1979 \param[in] interrupt: timer interrupt enable source
1980 only one parameter can be selected which is shown as below:
1981 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
1982 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
1983 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
1984 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
1985 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
1986 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
1987 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
1988 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
1989 \param[out] none
1990 \retval none
1991 */
timer_interrupt_enable(uint32_t timer_periph,uint32_t interrupt)1992 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt)
1993 {
1994 TIMER_DMAINTEN(timer_periph) |= (uint32_t) interrupt;
1995 }
1996
1997 /*!
1998 \brief disable the TIMER interrupt
1999 \param[in] timer_periph: please refer to the following parameters
2000 \param[in] interrupt: timer interrupt source enable
2001 only one parameter can be selected which is shown as below:
2002 \arg TIMER_INT_UP: update interrupt enable, TIMERx(x=0..13)
2003 \arg TIMER_INT_CH0: channel 0 interrupt enable, TIMERx(x=0..4,7..13)
2004 \arg TIMER_INT_CH1: channel 1 interrupt enable, TIMERx(x=0..4,7,8,11)
2005 \arg TIMER_INT_CH2: channel 2 interrupt enable, TIMERx(x=0..4,7)
2006 \arg TIMER_INT_CH3: channel 3 interrupt enable , TIMERx(x=0..4,7)
2007 \arg TIMER_INT_CMT: commutation interrupt enable, TIMERx(x=0,7)
2008 \arg TIMER_INT_TRG: trigger interrupt enable, TIMERx(x=0..4,7,8,11)
2009 \arg TIMER_INT_BRK: break interrupt enable, TIMERx(x=0,7)
2010 \param[out] none
2011 \retval none
2012 */
timer_interrupt_disable(uint32_t timer_periph,uint32_t interrupt)2013 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt)
2014 {
2015 TIMER_DMAINTEN(timer_periph) &= (~(uint32_t)interrupt);
2016 }
2017
2018 /*!
2019 \brief get timer interrupt flag
2020 \param[in] timer_periph: please refer to the following parameters
2021 \param[in] interrupt: the timer interrupt bits
2022 only one parameter can be selected which is shown as below:
2023 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
2024 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
2025 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
2026 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
2027 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
2028 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
2029 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
2030 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
2031 \param[out] none
2032 \retval FlagStatus: SET or RESET
2033 */
timer_interrupt_flag_get(uint32_t timer_periph,uint32_t interrupt)2034 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt)
2035 {
2036 uint32_t val;
2037 val = (TIMER_DMAINTEN(timer_periph) & interrupt);
2038 if((RESET != (TIMER_INTF(timer_periph) & interrupt)) && (RESET != val)) {
2039 return SET;
2040 } else {
2041 return RESET;
2042 }
2043 }
2044
2045 /*!
2046 \brief clear TIMER interrupt flag
2047 \param[in] timer_periph: please refer to the following parameters
2048 \param[in] interrupt: the timer interrupt bits
2049 only one parameter can be selected which is shown as below:
2050 \arg TIMER_INT_FLAG_UP: update interrupt flag,TIMERx(x=0..13)
2051 \arg TIMER_INT_FLAG_CH0: channel 0 interrupt flag,TIMERx(x=0..4,7..13)
2052 \arg TIMER_INT_FLAG_CH1: channel 1 interrupt flag,TIMERx(x=0..4,7,8,11)
2053 \arg TIMER_INT_FLAG_CH2: channel 2 interrupt flag,TIMERx(x=0..4,7)
2054 \arg TIMER_INT_FLAG_CH3: channel 3 interrupt flag,TIMERx(x=0..4,7)
2055 \arg TIMER_INT_FLAG_CMT: channel commutation interrupt flag,TIMERx(x=0,7)
2056 \arg TIMER_INT_FLAG_TRG: trigger interrupt flag,TIMERx(x=0,7,8,11)
2057 \arg TIMER_INT_FLAG_BRK: break interrupt flag,TIMERx(x=0,7)
2058 \param[out] none
2059 \retval none
2060 */
timer_interrupt_flag_clear(uint32_t timer_periph,uint32_t interrupt)2061 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt)
2062 {
2063 TIMER_INTF(timer_periph) = (~(uint32_t)interrupt);
2064 }
2065
