1 /*! 2 \file gd32f4xx_exmc.h 3 \brief definitions for the EXMC 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_EXMC_H 39 #define GD32F4XX_EXMC_H 40 41 #include "gd32f4xx.h" 42 43 /* EXMC definitions */ 44 #define EXMC (EXMC_BASE) /*!< EXMC register base address */ 45 #define EXMC_NOR_PSRAM (EXMC_BASE - 0x40000000) /*!< EXMC NOR/PSRAM base address */ 46 #define EXMC_NAND (EXMC_BASE - 0x30000000) /*!< EXMC NAND base address */ 47 #define EXMC_PCCARD (EXMC_BASE - 0x10000000) /*!< EXMC PC card base address */ 48 #define EXMC_SDRAM (EXMC_BASE + 0x20000000) /*!< EXMC SDRAM base address */ 49 50 /* registers definitions */ 51 /* NOR/PSRAM */ 52 #define EXMC_SNCTL0 REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register for region0 */ 53 #define EXMC_SNTCFG0 REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register for region0 */ 54 #define EXMC_SNWTCFG0 REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register for region0 */ 55 56 #define EXMC_SNCTL1 REG32(EXMC + 0x08U) /*!< EXMC SRAM/NOR flash control register for region1 */ 57 #define EXMC_SNTCFG1 REG32(EXMC + 0x0CU) /*!< EXMC SRAM/NOR flash timing configuration register for region1 */ 58 #define EXMC_SNWTCFG1 REG32(EXMC + 0x10CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region1 */ 59 60 #define EXMC_SNCTL2 REG32(EXMC + 0x10U) /*!< EXMC SRAM/NOR flash control register for region2 */ 61 #define EXMC_SNTCFG2 REG32(EXMC + 0x14U) /*!< EXMC SRAM/NOR flash timing configuration register for region2 */ 62 #define EXMC_SNWTCFG2 REG32(EXMC + 0x114U) /*!< EXMC SRAM/NOR flash write timing configuration register for region2 */ 63 64 #define EXMC_SNCTL3 REG32(EXMC + 0x18U) /*!< EXMC SRAM/NOR flash control register for region3 */ 65 #define EXMC_SNTCFG3 REG32(EXMC + 0x1CU) /*!< EXMC SRAM/NOR flash timing configuration register for region3 */ 66 #define EXMC_SNWTCFG3 REG32(EXMC + 0x11CU) /*!< EXMC SRAM/NOR flash write timing configuration register for region3 */ 67 68 /* NAND/PC card */ 69 #define EXMC_NPCTL1 REG32(EXMC + 0x60U) /*!< EXMC NAND/PC card control register for bank1 */ 70 #define EXMC_NPINTEN1 REG32(EXMC + 0x64U) /*!< EXMC NAND/PC card interrupt enable register for bank1 */ 71 #define EXMC_NPCTCFG1 REG32(EXMC + 0x68U) /*!< EXMC NAND/PC card common space timing configuration register for bank1 */ 72 #define EXMC_NPATCFG1 REG32(EXMC + 0x6CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank1 */ 73 #define EXMC_NECC1 REG32(EXMC + 0x74U) /*!< EXMC NAND ECC register */ 74 75 #define EXMC_NPCTL2 REG32(EXMC + 0x80U) /*!< EXMC NAND/PC card control register for bank2 */ 76 #define EXMC_NPINTEN2 REG32(EXMC + 0x84U) /*!< EXMC NAND/PC card interrupt enable register for bank2 */ 77 #define EXMC_NPCTCFG2 REG32(EXMC + 0x88U) /*!< EXMC NAND/PC card common space timing configuration register for bank2 */ 78 #define EXMC_NPATCFG2 REG32(EXMC + 0x8CU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank2 */ 79 #define EXMC_NECC2 REG32(EXMC + 0x94U) /*!< EXMC NAND ECC register */ 80 81 #define EXMC_NPCTL3 REG32(EXMC + 0xA0U) /*!< EXMC NAND/PC card control register for bank3 */ 82 #define EXMC_NPINTEN3 REG32(EXMC + 0xA4U) /*!< EXMC NAND/PC card interrupt enable register for bank3 */ 83 #define EXMC_NPCTCFG3 REG32(EXMC + 0xA8U) /*!< EXMC NAND/PC card common space timing configuration register for bank3 */ 84 #define EXMC_NPATCFG3 REG32(EXMC + 0xACU) /*!< EXMC NAND/PC card attribute space timing configuration register for bank3 */ 85 #define EXMC_PIOTCFG3 REG32(EXMC + 0xB0U) /*!< EXMC PC card I/O space timing configuration register for bank3 */ 86 87 /* SDRAM */ 88 #define EXMC_SDCTL0 REG32(EXMC + 0x140U) /*!< EXMC SDRAM control register for device0 */ 89 #define EXMC_SDTCFG0 REG32(EXMC + 0x148U) /*!< EXMC SDRAM timing configuration register register for device0 */ 90 91 #define EXMC_SDCTL1 REG32(EXMC + 0x144U) /*!< EXMC SDRAM control register for device1 */ 92 #define EXMC_SDTCFG1 REG32(EXMC + 0x14CU) /*!< EXMC SDRAM timing configuration register register for device1 */ 93 94 #define EXMC_SDCMD REG32(EXMC + 0x150U) /*!< EXMC SDRAM command register */ 95 #define EXMC_SDARI REG32(EXMC + 0x154U) /*!< EXMC SDRAM auto-refresh interval register */ 96 #define EXMC_SDSTAT REG32(EXMC + 0x158U) /*!< EXMC SDRAM status register */ 97 #define EXMC_SDRSCTL REG32(EXMC + 0x180U) /*!< EXMC SDRAM read sample control register */ 98 99 /* SQPI PSRAM */ 100 #define EXMC_SINIT REG32(EXMC + 0x310U) /*!< EXMC SPI initialization register */ 101 #define EXMC_SRCMD REG32(EXMC + 0x320U) /*!< EXMC SPI read command register */ 102 #define EXMC_SWCMD REG32(EXMC + 0x330U) /*!< EXMC SPI write command register */ 103 #define EXMC_SIDL REG32(EXMC + 0x340U) /*!< EXMC SPI ID low register */ 104 #define EXMC_SIDH REG32(EXMC + 0x350U) /*!< EXMC SPI ID high register */ 105 106 /* bits definitions */ 107 /* EXMC_SNCTLx,x=0..3 */ 108 #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR bank enable */ 109 #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR bank memory address/data multiplexing enable */ 110 #define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR bank memory type */ 111 #define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR bank memory data bus width */ 112 #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ 113 #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ 114 #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ 115 #define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ 116 #define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ 117 #define EXMC_SNCTL_WEN BIT(12) /*!< write enable */ 118 #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ 119 #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ 120 #define EXMC_SNCTL_ASYNCWTEN BIT(15) /*!< asynchronous wait enable */ 121 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ 122 #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write configuration */ 123 #define EXMC_SNCTL_CCK BIT(20) /*!< consecutive clock configuration */ 124 125 /* EXMC_SNTCFGx,x=0..3 */ 126 #define EXMC_SNTCFG_ASET BITS(0,3) /*!< asynchronous address setup time */ 127 #define EXMC_SNTCFG_AHLD BITS(4,7) /*!< asynchronous address hold time */ 128 #define EXMC_SNTCFG_DSET BITS(8,15) /*!< asynchronous data setup time */ 129 #define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ 130 #define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ 131 #define EXMC_SNTCFG_DLAT BITS(24,27) /*!< synchronous data latency for NOR flash */ 132 #define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 133 134 /* EXMC_SNWTCFGx,x=0..3 */ 135 #define EXMC_SNWTCFG_WASET BITS(0,3) /*!< asynchronous address setup time */ 136 #define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< asynchronous address hold time */ 137 #define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< asynchronous data setup time */ 138 #define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ 139 #define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 140 141 /* EXMC_NPCTLx,x=1..3 */ 142 #define EXMC_NPCTL_NDWTEN BIT(1) /*!< wait feature enable */ 143 #define EXMC_NPCTL_NDBKEN BIT(2) /*!< NAND bank enable */ 144 #define EXMC_NPCTL_NDTP BIT(3) /*!< NAND bank memory type */ 145 #define EXMC_NPCTL_NDW BITS(4,5) /*!< NAND bank memory data bus width */ 146 #define EXMC_NPCTL_ECCEN BIT(6) /*!< ECC enable */ 147 #define EXMC_NPCTL_CTR BITS(9,12) /*!< CLE to RE delay */ 148 #define EXMC_NPCTL_ATR BITS(13,16) /*!< ALE to RE delay */ 149 #define EXMC_NPCTL_ECCSZ BITS(17,19) /*!< ECC size */ 150 151 /* EXMC_NPINTENx,x=1..3 */ 152 #define EXMC_NPINTEN_INTRS BIT(0) /*!< interrupt rising edge status */ 153 #define EXMC_NPINTEN_INTHS BIT(1) /*!< interrupt high-level status */ 154 #define EXMC_NPINTEN_INTFS BIT(2) /*!< interrupt falling edge status */ 155 #define EXMC_NPINTEN_INTREN BIT(3) /*!< interrupt rising edge detection enable */ 156 #define EXMC_NPINTEN_INTHEN BIT(4) /*!< interrupt high-level detection enable */ 157 #define EXMC_NPINTEN_INTFEN BIT(5) /*!< interrupt falling edge detection enable */ 158 #define EXMC_NPINTEN_FFEPT BIT(6) /*!< FIFO empty flag */ 159 160 /* EXMC_NPCTCFGx,x=1..3 */ 161 #define EXMC_NPCTCFG_COMSET BITS(0,7) /*!< common memory setup time */ 162 #define EXMC_NPCTCFG_COMWAIT BITS(8,15) /*!< common memory wait time */ 163 #define EXMC_NPCTCFG_COMHLD BITS(16,23) /*!< common memory hold time */ 164 #define EXMC_NPCTCFG_COMHIZ BITS(24,31) /*!< common memory data bus HiZ time */ 165 166 /* EXMC_NPATCFGx,x=1..3 */ 167 #define EXMC_NPATCFG_ATTSET BITS(0,7) /*!< attribute memory setup time */ 168 #define EXMC_NPATCFG_ATTWAIT BITS(8,15) /*!< attribute memory wait time */ 169 #define EXMC_NPATCFG_ATTHLD BITS(16,23) /*!< attribute memory hold time */ 170 #define EXMC_NPATCFG_ATTHIZ BITS(24,31) /*!< attribute memory data bus HiZ time */ 171 172 /* EXMC_PIOTCFG3 */ 173 #define EXMC_PIOTCFG3_IOSET BITS(0,7) /*!< IO space setup time */ 174 #define EXMC_PIOTCFG3_IOWAIT BITS(8,15) /*!< IO space wait time */ 175 #define EXMC_PIOTCFG3_IOHLD BITS(16,23) /*!< IO space hold time */ 176 #define EXMC_PIOTCFG3_IOHIZ BITS(24,31) /*!< IO space data bus HiZ time */ 177 178 /* EXMC_NECCx,x=1..2 */ 179 #define EXMC_NECC_ECC BITS(0,31) /*!< ECC result */ 180 181 /* EXMC_SDCTLx,x=0..1 */ 182 #define EXMC_SDCTL_CAW BITS(0,1) /*!< column address bit width */ 183 #define EXMC_SDCTL_RAW BITS(2,3) /*!< row address bit width */ 184 #define EXMC_SDCTL_SDW BITS(4,5) /*!< SDRAM data bus width */ 185 #define EXMC_SDCTL_NBK BIT(6) /*!< number of banks */ 186 #define EXMC_SDCTL_CL BIT(7,8) /*!< CAS Latency */ 187 #define EXMC_SDCTL_WPEN BIT(9) /*!< write protection enable */ 188 #define EXMC_SDCTL_SDCLK BITS(10,11) /*!< SDRAM clock configuration */ 189 #define EXMC_SDCTL_BRSTRD BIT(12) /*!< burst read enable */ 190 #define EXMC_SDCTL_PIPED BITS(13,14) /*!< pipeline delay */ 191 192 /* EXMC_SDTCFGx,x=0..1 */ 193 #define EXMC_SDTCFG_LMRD BITS(0,3) /*!< load mode register delay */ 194 #define EXMC_SDTCFG_XSRD BITS(4,7) /*!< exit self-refresh delay */ 195 #define EXMC_SDTCFG_RASD BITS(8,11) /*!< row address select delay */ 196 #define EXMC_SDTCFG_ARFD BITS(12,15) /*!< auto refresh delay */ 197 #define EXMC_SDTCFG_WRD BITS(16,19) /*!< write recovery delay */ 198 #define EXMC_SDTCFG_RPD BITS(20,23) /*!< row precharge delay */ 199 #define EXMC_SDTCFG_RCD BITS(24,27) /*!< row to column delay */ 200 201 /* EXMC_SDCMD */ 202 #define EXMC_SDCMD_CMD BITS(0,2) /*!< command */ 203 #define EXMC_SDCMD_DS1 BIT(3) /*!< select device1 */ 204 #define EXMC_SDCMD_DS0 BIT(4) /*!< select device0 */ 205 #define EXMC_SDCMD_NARF BITS(5,8) /*!< number of successive auto-refresh */ 206 #define EXMC_SDCMD_MRC BITS(9,21) /*!< mode register content */ 207 208 /* EXMC_SDARI */ 209 #define EXMC_SDARI_REC BIT(0) /*!< refresh error flag clear */ 210 #define EXMC_SDARI_ARINTV BITS(1,13) /*!< auto-refresh interval */ 211 #define EXMC_SDARI_REIE BIT(14) /*!< interrupt refresh error enable */ 212 213 /* EXMC_SDSTAT */ 214 #define EXMC_SDSDAT_REIF BIT(0) /*!< refresh error interrupt flag */ 215 #define EXMC_SDSDAT_STA0 BITS(1,2) /*!< device0 status */ 216 #define EXMC_SDSDAT_STA1 BITS(3,4) /*!< device1 status */ 217 #define EXMC_SDSDAT_NRDY BIT(5) /*!< not ready status */ 218 219 /* EXMC_SDRSCTL */ 220 #define EXMC_SDRSCTL_RSEN BIT(0) /*!< read sample enable */ 221 #define EXMC_SDRSCTL_SSCR BIT(1) /*!< select sample cycle of read data */ 222 #define EXMC_SDRSCTL_SDSC BITS(4,7) /*!< select the delayed sample clock of read data */ 223 224 /* EXMC_SINIT */ 225 #define EXMC_SINIT_CMDBIT BITS(16,17) /*!< bit number of SPI PSRAM command phase */ 226 #define EXMC_SINIT_ARDBIT BITS(24,28) /*!< bit number of SPI PSRAM address phase */ 227 #define EXMC_SINIT_IDL BITS(29,30) /*!< SPI PSRAM ID length */ 228 #define EXMC_SINIT_POL BIT(31) /*!< read data sample polarity */ 229 230 /* EXMC_SRCMD */ 231 #define EXMC_SRCMD_RCMD BITS(0,15) /*!< SPI read command for AHB read transfer */ 232 #define EXMC_SRCMD_RWAITCYCLE BITS(16,19) /*!< SPI read wait cycle number after address phase */ 233 #define EXMC_SRCMD_RMODE BITS(20,21) /*!< SPI PSRAM read command mode */ 234 #define EXMC_SRCMD_RDID BIT(31) /*!< send SPI read ID command */ 235 236 /* EXMC_SWCMD */ 237 #define EXMC_SWCMD_WCMD BITS(0,15) /*!< SPI write command for AHB write transfer */ 238 #define EXMC_SWCMD_WWAITCYCLE BITS(16,19) /*!< SPI write wait cycle number after address phase */ 239 #define EXMC_SWCMD_WMODE BITS(20,21) /*!< SPI PSRAM write command mode */ 240 #define EXMC_SWCMD_SC BIT(31) /*!< send SPI special command */ 241 242 /* EXMC_SIDL */ 243 #define EXMC_SIDL_SIDL BITS(0,31) /*!< ID low data saved for SPI read ID command */ 244 245 /* EXMC_SIDH */ 246 #define EXMC_SIDL_SIDH BITS(0,31) /*!< ID high Data saved for SPI read ID command */ 247 248 /* constants definitions */ 249 /* EXMC NOR/SRAM timing initialize structure */ 250 typedef struct 251 { 252 uint32_t asyn_access_mode; /*!< asynchronous access mode */ 253 uint32_t syn_data_latency; /*!< configure the data latency */ 254 uint32_t syn_clk_division; /*!< configure the clock divide ratio */ 255 uint32_t bus_latency; /*!< configure the bus latency */ 256 uint32_t asyn_data_setuptime; /*!< configure the data setup time, asynchronous access mode valid */ 257 uint32_t asyn_address_holdtime; /*!< configure the address hold time, asynchronous access mode valid */ 258 uint32_t asyn_address_setuptime; /*!< configure the address setup time, asynchronous access mode valid */ 259 }exmc_norsram_timing_parameter_struct; 260 261 /* EXMC NOR/SRAM initialize structure */ 262 typedef struct 263 { 264 uint32_t norsram_region; /*!< select the region of EXMC NOR/SRAM bank */ 265 uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ 266 uint32_t extended_mode; /*!< enable or disable the extended mode */ 267 uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ 268 uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ 269 uint32_t memory_write; /*!< enable or disable the write operation */ 270 uint32_t nwait_config; /*!< NWAIT signal configuration */ 271 uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ 272 uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ 273 uint32_t burst_mode; /*!< enable or disable the burst mode */ 274 uint32_t databus_width; /*!< specifies the databus width of external memory */ 275 uint32_t memory_type; /*!< specifies the type of external memory */ 276 uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ 277 exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extendedmode is not used or the timing 278 parameters for read if the extendedmode is used. */ 279 exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extendedmode is used. */ 280 }exmc_norsram_parameter_struct; 281 282 /* EXMC NAND/PC card timing initialize structure */ 283 typedef struct 284 { 285 uint32_t databus_hiztime; /*!< configure the dadtabus HiZ time for write operation */ 286 uint32_t holdtime; /*!< configure the address hold time(or the data hold time for write operation) */ 287 uint32_t waittime; /*!< configure the minimum wait time */ 288 uint32_t setuptime; /*!< configure the address setup time */ 289 }exmc_nand_pccard_timing_parameter_struct; 290 291 /* EXMC NAND initialize structure */ 292 typedef struct 293 { 294 uint32_t nand_bank; /*!< select the bank of NAND */ 295 uint32_t ecc_size; /*!< the page size for the ECC calculation */ 296 uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ 297 uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ 298 uint32_t ecc_logic; /*!< enable or disable the ECC calculation logic */ 299 uint32_t databus_width; /*!< the NAND flash databus width */ 300 uint32_t wait_feature; /*!< enable or disable the wait feature */ 301 exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for NAND flash common space */ 302 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for NAND flash attribute space */ 303 }exmc_nand_parameter_struct; 304 305 /* EXMC PC card initialize structure */ 306 typedef struct 307 { 308 uint32_t atr_latency; /*!< configure the latency of ALE low to RB low */ 309 uint32_t ctr_latency; /*!< configure the latency of CLE low to RB low */ 310 uint32_t wait_feature; /*!< enable or disable the wait feature */ 311 exmc_nand_pccard_timing_parameter_struct* common_space_timing; /*!< the timing parameters for PC card common space */ 312 exmc_nand_pccard_timing_parameter_struct* attribute_space_timing; /*!< the timing parameters for PC card attribute space */ 313 exmc_nand_pccard_timing_parameter_struct* io_space_timing; /*!< the timing parameters for PC card IO space */ 314 }exmc_pccard_parameter_struct; 315 316 /* EXMC SDRAM timing initialize structure */ 317 typedef struct 318 { 319 uint32_t row_to_column_delay; /*!< configure the row to column delay */ 320 uint32_t row_precharge_delay; /*!< configure the row precharge delay */ 321 uint32_t write_recovery_delay; /*!< configure the write recovery delay */ 322 uint32_t auto_refresh_delay; /*!< configure the auto refresh delay */ 323 uint32_t row_address_select_delay; /*!< configure the row address select delay */ 324 uint32_t exit_selfrefresh_delay; /*!< configure the exit self-refresh delay */ 325 uint32_t load_mode_register_delay; /*!< configure the load mode register delay */ 326 }exmc_sdram_timing_parameter_struct; 327 328 /* EXMC SDRAM initialize structure */ 329 typedef struct 330 { 331 uint32_t sdram_device; /*!< device of SDRAM */ 332 uint32_t pipeline_read_delay; /*!< the delay for reading data after CAS latency in HCLK clock cycles */ 333 uint32_t brust_read_switch; /*!< enable or disable the burst read */ 334 uint32_t sdclock_config; /*!< the SDCLK memory clock for both SDRAM banks */ 335 uint32_t write_protection; /*!< enable or disable SDRAM bank write protection function */ 336 uint32_t cas_latency; /*!< configure the SDRAM CAS latency */ 337 uint32_t internal_bank_number; /*!< the number of internal bank */ 338 uint32_t data_width; /*!< the databus width of SDRAM memory */ 339 uint32_t row_address_width; /*!< the bit width of a row address */ 340 uint32_t column_address_width; /*!< the bit width of a column address */ 341 exmc_sdram_timing_parameter_struct* timing; /*!< the timing parameters for write and read SDRAM */ 342 }exmc_sdram_parameter_struct; 343 344 /* EXMC SDRAM command initialize structure */ 345 typedef struct 346 { 347 uint32_t mode_register_content; /*!< the SDRAM mode register content */ 348 uint32_t auto_refresh_number; /*!< the number of successive auto-refresh cycles will be send when CMD = 011 */ 349 uint32_t bank_select; /*!< the bank which command will be sent to */ 350 uint32_t command; /*!< the commands that will be sent to SDRAM */ 351 }exmc_sdram_command_parameter_struct; 352 353 /* EXMC SQPISRAM initialize structure */ 354 typedef struct{ 355 uint32_t sample_polarity; /*!< read data sample polarity */ 356 uint32_t id_length; /*!< SPI PSRAM ID length */ 357 uint32_t address_bits; /*!< bit number of SPI PSRAM address phase */ 358 uint32_t command_bits; /*!< bit number of SPI PSRAM command phase */ 359 }exmc_sqpipsram_parameter_struct; 360 361 /* EXMC register address */ 362 #define EXMC_SNCTL(region) REG32(EXMC + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash control registers, region = 0,1,2,3 */ 363 #define EXMC_SNTCFG(region) REG32(EXMC + 0x04U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash timing configuration registers, region = 0,1,2,3 */ 364 #define EXMC_SNWTCFG(region) REG32(EXMC + 0x104U + 0x08U*((uint32_t)(region))) /*!< EXMC SRAM/NOR flash write timing configuration registers, region = 0,1,2,3 */ 365 366 #define EXMC_NPCTL(bank) REG32(EXMC + 0x40U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card control registers, bank = 1,2,3 */ 367 #define EXMC_NPINTEN(bank) REG32(EXMC + 0x44U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card interrupt enable registers, bank = 1,2,3 */ 368 #define EXMC_NPCTCFG(bank) REG32(EXMC + 0x48U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card common space timing configuration registers, bank = 1,2,3 */ 369 #define EXMC_NPATCFG(bank) REG32(EXMC + 0x4CU + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND/PC card attribute space timing configuration registers, bank = 1,2,3 */ 370 #define EXMC_NECC(bank) REG32(EXMC + 0x54U + 0x20U*((uint32_t)(bank))) /*!< EXMC NAND ECC registers, bank = 1,2 */ 371 372 #define EXMC_SDCTL(device) REG32(EXMC + 0x140U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM control registers,device = 0,1 */ 373 #define EXMC_SDTCFG(device) REG32(EXMC + 0x148U + 0x4U*(((uint32_t)(device)) - 0x4U)) /*!< EXMC SDRAM timing configuration registers,device = 0,1 */ 374 375 /* CRAM page size */ 376 #define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) 377 #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ 378 #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ 379 #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ 380 #define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ 381 #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ 382 383 /* NOR bank memory data bus width */ 384 #define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 385 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width is 8 bits */ 386 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width is 16 bits */ 387 388 /* NOR bank memory type */ 389 #define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 390 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ 391 #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ 392 #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ 393 394 /* asynchronous access mode */ 395 #define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) 396 #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ 397 #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ 398 #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ 399 #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ 400 401 /* data latency for NOR flash */ 402 #define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 403 #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency of first burst access is 2 EXMC_CLK */ 404 #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency of first burst access is 3 EXMC_CLK */ 405 #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency of first burst access is 4 EXMC_CLK */ 406 #define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency of first burst access is 5 EXMC_CLK */ 407 #define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency of first burst access is 6 EXMC_CLK */ 408 #define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency of first burst access is 7 EXMC_CLK */ 409 #define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency of first burst access is 8 EXMC_CLK */ 410 #define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency of first burst access is 9 EXMC_CLK */ 411 #define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency of first burst access is 10 EXMC_CLK */ 412 #define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency of first burst access is 11 EXMC_CLK */ 413 #define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency of first burst access is 12 EXMC_CLK */ 414 #define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency of first burst access is 13 EXMC_CLK */ 415 #define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency of first burst access is 14 EXMC_CLK */ 416 #define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency of first burst access is 15 EXMC_CLK */ 417 #define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency of first burst access is 16 EXMC_CLK */ 418 #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency of first burst access is 17 EXMC_CLK */ 419 420 /* synchronous clock divide ratio */ 421 #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) 422 #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ 423 #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< EXMC_CLK = 2*HCLK */ 424 #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< EXMC_CLK = 3*HCLK */ 425 #define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< EXMC_CLK = 4*HCLK */ 426 #define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< EXMC_CLK = 5*HCLK */ 427 #define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< EXMC_CLK = 6*HCLK */ 428 #define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< EXMC_CLK = 7*HCLK */ 429 #define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< EXMC_CLK = 8*HCLK */ 430 #define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< EXMC_CLK = 9*HCLK */ 431 #define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< EXMC_CLK = 10*HCLK */ 432 #define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< EXMC_CLK = 11*HCLK */ 433 #define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< EXMC_CLK = 12*HCLK */ 434 #define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< EXMC_CLK = 13*HCLK */ 435 #define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< EXMC_CLK = 14*HCLK*/ 436 #define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< EXMC_CLK = 15*HCLK */ 437 #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< EXMC_CLK = 16*HCLK */ 438 439 /* ECC size */ 440 #define NPCTL_ECCSZ(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) 441 #define EXMC_ECC_SIZE_256BYTES NPCTL_ECCSZ(0) /* ECC size is 256 bytes */ 442 #define EXMC_ECC_SIZE_512BYTES NPCTL_ECCSZ(1) /* ECC size is 512 bytes */ 443 #define EXMC_ECC_SIZE_1024BYTES NPCTL_ECCSZ(2) /* ECC size is 1024 bytes */ 444 #define EXMC_ECC_SIZE_2048BYTES NPCTL_ECCSZ(3) /* ECC size is 2048 bytes */ 445 #define EXMC_ECC_SIZE_4096BYTES NPCTL_ECCSZ(4) /* ECC size is 4096 bytes */ 446 #define EXMC_ECC_SIZE_8192BYTES NPCTL_ECCSZ(5) /* ECC size is 8192 bytes */ 447 448 /* ALE to RE delay */ 449 #define NPCTL_ATR(regval) (BITS(13,16) & ((uint32_t)(regval) << 13)) 450 #define EXMC_ALE_RE_DELAY_1_HCLK NPCTL_ATR(0) /* ALE to RE delay = 1*HCLK */ 451 #define EXMC_ALE_RE_DELAY_2_HCLK NPCTL_ATR(1) /* ALE to RE delay = 2*HCLK */ 452 #define EXMC_ALE_RE_DELAY_3_HCLK NPCTL_ATR(2) /* ALE to RE delay = 3*HCLK */ 453 #define EXMC_ALE_RE_DELAY_4_HCLK NPCTL_ATR(3) /* ALE to RE delay = 4*HCLK */ 454 #define EXMC_ALE_RE_DELAY_5_HCLK NPCTL_ATR(4) /* ALE to RE delay = 5*HCLK */ 455 #define EXMC_ALE_RE_DELAY_6_HCLK NPCTL_ATR(5) /* ALE to RE delay = 6*HCLK */ 456 #define EXMC_ALE_RE_DELAY_7_HCLK NPCTL_ATR(6) /* ALE to RE delay = 7*HCLK */ 457 #define EXMC_ALE_RE_DELAY_8_HCLK NPCTL_ATR(7) /* ALE to RE delay = 8*HCLK */ 458 #define EXMC_ALE_RE_DELAY_9_HCLK NPCTL_ATR(8) /* ALE to RE delay = 9*HCLK */ 459 #define EXMC_ALE_RE_DELAY_10_HCLK NPCTL_ATR(9) /* ALE to RE delay = 10*HCLK */ 460 #define EXMC_ALE_RE_DELAY_11_HCLK NPCTL_ATR(10) /* ALE to RE delay = 11*HCLK */ 461 #define EXMC_ALE_RE_DELAY_12_HCLK NPCTL_ATR(11) /* ALE to RE delay = 12*HCLK */ 462 #define EXMC_ALE_RE_DELAY_13_HCLK NPCTL_ATR(12) /* ALE to RE delay = 13*HCLK */ 463 #define EXMC_ALE_RE_DELAY_14_HCLK NPCTL_ATR(13) /* ALE to RE delay = 14*HCLK */ 464 #define EXMC_ALE_RE_DELAY_15_HCLK NPCTL_ATR(14) /* ALE to RE delay = 15*HCLK */ 465 #define EXMC_ALE_RE_DELAY_16_HCLK NPCTL_ATR(15) /* ALE to RE delay = 16*HCLK */ 466 467 /* CLE to RE delay */ 468 #define NPCTL_CTR(regval) (BITS(9,12) & ((uint32_t)(regval) << 9)) 469 #define EXMC_CLE_RE_DELAY_1_HCLK NPCTL_CTR(0) /* CLE to RE delay = 1*HCLK */ 470 #define EXMC_CLE_RE_DELAY_2_HCLK NPCTL_CTR(1) /* CLE to RE delay = 2*HCLK */ 471 #define EXMC_CLE_RE_DELAY_3_HCLK NPCTL_CTR(2) /* CLE to RE delay = 3*HCLK */ 472 #define EXMC_CLE_RE_DELAY_4_HCLK NPCTL_CTR(3) /* CLE to RE delay = 4*HCLK */ 473 #define EXMC_CLE_RE_DELAY_5_HCLK NPCTL_CTR(4) /* CLE to RE delay = 5*HCLK */ 474 #define EXMC_CLE_RE_DELAY_6_HCLK NPCTL_CTR(5) /* CLE to RE delay = 6*HCLK */ 475 #define EXMC_CLE_RE_DELAY_7_HCLK NPCTL_CTR(6) /* CLE to RE delay = 7*HCLK */ 476 #define EXMC_CLE_RE_DELAY_8_HCLK NPCTL_CTR(7) /* CLE to RE delay = 8*HCLK */ 477 #define EXMC_CLE_RE_DELAY_9_HCLK NPCTL_CTR(8) /* CLE to RE delay = 9*HCLK */ 478 #define EXMC_CLE_RE_DELAY_10_HCLK NPCTL_CTR(9) /* CLE to RE delay = 10*HCLK */ 479 #define EXMC_CLE_RE_DELAY_11_HCLK NPCTL_CTR(10) /* CLE to RE delay = 11*HCLK */ 480 #define EXMC_CLE_RE_DELAY_12_HCLK NPCTL_CTR(11) /* CLE to RE delay = 12*HCLK */ 481 #define EXMC_CLE_RE_DELAY_13_HCLK NPCTL_CTR(12) /* CLE to RE delay = 13*HCLK */ 482 #define EXMC_CLE_RE_DELAY_14_HCLK NPCTL_CTR(13) /* CLE to RE delay = 14*HCLK */ 483 #define EXMC_CLE_RE_DELAY_15_HCLK NPCTL_CTR(14) /* CLE to RE delay = 15*HCLK */ 484 #define EXMC_CLE_RE_DELAY_16_HCLK NPCTL_CTR(15) /* CLE to RE delay = 16*HCLK */ 485 486 /* NAND bank memory data bus width */ 487 #define NPCTL_NDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 488 #define EXMC_NAND_DATABUS_WIDTH_8B NPCTL_NDW(0) /*!< NAND data width is 8 bits */ 489 #define EXMC_NAND_DATABUS_WIDTH_16B NPCTL_NDW(1) /*!< NAND data width is 16 bits */ 490 491 /* SDRAM pipeline delay */ 492 #define SDCTL_PIPED(regval) (BITS(13,14) & ((uint32_t)(regval) << 13)) 493 #define EXMC_PIPELINE_DELAY_0_HCLK SDCTL_PIPED(0) /*!< 0 HCLK clock cycle delay */ 494 #define EXMC_PIPELINE_DELAY_1_HCLK SDCTL_PIPED(1) /*!< 1 HCLK clock cycle delay */ 495 #define EXMC_PIPELINE_DELAY_2_HCLK SDCTL_PIPED(2) /*!< 2 HCLK clock cycle delay */ 496 497 /* SDRAM clock configuration */ 498 #define SDCTL_SDCLK(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) 499 #define EXMC_SDCLK_DISABLE SDCTL_SDCLK(0) /*!< SDCLK memory clock disabled */ 500 #define EXMC_SDCLK_PERIODS_2_HCLK SDCTL_SDCLK(2) /*!< SDCLK memory period = 2*HCLK */ 501 #define EXMC_SDCLK_PERIODS_3_HCLK SDCTL_SDCLK(3) /*!< SDCLK memory period = 3*HCLK */ 502 503 /* CAS latency */ 504 #define SDCTL_CL(regval) (BITS(7,8) & ((uint32_t)(regval) << 7)) 505 #define EXMC_CAS_LATENCY_1_SDCLK SDCTL_CL(1) /*!< CAS latency is 1 memory clock cycle */ 506 #define EXMC_CAS_LATENCY_2_SDCLK SDCTL_CL(2) /*!< CAS latency is 2 memory clock cycle */ 507 #define EXMC_CAS_LATENCY_3_SDCLK SDCTL_CL(3) /*!< CAS latency is 3 memory clock cycle */ 508 509 /* SDRAM data bus width */ 510 #define SDCTL_SDW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 511 #define EXMC_SDRAM_DATABUS_WIDTH_8B SDCTL_SDW(0) /*!< SDRAM data width 8 bits */ 512 #define EXMC_SDRAM_DATABUS_WIDTH_16B SDCTL_SDW(1) /*!< SDRAM data width 16 bits */ 513 #define EXMC_SDRAM_DATABUS_WIDTH_32B SDCTL_SDW(2) /*!< SDRAM data width 32 bits */ 514 515 /* SDRAM row address bit width */ 516 #define SDCTL_RAW(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 517 #define EXMC_SDRAM_ROW_ADDRESS_11 SDCTL_RAW(0) /*!< row address bit width is 11 bits */ 518 #define EXMC_SDRAM_ROW_ADDRESS_12 SDCTL_RAW(1) /*!< row address bit width is 12 bits */ 519 #define EXMC_SDRAM_ROW_ADDRESS_13 SDCTL_RAW(2) /*!< row address bit width is 13 bits */ 520 521 /* SDRAM column address bit width */ 522 #define SDCTL_CAW(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 523 #define EXMC_SDRAM_COW_ADDRESS_8 SDCTL_CAW(0) /*!< column address bit width is 8 bits */ 524 #define EXMC_SDRAM_COW_ADDRESS_9 SDCTL_CAW(1) /*!< column address bit width is 9 bits */ 525 #define EXMC_SDRAM_COW_ADDRESS_10 SDCTL_CAW(2) /*!< column address bit width is 10 bits */ 526 #define EXMC_SDRAM_COW_ADDRESS_11 SDCTL_CAW(3) /*!< column address bit width is 11 bits */ 527 528 /* SDRAM number of successive auto-refresh */ 529 #define SDCMD_NARF(regval) (BITS(5,8) & ((uint32_t)(regval) << 5)) 530 #define EXMC_SDRAM_AUTO_REFLESH_1_SDCLK SDCMD_NARF(0) /*!< 1 auto-refresh cycle */ 531 #define EXMC_SDRAM_AUTO_REFLESH_2_SDCLK SDCMD_NARF(1) /*!< 2 auto-refresh cycles */ 532 #define EXMC_SDRAM_AUTO_REFLESH_3_SDCLK SDCMD_NARF(2) /*!< 3 auto-refresh cycles */ 533 #define EXMC_SDRAM_AUTO_REFLESH_4_SDCLK SDCMD_NARF(3) /*!< 4 auto-refresh cycles */ 534 #define EXMC_SDRAM_AUTO_REFLESH_5_SDCLK SDCMD_NARF(4) /*!< 5 auto-refresh cycles */ 535 #define EXMC_SDRAM_AUTO_REFLESH_6_SDCLK SDCMD_NARF(5) /*!< 6 auto-refresh cycles */ 536 #define EXMC_SDRAM_AUTO_REFLESH_7_SDCLK SDCMD_NARF(6) /*!< 7 auto-refresh cycles */ 537 #define EXMC_SDRAM_AUTO_REFLESH_8_SDCLK SDCMD_NARF(7) /*!< 8 auto-refresh cycles */ 538 #define EXMC_SDRAM_AUTO_REFLESH_9_SDCLK SDCMD_NARF(8) /*!< 9 auto-refresh cycles */ 539 #define EXMC_SDRAM_AUTO_REFLESH_10_SDCLK SDCMD_NARF(9) /*!< 10 auto-refresh cycles */ 540 #define EXMC_SDRAM_AUTO_REFLESH_11_SDCLK SDCMD_NARF(10) /*!< 11 auto-refresh cycles */ 541 #define EXMC_SDRAM_AUTO_REFLESH_12_SDCLK SDCMD_NARF(11) /*!< 12 auto-refresh cycles */ 542 #define EXMC_SDRAM_AUTO_REFLESH_13_SDCLK SDCMD_NARF(12) /*!< 13 auto-refresh cycles */ 543 #define EXMC_SDRAM_AUTO_REFLESH_14_SDCLK SDCMD_NARF(13) /*!< 14 auto-refresh cycles */ 544 #define EXMC_SDRAM_AUTO_REFLESH_15_SDCLK SDCMD_NARF(14) /*!< 15 auto-refresh cycles */ 545 546 /* SDRAM command selection */ 547 #define SDCMD_CMD(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 548 #define EXMC_SDRAM_NORMAL_OPERATION SDCMD_CMD(0) /*!< normal operation command */ 549 #define EXMC_SDRAM_CLOCK_ENABLE SDCMD_CMD(1) /*!< clock enable command */ 550 #define EXMC_SDRAM_PRECHARGE_ALL SDCMD_CMD(2) /*!< precharge all command */ 551 #define EXMC_SDRAM_AUTO_REFRESH SDCMD_CMD(3) /*!< auto-refresh command */ 552 #define EXMC_SDRAM_LOAD_MODE_REGISTER SDCMD_CMD(4) /*!< load mode register command */ 553 #define EXMC_SDRAM_SELF_REFRESH SDCMD_CMD(5) /*!< self-refresh command */ 554 #define EXMC_SDRAM_POWERDOWN_ENTRY SDCMD_CMD(6) /*!< power-down entry command */ 555 556 /* SDRAM the delayed sample clock of read data */ 557 #define SDRSCTL_SDSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 558 #define EXMC_SDRAM_0_DELAY_CELL SDRSCTL_SDSC(0) /*!< select the clock after 0 delay cell */ 559 #define EXMC_SDRAM_1_DELAY_CELL SDRSCTL_SDSC(1) /*!< select the clock after 1 delay cell */ 560 #define EXMC_SDRAM_2_DELAY_CELL SDRSCTL_SDSC(2) /*!< select the clock after 2 delay cell */ 561 #define EXMC_SDRAM_3_DELAY_CELL SDRSCTL_SDSC(3) /*!< select the clock after 3 delay cell */ 562 #define EXMC_SDRAM_4_DELAY_CELL SDRSCTL_SDSC(4) /*!< select the clock after 4 delay cell */ 563 #define EXMC_SDRAM_5_DELAY_CELL SDRSCTL_SDSC(5) /*!< select the clock after 5 delay cell */ 564 #define EXMC_SDRAM_6_DELAY_CELL SDRSCTL_SDSC(6) /*!< select the clock after 6 delay cell */ 565 #define EXMC_SDRAM_7_DELAY_CELL SDRSCTL_SDSC(7) /*!< select the clock after 7 delay cell */ 566 #define EXMC_SDRAM_8_DELAY_CELL SDRSCTL_SDSC(8) /*!< select the clock after 8 delay cell */ 567 #define EXMC_SDRAM_9_DELAY_CELL SDRSCTL_SDSC(9) /*!< select the clock after 9 delay cell */ 568 #define EXMC_SDRAM_10_DELAY_CELL SDRSCTL_SDSC(10) /*!< select the clock after 10 delay cell */ 569 #define EXMC_SDRAM_11_DELAY_CELL SDRSCTL_SDSC(11) /*!< select the clock after 11 delay cell */ 570 #define EXMC_SDRAM_12_DELAY_CELL SDRSCTL_SDSC(12) /*!< select the clock after 12 delay cell */ 571 #define EXMC_SDRAM_13_DELAY_CELL SDRSCTL_SDSC(13) /*!< select the clock after 13 delay cell */ 572 #define EXMC_SDRAM_14_DELAY_CELL SDRSCTL_SDSC(14) /*!< select the clock after 14 delay cell */ 573 #define EXMC_SDRAM_15_DELAY_CELL SDRSCTL_SDSC(15) /*!< select the clock after 15 delay cell */ 574 575 /* SPI PSRAM ID length */ 576 #define SINIT_IDL(regval) (BITS(29,30) & ((uint32_t)(regval) << 29)) 577 #define EXMC_SQPIPSRAM_ID_LENGTH_64B SINIT_IDL(0) /*!< SPI PSRAM ID length is 64 bits */ 578 #define EXMC_SQPIPSRAM_ID_LENGTH_32B SINIT_IDL(1) /*!< SPI PSRAM ID length is 32 bits */ 579 #define EXMC_SQPIPSRAM_ID_LENGTH_16B SINIT_IDL(2) /*!< SPI PSRAM ID length is 16 bits */ 580 #define EXMC_SQPIPSRAM_ID_LENGTH_8B SINIT_IDL(3) /*!< SPI PSRAM ID length is 8 bits */ 581 582 /* SPI PSRAM bit number of address phase */ 583 #define SINIT_ADRBIT(regval) (BITS(24,28) & ((uint32_t)(regval) << 24)) 584 #define EXMC_SQPIPSRAM_ADDR_LENGTH_1B SINIT_ADRBIT(1) /*!< SPI PSRAM address is 1 bit */ 585 #define EXMC_SQPIPSRAM_ADDR_LENGTH_2B SINIT_ADRBIT(2) /*!< SPI PSRAM address is 2 bits */ 586 #define EXMC_SQPIPSRAM_ADDR_LENGTH_3B SINIT_ADRBIT(3) /*!< SPI PSRAM address is 3 bits */ 587 #define EXMC_SQPIPSRAM_ADDR_LENGTH_4B SINIT_ADRBIT(4) /*!< SPI PSRAM address is 4 bits */ 588 #define EXMC_SQPIPSRAM_ADDR_LENGTH_5B SINIT_ADRBIT(5) /*!< SPI PSRAM address is 5 bits */ 589 #define EXMC_SQPIPSRAM_ADDR_LENGTH_6B SINIT_ADRBIT(6) /*!< SPI PSRAM address is 6 bits */ 590 #define EXMC_SQPIPSRAM_ADDR_LENGTH_7B SINIT_ADRBIT(7) /*!< SPI PSRAM address is 7 bits */ 591 #define EXMC_SQPIPSRAM_ADDR_LENGTH_8B SINIT_ADRBIT(8) /*!< SPI PSRAM address is 8 bits */ 592 #define EXMC_SQPIPSRAM_ADDR_LENGTH_9B SINIT_ADRBIT(9) /*!< SPI PSRAM address is 9 bits */ 593 #define EXMC_SQPIPSRAM_ADDR_LENGTH_10B SINIT_ADRBIT(10) /*!< SPI PSRAM address is 10 bits */ 594 #define EXMC_SQPIPSRAM_ADDR_LENGTH_11B SINIT_ADRBIT(11) /*!< SPI PSRAM address is 11 bits */ 595 #define EXMC_SQPIPSRAM_ADDR_LENGTH_12B SINIT_ADRBIT(12) /*!< SPI PSRAM address is 12 bits */ 596 #define EXMC_SQPIPSRAM_ADDR_LENGTH_13B SINIT_ADRBIT(13) /*!< SPI PSRAM address is 13 bits */ 597 #define EXMC_SQPIPSRAM_ADDR_LENGTH_14B SINIT_ADRBIT(14) /*!< SPI PSRAM address is 14 bits */ 598 #define EXMC_SQPIPSRAM_ADDR_LENGTH_15B SINIT_ADRBIT(15) /*!< SPI PSRAM address is 15 bits */ 599 #define EXMC_SQPIPSRAM_ADDR_LENGTH_16B SINIT_ADRBIT(16) /*!< SPI PSRAM address is 16 bits */ 600 #define EXMC_SQPIPSRAM_ADDR_LENGTH_17B SINIT_ADRBIT(17) /*!< SPI PSRAM address is 17 bits */ 601 #define EXMC_SQPIPSRAM_ADDR_LENGTH_18B SINIT_ADRBIT(18) /*!< SPI PSRAM address is 18 bits */ 602 #define EXMC_SQPIPSRAM_ADDR_LENGTH_19B SINIT_ADRBIT(19) /*!< SPI PSRAM address is 19 bits */ 603 #define EXMC_SQPIPSRAM_ADDR_LENGTH_20B SINIT_ADRBIT(20) /*!< SPI PSRAM address is 20 bits */ 604 #define EXMC_SQPIPSRAM_ADDR_LENGTH_21B SINIT_ADRBIT(21) /*!< SPI PSRAM address is 21 bits */ 605 #define EXMC_SQPIPSRAM_ADDR_LENGTH_22B SINIT_ADRBIT(22) /*!< SPI PSRAM address is 22 bits */ 606 #define EXMC_SQPIPSRAM_ADDR_LENGTH_23B SINIT_ADRBIT(23) /*!< SPI PSRAM address is 23 bits */ 607 #define EXMC_SQPIPSRAM_ADDR_LENGTH_24B SINIT_ADRBIT(24) /*!< SPI PSRAM address is 24 bits */ 608 #define EXMC_SQPIPSRAM_ADDR_LENGTH_25B SINIT_ADRBIT(25) /*!< SPI PSRAM address is 25 bits */ 609 #define EXMC_SQPIPSRAM_ADDR_LENGTH_26B SINIT_ADRBIT(26) /*!< SPI PSRAM address is 26 bits */ 610 611 /* SPI PSRAM bit number of command phase */ 612 #define SINIT_CMDBIT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) 613 #define EXMC_SQPIPSRAM_COMMAND_LENGTH_4B SINIT_CMDBIT(0) /*!< SPI PSRAM command is 4 bits */ 614 #define EXMC_SQPIPSRAM_COMMAND_LENGTH_8B SINIT_CMDBIT(1) /*!< SPI PSRAM command is 8 bits */ 615 #define EXMC_SQPIPSRAM_COMMAND_LENGTH_16B SINIT_CMDBIT(2) /*!< SPI PSRAM command is 16 bits */ 616 617 /* SPI PSRAM read command mode */ 618 #define SRCMD_RMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 619 #define EXMC_SQPIPSRAM_READ_MODE_DISABLE SRCMD_RMODE(0) /*!< not SPI mode */ 620 #define EXMC_SQPIPSRAM_READ_MODE_SPI SRCMD_RMODE(1) /*!< SPI mode */ 621 #define EXMC_SQPIPSRAM_READ_MODE_SQPI SRCMD_RMODE(2) /*!< SQPI mode */ 622 #define EXMC_SQPIPSRAM_READ_MODE_QPI SRCMD_RMODE(3) /*!< QPI mode */ 623 624 /* SPI PSRAM write command mode */ 625 #define SRCMD_WMODE(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 626 #define EXMC_SQPIPSRAM_WRITE_MODE_DISABLE SRCMD_WMODE(0) /*!< not SPI mode */ 627 #define EXMC_SQPIPSRAM_WRITE_MODE_SPI SRCMD_WMODE(1) /*!< SPI mode */ 628 #define EXMC_SQPIPSRAM_WRITE_MODE_SQPI SRCMD_WMODE(2) /*!< SQPI mode */ 629 #define EXMC_SQPIPSRAM_WRITE_MODE_QPI SRCMD_WMODE(3) /*!< QPI mode */ 630 631 /* EXMC NOR/SRAM bank region definition */ 632 #define EXMC_BANK0_NORSRAM_REGION0 ((uint32_t)0x00000000U) /*!< bank0 NOR/SRAM region0 */ 633 #define EXMC_BANK0_NORSRAM_REGION1 ((uint32_t)0x00000001U) /*!< bank0 NOR/SRAM region1 */ 634 #define EXMC_BANK0_NORSRAM_REGION2 ((uint32_t)0x00000002U) /*!< bank0 NOR/SRAM region2 */ 635 #define EXMC_BANK0_NORSRAM_REGION3 ((uint32_t)0x00000003U) /*!< bank0 NOR/SRAM region3 */ 636 637 /* EXMC consecutive clock */ 638 #define EXMC_CLOCK_SYN_MODE ((uint32_t)0x00000000U) /*!< EXMC_CLK is generated only during synchronous access */ 639 #define EXMC_CLOCK_UNCONDITIONALLY EXMC_SNCTL_CCK /*!< EXMC_CLK is generated unconditionally */ 640 641 /* EXMC NOR/SRAM write mode */ 642 #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ 643 #define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ 644 645 /* EXMC NWAIT signal configuration */ 646 #define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ 647 #define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ 648 649 /* EXMC NWAIT signal polarity configuration */ 650 #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ 651 #define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ 652 653 /* EXMC NAND/PC card bank definition */ 654 #define EXMC_BANK1_NAND ((uint32_t)0x00000001U) /*!< NAND flash bank1 */ 655 #define EXMC_BANK2_NAND ((uint32_t)0x00000002U) /*!< NAND flash bank2 */ 656 #define EXMC_BANK3_PCCARD ((uint32_t)0x00000003U) /*!< PC card bank3 */ 657 658 /* EXMC SDRAM bank definition */ 659 #define EXMC_SDRAM_DEVICE0 ((uint32_t)0x00000004U) /*!< SDRAM device0 */ 660 #define EXMC_SDRAM_DEVICE1 ((uint32_t)0x00000005U) /*!< SDRAM device1 */ 661 662 /* EXMC SDRAM internal banks */ 663 #define EXMC_SDRAM_2_INTER_BANK ((uint32_t)0x00000000U) /*!< 2 internal banks */ 664 #define EXMC_SDRAM_4_INTER_BANK EXMC_SDCTL_NBK /*!< 4 internal banks */ 665 666 /* SDRAM device0 selection */ 667 #define EXMC_SDRAM_DEVICE0_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device0 */ 668 #define EXMC_SDRAM_DEVICE0_SELECT EXMC_SDCMD_DS0 /*!< select SDRAM device0 */ 669 670 /* SDRAM device1 selection */ 671 #define EXMC_SDRAM_DEVICE1_UNSELECT ((uint32_t)0x00000000U) /*!< unselect SDRAM device1 */ 672 #define EXMC_SDRAM_DEVICE1_SELECT EXMC_SDCMD_DS1 /*!< select SDRAM device1 */ 673 674 /* SDRAM device status */ 675 #define EXMC_SDRAM_DEVICE_NORMAL ((uint32_t)0x00000000U) /*!< normal status */ 676 #define EXMC_SDRAM_DEVICE_SELF_REFRESH ((uint32_t)0x00000001U) /*!< self refresh status */ 677 #define EXMC_SDRAM_DEVICE_POWER_DOWN ((uint32_t)0x00000002U) /*!< power down status */ 678 679 /* sample cycle of read data */ 680 #define EXMC_SDRAM_READSAMPLE_0_EXTRAHCLK ((uint32_t)0x00000000U) /*!< add 0 extra HCLK cycle to the read data sample clock besides the delay chain */ 681 #define EXMC_SDRAM_READSAMPLE_1_EXTRAHCLK EXMC_SDRSCTL_SSCR /*!< add 1 extra HCLK cycle to the read data sample clock besides the delay chain */ 682 683 /* read data sample polarity */ 684 #define EXMC_SQPIPSRAM_SAMPLE_RISING_EDGE ((uint32_t)0x00000000U) /*!< sample data at rising edge */ 685 #define EXMC_SQPIPSRAM_SAMPLE_FALLING_EDGE EXMC_SINIT_POL /*!< sample data at falling edge */ 686 687 /* SQPI SRAM command flag */ 688 #define EXMC_SEND_COMMAND_FLAG_RDID EXMC_SRCMD_RDID /*!< EXMC_SRCMD_RDID flag bit */ 689 #define EXMC_SEND_COMMAND_FLAG_SC EXMC_SWCMD_SC /*!< EXMC_SWCMD_SC flag bit */ 690 691 /* EXMC flag bits */ 692 #define EXMC_NAND_PCCARD_FLAG_RISE EXMC_NPINTEN_INTRS /*!< interrupt rising edge status */ 693 #define EXMC_NAND_PCCARD_FLAG_LEVEL EXMC_NPINTEN_INTHS /*!< interrupt high-level status */ 694 #define EXMC_NAND_PCCARD_FLAG_FALL EXMC_NPINTEN_INTFS /*!< interrupt falling edge status */ 695 #define EXMC_NAND_PCCARD_FLAG_FIFOE EXMC_NPINTEN_FFEPT /*!< FIFO empty flag */ 696 #define EXMC_SDRAM_FLAG_REFRESH EXMC_SDSDAT_REIF /*!< refresh error interrupt flag */ 697 #define EXMC_SDRAM_FLAG_NREADY EXMC_SDSDAT_NRDY /*!< not ready status */ 698 699 /* EXMC interrupt flag bits */ 700 #define EXMC_NAND_PCCARD_INT_FLAG_RISE EXMC_NPINTEN_INTREN /*!< rising edge interrupt and flag */ 701 #define EXMC_NAND_PCCARD_INT_FLAG_LEVEL EXMC_NPINTEN_INTHEN /*!< high-level interrupt and flag */ 702 #define EXMC_NAND_PCCARD_INT_FLAG_FALL EXMC_NPINTEN_INTFEN /*!< falling edge interrupt and flag */ 703 #define EXMC_SDRAM_INT_FLAG_REFRESH EXMC_SDARI_REIE /*!< refresh error interrupt and flag */ 704 705 /* function declarations */ 706 /* initialization functions */ 707 /* NOR/SRAM */ 708 /* deinitialize EXMC NOR/SRAM region */ 709 void exmc_norsram_deinit(uint32_t exmc_norsram_region); 710 /* initialize exmc_norsram_parameter_struct with the default values */ 711 void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 712 /* initialize EXMC NOR/SRAM region */ 713 void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 714 /* enable EXMC NOR/SRAM region */ 715 void exmc_norsram_enable(uint32_t exmc_norsram_region); 716 /* disable EXMC NOR/SRAM region */ 717 void exmc_norsram_disable(uint32_t exmc_norsram_region); 718 /* NAND */ 719 /* deinitialize EXMC NAND bank */ 720 void exmc_nand_deinit(uint32_t exmc_nand_bank); 721 /* initialize exmc_norsram_parameter_struct with the default values */ 722 void exmc_nand_struct_para_init(exmc_nand_parameter_struct* exmc_nand_init_struct); 723 /* initialize EXMC NAND bank */ 724 void exmc_nand_init(exmc_nand_parameter_struct* exmc_nand_init_struct); 725 /* enable EXMC NAND bank */ 726 void exmc_nand_enable(uint32_t exmc_nand_bank); 727 /* disable EXMC NAND bank */ 728 void exmc_nand_disable(uint32_t exmc_nand_bank); 729 /* PC card */ 730 /* deinitialize EXMC PC card bank */ 731 void exmc_pccard_deinit(void); 732 /* initialize exmc_pccard_parameter_struct with the default values */ 733 void exmc_pccard_struct_para_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); 734 /* initialize EXMC PC card bank */ 735 void exmc_pccard_init(exmc_pccard_parameter_struct* exmc_pccard_init_struct); 736 /* enable EXMC PC card bank */ 737 void exmc_pccard_enable(void); 738 /* disable EXMC PC card bank */ 739 void exmc_pccard_disable(void); 740 /* SDRAM */ 741 /* deinitialize EXMC SDRAM device */ 742 void exmc_sdram_deinit(uint32_t exmc_sdram_device); 743 /* initialize exmc_sdram_parameter_struct with the default values */ 744 void exmc_sdram_struct_para_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); 745 /* initialize EXMC SDRAM device */ 746 void exmc_sdram_init(exmc_sdram_parameter_struct* exmc_sdram_init_struct); 747 /* SQPIPSRAM */ 748 /* deinitialize EXMC SQPIPSRAM */ 749 void exmc_sqpipsram_deinit(void); 750 /* initialize exmc_sqpipsram_parameter_struct with the default values */ 751 void exmc_sqpipsram_struct_para_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); 752 /* initialize EXMC SQPIPSRAM */ 753 void exmc_sqpipsram_init(exmc_sqpipsram_parameter_struct* exmc_sqpipsram_init_struct); 754 755 /* function configuration */ 756 /* NOR/SRAM */ 757 /* configure consecutive clock */ 758 void exmc_norsram_consecutive_clock_config(uint32_t clock_mode); 759 /* configure CRAM page size */ 760 void exmc_norsram_page_size_config(uint32_t exmc_norsram_region, uint32_t page_size); 761 /* NAND */ 762 /* enable or disable the EXMC NAND ECC function */ 763 void exmc_nand_ecc_config(uint32_t exmc_nand_bank, ControlStatus newvalue); 764 /* get the EXMC ECC value */ 765 uint32_t exmc_ecc_get(uint32_t exmc_nand_bank); 766 /* SDRAM */ 767 /* enable or disable read sample */ 768 void exmc_sdram_readsample_enable(ControlStatus newvalue); 769 /* configure the delayed sample clock of read data */ 770 void exmc_sdram_readsample_config(uint32_t delay_cell, uint32_t extra_hclk); 771 /* configure the SDRAM memory command */ 772 void exmc_sdram_command_config(exmc_sdram_command_parameter_struct* exmc_sdram_command_init_struct); 773 /* set auto-refresh interval */ 774 void exmc_sdram_refresh_count_set(uint32_t exmc_count); 775 /* set the number of successive auto-refresh command */ 776 void exmc_sdram_autorefresh_number_set(uint32_t exmc_number); 777 /* config the write protection function */ 778 void exmc_sdram_write_protection_config(uint32_t exmc_sdram_device, ControlStatus newvalue); 779 /* get the status of SDRAM device0 or device1 */ 780 uint32_t exmc_sdram_bankstatus_get(uint32_t exmc_sdram_device); 781 /* SQPIPSRAM */ 782 /* set the read command */ 783 void exmc_sqpipsram_read_command_set(uint32_t read_command_mode,uint32_t read_wait_cycle,uint32_t read_command_code); 784 /* set the write command */ 785 void exmc_sqpipsram_write_command_set(uint32_t write_command_mode,uint32_t write_wait_cycle,uint32_t write_command_code); 786 /* send SPI read ID command */ 787 void exmc_sqpipsram_read_id_command_send(void); 788 /* send SPI special command which does not have address and data phase */ 789 void exmc_sqpipsram_write_cmd_send(void); 790 /* get the EXMC SPI ID low data */ 791 uint32_t exmc_sqpipsram_low_id_get(void); 792 /* get the EXMC SPI ID high data */ 793 uint32_t exmc_sqpipsram_high_id_get(void); 794 /* get the bit value of EXMC send write command bit or read ID command */ 795 FlagStatus exmc_sqpipsram_send_command_state_get(uint32_t send_command_flag); 796 797 /* interrupt & flag functions */ 798 /* enable EXMC interrupt */ 799 void exmc_interrupt_enable(uint32_t exmc_bank,uint32_t interrupt); 800 /* disable EXMC interrupt */ 801 void exmc_interrupt_disable(uint32_t exmc_bank,uint32_t interrupt); 802 /* get EXMC flag status */ 803 FlagStatus exmc_flag_get(uint32_t exmc_bank,uint32_t flag); 804 /* clear EXMC flag status */ 805 void exmc_flag_clear(uint32_t exmc_bank,uint32_t flag); 806 /* get EXMC interrupt flag */ 807 FlagStatus exmc_interrupt_flag_get(uint32_t exmc_bank,uint32_t interrupt); 808 /* clear EXMC interrupt flag */ 809 void exmc_interrupt_flag_clear(uint32_t exmc_bank,uint32_t interrupt); 810 811 #endif /* GD32F4XX_EXMC_H */ 812
