1 /*! 2 \file gd32f4xx_enet.h 3 \brief definitions for the ENET 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F4XX_ENET_H 39 #define GD32F4XX_ENET_H 40 41 #include "gd32f4xx.h" 42 #include <stdlib.h> 43 44 #define IF_USE_EXTERNPHY_LIB 0 45 #if (1 == IF_USE_EXTERNPHY_LIB) 46 #include "phy.h" 47 #endif 48 49 #ifndef ENET_RXBUF_NUM 50 #define ENET_RXBUF_NUM 5U /*!< ethernet Rx DMA descriptor number */ 51 #endif 52 53 #ifndef ENET_TXBUF_NUM 54 #define ENET_TXBUF_NUM 5U /*!< ethernet Tx DMA descriptor number */ 55 #endif 56 57 #ifndef ENET_RXBUF_SIZE 58 #define ENET_RXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet receive buffer size */ 59 #endif 60 61 #ifndef ENET_TXBUF_SIZE 62 #define ENET_TXBUF_SIZE ENET_MAX_FRAME_SIZE /*!< ethernet transmit buffer size */ 63 #endif 64 65 //#define SELECT_DESCRIPTORS_ENHANCED_MODE 66 67 //#define USE_DELAY 68 69 #ifndef _PHY_H_ 70 #define DP83848 0 71 #define LAN8700 1 72 #define PHY_TYPE DP83848 73 74 #define PHY_ADDRESS ((uint16_t)1U) /*!< phy address determined by the hardware */ 75 76 /* PHY read write timeouts */ 77 #define PHY_READ_TO ((uint32_t)0x0004FFFFU) /*!< PHY read timeout */ 78 #define PHY_WRITE_TO ((uint32_t)0x0004FFFFU) /*!< PHY write timeout */ 79 80 /* PHY delay */ 81 #define PHY_RESETDELAY ((uint32_t)0x008FFFFFU) /*!< PHY reset delay */ 82 #define PHY_CONFIGDELAY ((uint32_t)0x00FFFFFFU) /*!< PHY configure delay */ 83 84 /* PHY register address */ 85 #define PHY_REG_BCR 0U /*!< tranceiver basic control register */ 86 #define PHY_REG_BSR 1U /*!< tranceiver basic status register */ 87 88 /* PHY basic control register */ 89 #define PHY_RESET ((uint16_t)0x8000) /*!< PHY reset */ 90 #define PHY_LOOPBACK ((uint16_t)0x4000) /*!< enable phy loop-back mode */ 91 #define PHY_FULLDUPLEX_100M ((uint16_t)0x2100) /*!< configure speed to 100 Mbit/s and the full-duplex mode */ 92 #define PHY_HALFDUPLEX_100M ((uint16_t)0x2000) /*!< configure speed to 100 Mbit/s and the half-duplex mode */ 93 #define PHY_FULLDUPLEX_10M ((uint16_t)0x0100) /*!< configure speed to 10 Mbit/s and the full-duplex mode */ 94 #define PHY_HALFDUPLEX_10M ((uint16_t)0x0000) /*!< configure speed to 10 Mbit/s and the half-duplex mode */ 95 #define PHY_AUTONEGOTIATION ((uint16_t)0x1000) /*!< enable auto-negotiation function */ 96 #define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200) /*!< restart auto-negotiation function */ 97 #define PHY_POWERDOWN ((uint16_t)0x0800) /*!< enable the power down mode */ 98 #define PHY_ISOLATE ((uint16_t)0x0400) /*!< isolate PHY from MII */ 99 100 /* PHY basic status register */ 101 #define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020) /*!< auto-negotioation process completed */ 102 #define PHY_LINKED_STATUS ((uint16_t)0x0004) /*!< valid link established */ 103 #define PHY_JABBER_DETECTION ((uint16_t)0x0002) /*!< jabber condition detected */ 104 105 #if(PHY_TYPE == LAN8700) 106 #define PHY_SR 31U /*!< tranceiver status register */ 107 #define PHY_SPEED_STATUS ((uint16_t)0x0004) /*!< configured information of speed: 10Mbit/s */ 108 #define PHY_DUPLEX_STATUS ((uint16_t)0x0010) /*!< configured information of duplex: full-duplex */ 109 #elif(PHY_TYPE == DP83848) 110 #define PHY_SR 16U /*!< tranceiver status register */ 111 #define PHY_SPEED_STATUS ((uint16_t)0x0002) /*!< configured information of speed: 10Mbit/s */ 112 #define PHY_DUPLEX_STATUS ((uint16_t)0x0004) /*!< configured information of duplex: full-duplex */ 113 #endif /* PHY_TYPE */ 114 115 #endif /* _PHY_H_ */ 116 117 118 /* ENET definitions */ 119 #define ENET ENET_BASE 120 121 /* registers definitions */ 122 #define ENET_MAC_CFG REG32((ENET) + 0x0000U) /*!< ethernet MAC configuration register */ 123 #define ENET_MAC_FRMF REG32((ENET) + 0x0004U) /*!< ethernet MAC frame filter register */ 124 #define ENET_MAC_HLH REG32((ENET) + 0x0008U) /*!< ethernet MAC hash list high register */ 125 #define ENET_MAC_HLL REG32((ENET) + 0x000CU) /*!< ethernet MAC hash list low register */ 126 #define ENET_MAC_PHY_CTL REG32((ENET) + 0x0010U) /*!< ethernet MAC PHY control register */ 127 #define ENET_MAC_PHY_DATA REG32((ENET) + 0x0014U) /*!< ethernet MAC MII data register */ 128 #define ENET_MAC_FCTL REG32((ENET) + 0x0018U) /*!< ethernet MAC flow control register */ 129 #define ENET_MAC_VLT REG32((ENET) + 0x001CU) /*!< ethernet MAC VLAN tag register */ 130 #define ENET_MAC_RWFF REG32((ENET) + 0x0028U) /*!< ethernet MAC remote wakeup frame filter register */ 131 #define ENET_MAC_WUM REG32((ENET) + 0x002CU) /*!< ethernet MAC wakeup management register */ 132 #define ENET_MAC_DBG REG32((ENET) + 0x0034U) /*!< ethernet MAC debug register */ 133 #define ENET_MAC_INTF REG32((ENET) + 0x0038U) /*!< ethernet MAC interrupt flag register */ 134 #define ENET_MAC_INTMSK REG32((ENET) + 0x003CU) /*!< ethernet MAC interrupt mask register */ 135 #define ENET_MAC_ADDR0H REG32((ENET) + 0x0040U) /*!< ethernet MAC address 0 high register */ 136 #define ENET_MAC_ADDR0L REG32((ENET) + 0x0044U) /*!< ethernet MAC address 0 low register */ 137 #define ENET_MAC_ADDR1H REG32((ENET) + 0x0048U) /*!< ethernet MAC address 1 high register */ 138 #define ENET_MAC_ADDR1L REG32((ENET) + 0x004CU) /*!< ethernet MAC address 1 low register */ 139 #define ENET_MAC_ADDT2H REG32((ENET) + 0x0050U) /*!< ethernet MAC address 2 high register */ 140 #define ENET_MAC_ADDR2L REG32((ENET) + 0x0054U) /*!< ethernet MAC address 2 low register */ 141 #define ENET_MAC_ADDR3H REG32((ENET) + 0x0058U) /*!< ethernet MAC address 3 high register */ 142 #define ENET_MAC_ADDR3L REG32((ENET) + 0x005CU) /*!< ethernet MAC address 3 low register */ 143 #define ENET_MAC_FCTH REG32((ENET) + 0x1080U) /*!< ethernet MAC flow control threshold register */ 144 145 #define ENET_MSC_CTL REG32((ENET) + 0x0100U) /*!< ethernet MSC control register */ 146 #define ENET_MSC_RINTF REG32((ENET) + 0x0104U) /*!< ethernet MSC receive interrupt flag register */ 147 #define ENET_MSC_TINTF REG32((ENET) + 0x0108U) /*!< ethernet MSC transmit interrupt flag register */ 148 #define ENET_MSC_RINTMSK REG32((ENET) + 0x010CU) /*!< ethernet MSC receive interrupt mask register */ 149 #define ENET_MSC_TINTMSK REG32((ENET) + 0x0110U) /*!< ethernet MSC transmit interrupt mask register */ 150 #define ENET_MSC_SCCNT REG32((ENET) + 0x014CU) /*!< ethernet MSC transmitted good frames after a single collision counter register */ 151 #define ENET_MSC_MSCCNT REG32((ENET) + 0x0150U) /*!< ethernet MSC transmitted good frames after more than a single collision counter register */ 152 #define ENET_MSC_TGFCNT REG32((ENET) + 0x0168U) /*!< ethernet MSC transmitted good frames counter register */ 153 #define ENET_MSC_RFCECNT REG32((ENET) + 0x0194U) /*!< ethernet MSC received frames with CRC error counter register */ 154 #define ENET_MSC_RFAECNT REG32((ENET) + 0x0198U) /*!< ethernet MSC received frames with alignment error counter register */ 155 #define ENET_MSC_RGUFCNT REG32((ENET) + 0x01C4U) /*!< ethernet MSC received good unicast frames counter register */ 156 157 #define ENET_PTP_TSCTL REG32((ENET) + 0x0700U) /*!< ethernet PTP time stamp control register */ 158 #define ENET_PTP_SSINC REG32((ENET) + 0x0704U) /*!< ethernet PTP subsecond increment register */ 159 #define ENET_PTP_TSH REG32((ENET) + 0x0708U) /*!< ethernet PTP time stamp high register */ 160 #define ENET_PTP_TSL REG32((ENET) + 0x070CU) /*!< ethernet PTP time stamp low register */ 161 #define ENET_PTP_TSUH REG32((ENET) + 0x0710U) /*!< ethernet PTP time stamp update high register */ 162 #define ENET_PTP_TSUL REG32((ENET) + 0x0714U) /*!< ethernet PTP time stamp update low register */ 163 #define ENET_PTP_TSADDEND REG32((ENET) + 0x0718U) /*!< ethernet PTP time stamp addend register */ 164 #define ENET_PTP_ETH REG32((ENET) + 0x071CU) /*!< ethernet PTP expected time high register */ 165 #define ENET_PTP_ETL REG32((ENET) + 0x0720U) /*!< ethernet PTP expected time low register */ 166 #define ENET_PTP_TSF REG32((ENET) + 0x0728U) /*!< ethernet PTP time stamp flag register */ 167 #define ENET_PTP_PPSCTL REG32((ENET) + 0x072CU) /*!< ethernet PTP PPS control register */ 168 169 #define ENET_DMA_BCTL REG32((ENET) + 0x1000U) /*!< ethernet DMA bus control register */ 170 #define ENET_DMA_TPEN REG32((ENET) + 0x1004U) /*!< ethernet DMA transmit poll enable register */ 171 #define ENET_DMA_RPEN REG32((ENET) + 0x1008U) /*!< ethernet DMA receive poll enable register */ 172 #define ENET_DMA_RDTADDR REG32((ENET) + 0x100CU) /*!< ethernet DMA receive descriptor table address register */ 173 #define ENET_DMA_TDTADDR REG32((ENET) + 0x1010U) /*!< ethernet DMA transmit descriptor table address register */ 174 #define ENET_DMA_STAT REG32((ENET) + 0x1014U) /*!< ethernet DMA status register */ 175 #define ENET_DMA_CTL REG32((ENET) + 0x1018U) /*!< ethernet DMA control register */ 176 #define ENET_DMA_INTEN REG32((ENET) + 0x101CU) /*!< ethernet DMA interrupt enable register */ 177 #define ENET_DMA_MFBOCNT REG32((ENET) + 0x1020U) /*!< ethernet DMA missed frame and buffer overflow counter register */ 178 #define ENET_DMA_RSWDC REG32((ENET) + 0x1024U) /*!< ethernet DMA receive state watchdog counter register */ 179 #define ENET_DMA_CTDADDR REG32((ENET) + 0x1048U) /*!< ethernet DMA current transmit descriptor address register */ 180 #define ENET_DMA_CRDADDR REG32((ENET) + 0x104CU) /*!< ethernet DMA current receive descriptor address register */ 181 #define ENET_DMA_CTBADDR REG32((ENET) + 0x1050U) /*!< ethernet DMA current transmit buffer address register */ 182 #define ENET_DMA_CRBADDR REG32((ENET) + 0x1054U) /*!< ethernet DMA current receive buffer address register */ 183 184 /* bits definitions */ 185 /* ENET_MAC_CFG */ 186 #define ENET_MAC_CFG_REN BIT(2) /*!< receiver enable */ 187 #define ENET_MAC_CFG_TEN BIT(3) /*!< transmitter enable */ 188 #define ENET_MAC_CFG_DFC BIT(4) /*!< defferal check */ 189 #define ENET_MAC_CFG_BOL BITS(5,6) /*!< back-off limit */ 190 #define ENET_MAC_CFG_APCD BIT(7) /*!< automatic pad/CRC drop */ 191 #define ENET_MAC_CFG_RTD BIT(9) /*!< retry disable */ 192 #define ENET_MAC_CFG_IPFCO BIT(10) /*!< IP frame checksum offload */ 193 #define ENET_MAC_CFG_DPM BIT(11) /*!< duplex mode */ 194 #define ENET_MAC_CFG_LBM BIT(12) /*!< loopback mode */ 195 #define ENET_MAC_CFG_ROD BIT(13) /*!< receive own disable */ 196 #define ENET_MAC_CFG_SPD BIT(14) /*!< fast eneternet speed */ 197 #define ENET_MAC_CFG_CSD BIT(16) /*!< carrier sense disable */ 198 #define ENET_MAC_CFG_IGBS BITS(17,19) /*!< inter-frame gap bit selection */ 199 #define ENET_MAC_CFG_JBD BIT(22) /*!< jabber disable */ 200 #define ENET_MAC_CFG_WDD BIT(23) /*!< watchdog disable */ 201 #define ENET_MAC_CFG_TFCD BIT(25) /*!< type frame CRC dropping */ 202 203 /* ENET_MAC_FRMF */ 204 #define ENET_MAC_FRMF_PM BIT(0) /*!< promiscuous mode */ 205 #define ENET_MAC_FRMF_HUF BIT(1) /*!< hash unicast filter */ 206 #define ENET_MAC_FRMF_HMF BIT(2) /*!< hash multicast filter */ 207 #define ENET_MAC_FRMF_DAIFLT BIT(3) /*!< destination address inverse filtering enable */ 208 #define ENET_MAC_FRMF_MFD BIT(4) /*!< multicast filter disable */ 209 #define ENET_MAC_FRMF_BFRMD BIT(5) /*!< broadcast frame disable */ 210 #define ENET_MAC_FRMF_PCFRM BITS(6,7) /*!< pass control frames */ 211 #define ENET_MAC_FRMF_SAIFLT BIT(8) /*!< source address inverse filtering */ 212 #define ENET_MAC_FRMF_SAFLT BIT(9) /*!< source address filter */ 213 #define ENET_MAC_FRMF_HPFLT BIT(10) /*!< hash or perfect filter */ 214 #define ENET_MAC_FRMF_FAR BIT(31) /*!< frames all receive */ 215 216 /* ENET_MAC_HLH */ 217 #define ENET_MAC_HLH_HLH BITS(0,31) /*!< hash list high */ 218 219 /* ENET_MAC_HLL */ 220 #define ENET_MAC_HLL_HLL BITS(0,31) /*!< hash list low */ 221 222 /* ENET_MAC_PHY_CTL */ 223 #define ENET_MAC_PHY_CTL_PB BIT(0) /*!< PHY busy */ 224 #define ENET_MAC_PHY_CTL_PW BIT(1) /*!< PHY write */ 225 #define ENET_MAC_PHY_CTL_CLR BITS(2,4) /*!< clock range */ 226 #define ENET_MAC_PHY_CTL_PR BITS(6,10) /*!< PHY register */ 227 #define ENET_MAC_PHY_CTL_PA BITS(11,15) /*!< PHY address */ 228 229 /* ENET_MAC_PHY_DATA */ 230 #define ENET_MAC_PHY_DATA_PD BITS(0,15) /*!< PHY data */ 231 232 /* ENET_MAC_FCTL */ 233 #define ENET_MAC_FCTL_FLCBBKPA BIT(0) /*!< flow control busy(in full duplex mode)/backpressure activate(in half duplex mode) */ 234 #define ENET_MAC_FCTL_TFCEN BIT(1) /*!< transmit flow control enable */ 235 #define ENET_MAC_FCTL_RFCEN BIT(2) /*!< receive flow control enable */ 236 #define ENET_MAC_FCTL_UPFDT BIT(3) /*!< unicast pause frame detect */ 237 #define ENET_MAC_FCTL_PLTS BITS(4,5) /*!< pause low threshold */ 238 #define ENET_MAC_FCTL_DZQP BIT(7) /*!< disable zero-quanta pause */ 239 #define ENET_MAC_FCTL_PTM BITS(16,31) /*!< pause time */ 240 241 /* ENET_MAC_VLT */ 242 #define ENET_MAC_VLT_VLTI BITS(0,15) /*!< VLAN tag identifier(for receive frames) */ 243 #define ENET_MAC_VLT_VLTC BIT(16) /*!< 12-bit VLAN tag comparison */ 244 245 /* ENET_MAC_RWFF */ 246 #define ENET_MAC_RWFF_DATA BITS(0,31) /*!< wakeup frame filter register data */ 247 248 /* ENET_MAC_WUM */ 249 #define ENET_MAC_WUM_PWD BIT(0) /*!< power down */ 250 #define ENET_MAC_WUM_MPEN BIT(1) /*!< magic packet enable */ 251 #define ENET_MAC_WUM_WFEN BIT(2) /*!< wakeup frame enable */ 252 #define ENET_MAC_WUM_MPKR BIT(5) /*!< magic packet received */ 253 #define ENET_MAC_WUM_WUFR BIT(6) /*!< wakeup frame received */ 254 #define ENET_MAC_WUM_GU BIT(9) /*!< global unicast */ 255 #define ENET_MAC_WUM_WUFFRPR BIT(31) /*!< wakeup frame filter register pointer reset */ 256 257 /* ENET_MAC_DBG */ 258 #define ENET_MAC_DBG_MRNI BIT(0) /*!< MAC receive state not idle */ 259 #define ENET_MAC_DBG_RXAFS BITS(1,2) /*!< Rx asynchronous FIFO status */ 260 #define ENET_MAC_DBG_RXFW BIT(4) /*!< RxFIFO is writing */ 261 #define ENET_MAC_DBG_RXFRS BITS(5,6) /*!< RxFIFO read operation status */ 262 #define ENET_MAC_DBG_RXFS BITS(8,9) /*!< RxFIFO state */ 263 #define ENET_MAC_DBG_MTNI BIT(16) /*!< MAC transmit state not idle */ 264 #define ENET_MAC_DBG_SOMT BITS(17,18) /*!< status of mac transmitter */ 265 #define ENET_MAC_DBG_PCS BIT(19) /*!< pause condition status */ 266 #define ENET_MAC_DBG_TXFRS BITS(20,21) /*!< TxFIFO read operation status */ 267 #define ENET_MAC_DBG_TXFW BIT(22) /*!< TxFIFO is writing */ 268 #define ENET_MAC_DBG_TXFNE BIT(24) /*!< TxFIFO not empty flag */ 269 #define ENET_MAC_DBG_TXFF BIT(25) /*!< TxFIFO full flag */ 270 271 /* ENET_MAC_INTF */ 272 #define ENET_MAC_INTF_WUM BIT(3) /*!< WUM status */ 273 #define ENET_MAC_INTF_MSC BIT(4) /*!< MSC status */ 274 #define ENET_MAC_INTF_MSCR BIT(5) /*!< MSC receive status */ 275 #define ENET_MAC_INTF_MSCT BIT(6) /*!< MSC transmit status */ 276 #define ENET_MAC_INTF_TMST BIT(9) /*!< timestamp trigger status */ 277 278 /* ENET_MAC_INTMSK */ 279 #define ENET_MAC_INTMSK_WUMIM BIT(3) /*!< WUM interrupt mask */ 280 #define ENET_MAC_INTMSK_TMSTIM BIT(9) /*!< timestamp trigger interrupt mask */ 281 282 /* ENET_MAC_ADDR0H */ 283 #define ENET_MAC_ADDR0H_ADDR0H BITS(0,15) /*!< MAC address0 high */ 284 #define ENET_MAC_ADDR0H_MO BIT(31) /*!< always read 1 and must be kept */ 285 286 /* ENET_MAC_ADDR0L */ 287 #define ENET_MAC_ADDR0L_ADDR0L BITS(0,31) /*!< MAC address0 low */ 288 289 /* ENET_MAC_ADDR1H */ 290 #define ENET_MAC_ADDR1H_ADDR1H BITS(0,15) /*!< MAC address1 high */ 291 #define ENET_MAC_ADDR1H_MB BITS(24,29) /*!< mask byte */ 292 #define ENET_MAC_ADDR1H_SAF BIT(30) /*!< source address filter */ 293 #define ENET_MAC_ADDR1H_AFE BIT(31) /*!< address filter enable */ 294 295 /* ENET_MAC_ADDR1L */ 296 #define ENET_MAC_ADDR1L_ADDR1L BITS(0,31) /*!< MAC address1 low */ 297 298 /* ENET_MAC_ADDR2H */ 299 #define ENET_MAC_ADDR2H_ADDR2H BITS(0,15) /*!< MAC address2 high */ 300 #define ENET_MAC_ADDR2H_MB BITS(24,29) /*!< mask byte */ 301 #define ENET_MAC_ADDR2H_SAF BIT(30) /*!< source address filter */ 302 #define ENET_MAC_ADDR2H_AFE BIT(31) /*!< address filter enable */ 303 304 /* ENET_MAC_ADDR2L */ 305 #define ENET_MAC_ADDR2L_ADDR2L BITS(0,31) /*!< MAC address2 low */ 306 307 /* ENET_MAC_ADDR3H */ 308 #define ENET_MAC_ADDR3H_ADDR3H BITS(0,15) /*!< MAC address3 high */ 309 #define ENET_MAC_ADDR3H_MB BITS(24,29) /*!< mask byte */ 310 #define ENET_MAC_ADDR3H_SAF BIT(30) /*!< source address filter */ 311 #define ENET_MAC_ADDR3H_AFE BIT(31) /*!< address filter enable */ 312 313 /* ENET_MAC_ADDR3L */ 314 #define ENET_MAC_ADDR3L_ADDR3L BITS(0,31) /*!< MAC address3 low */ 315 316 /* ENET_MAC_FCTH */ 317 #define ENET_MAC_FCTH_RFA BITS(0,2) /*!< threshold of active flow control */ 318 #define ENET_MAC_FCTH_RFD BITS(4,6) /*!< threshold of deactive flow control */ 319 320 /* ENET_MSC_CTL */ 321 #define ENET_MSC_CTL_CTR BIT(0) /*!< counter reset */ 322 #define ENET_MSC_CTL_CTSR BIT(1) /*!< counter stop rollover */ 323 #define ENET_MSC_CTL_RTOR BIT(2) /*!< reset on read */ 324 #define ENET_MSC_CTL_MCFZ BIT(3) /*!< MSC counter freeze */ 325 #define ENET_MSC_CTL_PMC BIT(4) /*!< preset MSC counter */ 326 #define ENET_MSC_CTL_AFHPM BIT(5) /*!< almost full or half preset mode */ 327 328 /* ENET_MSC_RINTF */ 329 #define ENET_MSC_RINTF_RFCE BIT(5) /*!< received frames CRC error */ 330 #define ENET_MSC_RINTF_RFAE BIT(6) /*!< received frames alignment error */ 331 #define ENET_MSC_RINTF_RGUF BIT(17) /*!< receive good unicast frames */ 332 333 /* ENET_MSC_TINTF */ 334 #define ENET_MSC_TINTF_TGFSC BIT(14) /*!< transmitted good frames single collision */ 335 #define ENET_MSC_TINTF_TGFMSC BIT(15) /*!< transmitted good frames more single collision */ 336 #define ENET_MSC_TINTF_TGF BIT(21) /*!< transmitted good frames */ 337 338 /* ENET_MSC_RINTMSK */ 339 #define ENET_MSC_RINTMSK_RFCEIM BIT(5) /*!< received frame CRC error interrupt mask */ 340 #define ENET_MSC_RINTMSK_RFAEIM BIT(6) /*!< received frames alignment error interrupt mask */ 341 #define ENET_MSC_RINTMSK_RGUFIM BIT(17) /*!< received good unicast frames interrupt mask */ 342 343 /* ENET_MSC_TINTMSK */ 344 #define ENET_MSC_TINTMSK_TGFSCIM BIT(14) /*!< transmitted good frames single collision interrupt mask */ 345 #define ENET_MSC_TINTMSK_TGFMSCIM BIT(15) /*!< transmitted good frames more single collision interrupt mask */ 346 #define ENET_MSC_TINTMSK_TGFIM BIT(21) /*!< transmitted good frames interrupt mask */ 347 348 /* ENET_MSC_SCCNT */ 349 #define ENET_MSC_SCCNT_SCC BITS(0,31) /*!< transmitted good frames single collision counter */ 350 351 /* ENET_MSC_MSCCNT */ 352 #define ENET_MSC_MSCCNT_MSCC BITS(0,31) /*!< transmitted good frames more one single collision counter */ 353 354 /* ENET_MSC_TGFCNT */ 355 #define ENET_MSC_TGFCNT_TGF BITS(0,31) /*!< transmitted good frames counter */ 356 357 /* ENET_MSC_RFCECNT */ 358 #define ENET_MSC_RFCECNT_RFCER BITS(0,31) /*!< received frames with CRC error counter */ 359 360 /* ENET_MSC_RFAECNT */ 361 #define ENET_MSC_RFAECNT_RFAER BITS(0,31) /*!< received frames alignment error counter */ 362 363 /* ENET_MSC_RGUFCNT */ 364 #define ENET_MSC_RGUFCNT_RGUF BITS(0,31) /*!< received good unicast frames counter */ 365 366 /* ENET_PTP_TSCTL */ 367 #define PTP_TSCTL_CKNT(regval) (BITS(16,17) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_PTP_TSCTL_CKNT bit field */ 368 369 #define ENET_PTP_TSCTL_TMSEN BIT(0) /*!< timestamp enable */ 370 #define ENET_PTP_TSCTL_TMSFCU BIT(1) /*!< timestamp fine or coarse update */ 371 #define ENET_PTP_TSCTL_TMSSTI BIT(2) /*!< timestamp system time initialize */ 372 #define ENET_PTP_TSCTL_TMSSTU BIT(3) /*!< timestamp system time update */ 373 #define ENET_PTP_TSCTL_TMSITEN BIT(4) /*!< timestamp interrupt trigger enable */ 374 #define ENET_PTP_TSCTL_TMSARU BIT(5) /*!< timestamp addend register update */ 375 #define ENET_PTP_TSCTL_ARFSEN BIT(8) /*!< all received frames snapshot enable */ 376 #define ENET_PTP_TSCTL_SCROM BIT(9) /*!< subsecond counter rollover mode */ 377 #define ENET_PTP_TSCTL_PFSV BIT(10) /*!< PTP frame snooping version */ 378 #define ENET_PTP_TSCTL_ESEN BIT(11) /*!< received Ethernet snapshot enable */ 379 #define ENET_PTP_TSCTL_IP6SEN BIT(12) /*!< received IPv6 snapshot enable */ 380 #define ENET_PTP_TSCTL_IP4SEN BIT(13) /*!< received IPv4 snapshot enable */ 381 #define ENET_PTP_TSCTL_ETMSEN BIT(14) /*!< received event type message snapshot enable */ 382 #define ENET_PTP_TSCTL_MNMSEN BIT(15) /*!< received master node message snapshot enable */ 383 #define ENET_PTP_TSCTL_CKNT BITS(16,17) /*!< clock node type for time stamp */ 384 #define ENET_PTP_TSCTL_MAFEN BIT(18) /*!< MAC address filter enable for PTP frame */ 385 386 /* ENET_PTP_SSINC */ 387 #define ENET_PTP_SSINC_STMSSI BITS(0,7) /*!< system time subsecond increment */ 388 389 /* ENET_PTP_TSH */ 390 #define ENET_PTP_TSH_STMS BITS(0,31) /*!< system time second */ 391 392 /* ENET_PTP_TSL */ 393 #define ENET_PTP_TSL_STMSS BITS(0,30) /*!< system time subseconds */ 394 #define ENET_PTP_TSL_STS BIT(31) /*!< system time sign */ 395 396 /* ENET_PTP_TSUH */ 397 #define ENET_PTP_TSUH_TMSUS BITS(0,31) /*!< timestamp update seconds */ 398 399 /* ENET_PTP_TSUL */ 400 #define ENET_PTP_TSUL_TMSUSS BITS(0,30) /*!< timestamp update subseconds */ 401 #define ENET_PTP_TSUL_TMSUPNS BIT(31) /*!< timestamp update positive or negative sign */ 402 403 /* ENET_PTP_TSADDAND */ 404 #define ENET_PTP_TSADDAND_TMSA BITS(0,31) /*!< timestamp addend */ 405 406 /* ENET_PTP_ETH */ 407 #define ENET_PTP_ETH_ETSH BITS(0,31) /*!< expected time high */ 408 409 /* ENET_PTP_ETL */ 410 #define ENET_PTP_ETL_ETSL BITS(0,31) /*!< expected time low */ 411 412 /* ENET_PTP_TSF */ 413 #define ENET_PTP_TSF_TSSCO BIT(0) /*!< timestamp second counter overflow */ 414 #define ENET_PTP_TSF_TTM BIT(1) /*!< target time match */ 415 416 /* ENET_PTP_PPSCTL */ 417 #define ENET_PTP_PPSCTL_PPSOFC BITS(0,3) /*!< PPS output frequency configure */ 418 419 /* ENET_DMA_BCTL */ 420 #define ENET_DMA_BCTL_SWR BIT(0) /*!< software reset */ 421 #define ENET_DMA_BCTL_DAB BIT(1) /*!< DMA arbitration */ 422 #define ENET_DMA_BCTL_DPSL BITS(2,6) /*!< descriptor skip length */ 423 #define ENET_DMA_BCTL_DFM BIT(7) /*!< descriptor format mode */ 424 #define ENET_DMA_BCTL_PGBL BITS(8,13) /*!< programmable burst length */ 425 #define ENET_DMA_BCTL_RTPR BITS(14,15) /*!< RxDMA and TxDMA transfer priority ratio */ 426 #define ENET_DMA_BCTL_FB BIT(16) /*!< fixed Burst */ 427 #define ENET_DMA_BCTL_RXDP BITS(17,22) /*!< RxDMA PGBL */ 428 #define ENET_DMA_BCTL_UIP BIT(23) /*!< use independent PGBL */ 429 #define ENET_DMA_BCTL_FPBL BIT(24) /*!< four times PGBL mode */ 430 #define ENET_DMA_BCTL_AA BIT(25) /*!< address-aligned */ 431 #define ENET_DMA_BCTL_MB BIT(26) /*!< mixed burst */ 432 433 /* ENET_DMA_TPEN */ 434 #define ENET_DMA_TPEN_TPE BITS(0,31) /*!< transmit poll enable */ 435 436 /* ENET_DMA_RPEN */ 437 #define ENET_DMA_RPEN_RPE BITS(0,31) /*!< receive poll enable */ 438 439 /* ENET_DMA_RDTADDR */ 440 #define ENET_DMA_RDTADDR_SRT BITS(0,31) /*!< start address of receive table */ 441 442 /* ENET_DMA_TDTADDR */ 443 #define ENET_DMA_TDTADDR_STT BITS(0,31) /*!< start address of transmit table */ 444 445 /* ENET_DMA_STAT */ 446 #define ENET_DMA_STAT_TS BIT(0) /*!< transmit status */ 447 #define ENET_DMA_STAT_TPS BIT(1) /*!< transmit process stopped status */ 448 #define ENET_DMA_STAT_TBU BIT(2) /*!< transmit buffer unavailable status */ 449 #define ENET_DMA_STAT_TJT BIT(3) /*!< transmit jabber timeout status */ 450 #define ENET_DMA_STAT_RO BIT(4) /*!< receive overflow status */ 451 #define ENET_DMA_STAT_TU BIT(5) /*!< transmit underflow status */ 452 #define ENET_DMA_STAT_RS BIT(6) /*!< receive status */ 453 #define ENET_DMA_STAT_RBU BIT(7) /*!< receive buffer unavailable status */ 454 #define ENET_DMA_STAT_RPS BIT(8) /*!< receive process stopped status */ 455 #define ENET_DMA_STAT_RWT BIT(9) /*!< receive watchdog timeout status */ 456 #define ENET_DMA_STAT_ET BIT(10) /*!< early transmit status */ 457 #define ENET_DMA_STAT_FBE BIT(13) /*!< fatal bus error status */ 458 #define ENET_DMA_STAT_ER BIT(14) /*!< early receive status */ 459 #define ENET_DMA_STAT_AI BIT(15) /*!< abnormal interrupt summary */ 460 #define ENET_DMA_STAT_NI BIT(16) /*!< normal interrupt summary */ 461 #define ENET_DMA_STAT_RP BITS(17,19) /*!< receive process state */ 462 #define ENET_DMA_STAT_TP BITS(20,22) /*!< transmit process state */ 463 #define ENET_DMA_STAT_EB BITS(23,25) /*!< error bits status */ 464 #define ENET_DMA_STAT_MSC BIT(27) /*!< MSC status */ 465 #define ENET_DMA_STAT_WUM BIT(28) /*!< WUM status */ 466 #define ENET_DMA_STAT_TST BIT(29) /*!< timestamp trigger status */ 467 468 /* ENET_DMA_CTL */ 469 #define ENET_DMA_CTL_SRE BIT(1) /*!< start/stop receive enable */ 470 #define ENET_DMA_CTL_OSF BIT(2) /*!< operate on second frame */ 471 #define ENET_DMA_CTL_RTHC BITS(3,4) /*!< receive threshold control */ 472 #define ENET_DMA_CTL_FUF BIT(6) /*!< forward undersized good frames */ 473 #define ENET_DMA_CTL_FERF BIT(7) /*!< forward error frames */ 474 #define ENET_DMA_CTL_STE BIT(13) /*!< start/stop transmission enable */ 475 #define ENET_DMA_CTL_TTHC BITS(14,16) /*!< transmit threshold control */ 476 #define ENET_DMA_CTL_FTF BIT(20) /*!< flush transmit FIFO */ 477 #define ENET_DMA_CTL_TSFD BIT(21) /*!< transmit store-and-forward */ 478 #define ENET_DMA_CTL_DAFRF BIT(24) /*!< disable flushing of received frames */ 479 #define ENET_DMA_CTL_RSFD BIT(25) /*!< receive store-and-forward */ 480 #define ENET_DMA_CTL_DTCERFD BIT(26) /*!< dropping of TCP/IP checksum error frames disable */ 481 482 /* ENET_DMA_INTEN */ 483 #define ENET_DMA_INTEN_TIE BIT(0) /*!< transmit interrupt enable */ 484 #define ENET_DMA_INTEN_TPSIE BIT(1) /*!< transmit process stopped interrupt enable */ 485 #define ENET_DMA_INTEN_TBUIE BIT(2) /*!< transmit buffer unavailable interrupt enable */ 486 #define ENET_DMA_INTEN_TJTIE BIT(3) /*!< transmit jabber timeout interrupt enable */ 487 #define ENET_DMA_INTEN_ROIE BIT(4) /*!< receive overflow interrupt enable */ 488 #define ENET_DMA_INTEN_TUIE BIT(5) /*!< transmit underflow interrupt enable */ 489 #define ENET_DMA_INTEN_RIE BIT(6) /*!< receive interrupt enable */ 490 #define ENET_DMA_INTEN_RBUIE BIT(7) /*!< receive buffer unavailable interrupt enable */ 491 #define ENET_DMA_INTEN_RPSIE BIT(8) /*!< receive process stopped interrupt enable */ 492 #define ENET_DMA_INTEN_RWTIE BIT(9) /*!< receive watchdog timeout interrupt enable */ 493 #define ENET_DMA_INTEN_ETIE BIT(10) /*!< early transmit interrupt enable */ 494 #define ENET_DMA_INTEN_FBEIE BIT(13) /*!< fatal bus error interrupt enable */ 495 #define ENET_DMA_INTEN_ERIE BIT(14) /*!< early receive interrupt enable */ 496 #define ENET_DMA_INTEN_AIE BIT(15) /*!< abnormal interrupt summary enable */ 497 #define ENET_DMA_INTEN_NIE BIT(16) /*!< normal interrupt summary enable */ 498 499 /* ENET_DMA_MFBOCNT */ 500 #define ENET_DMA_MFBOCNT_MSFC BITS(0,15) /*!< missed frames by the controller */ 501 #define ENET_DMA_MFBOCNT_MSFA BITS(17,27) /*!< missed frames by the application */ 502 503 /* ENET_DMA_RSWDC */ 504 #define ENET_DMA_RSWDC_WDCFRS BITS(0,7) /*!< watchdog counter for receive status (RS) */ 505 506 /* ENET_DMA_CTDADDR */ 507 #define ENET_DMA_CTDADDR_TDAP BITS(0,31) /*!< transmit descriptor address pointer */ 508 509 /* ENET_DMA_CRDADDR */ 510 #define ENET_DMA_CRDADDR_RDAP BITS(0,31) /*!< receive descriptor address pointer */ 511 512 /* ENET_DMA_CTBADDR */ 513 #define ENET_DMA_CTBADDR_TBAP BITS(0,31) /*!< transmit buffer address pointer */ 514 515 /* ENET_DMA_CRBADDR */ 516 #define ENET_DMA_CRBADDR_RBAP BITS(0,31) /*!< receive buffer address pointer */ 517 518 /* ENET DMA Tx descriptor TDES0 */ 519 #define ENET_TDES0_DB BIT(0) /*!< deferred */ 520 #define ENET_TDES0_UFE BIT(1) /*!< underflow error */ 521 #define ENET_TDES0_EXD BIT(2) /*!< excessive deferral */ 522 #define ENET_TDES0_COCNT BITS(3,6) /*!< collision count */ 523 #define ENET_TDES0_VFRM BIT(7) /*!< VLAN frame */ 524 #define ENET_TDES0_ECO BIT(8) /*!< excessive collision */ 525 #define ENET_TDES0_LCO BIT(9) /*!< late collision */ 526 #define ENET_TDES0_NCA BIT(10) /*!< no carrier */ 527 #define ENET_TDES0_LCA BIT(11) /*!< loss of carrier */ 528 #define ENET_TDES0_IPPE BIT(12) /*!< IP payload error */ 529 #define ENET_TDES0_FRMF BIT(13) /*!< frame flushed */ 530 #define ENET_TDES0_JT BIT(14) /*!< jabber timeout */ 531 #define ENET_TDES0_ES BIT(15) /*!< error summary */ 532 #define ENET_TDES0_IPHE BIT(16) /*!< IP header error */ 533 #define ENET_TDES0_TTMSS BIT(17) /*!< transmit timestamp status */ 534 #define ENET_TDES0_TCHM BIT(20) /*!< the second address chained mode */ 535 #define ENET_TDES0_TERM BIT(21) /*!< transmit end of ring mode*/ 536 #define ENET_TDES0_CM BITS(22,23) /*!< checksum mode */ 537 #define ENET_TDES0_TTSEN BIT(25) /*!< transmit timestamp function enable */ 538 #define ENET_TDES0_DPAD BIT(26) /*!< disable adding pad */ 539 #define ENET_TDES0_DCRC BIT(27) /*!< disable CRC */ 540 #define ENET_TDES0_FSG BIT(28) /*!< first segment */ 541 #define ENET_TDES0_LSG BIT(29) /*!< last segment */ 542 #define ENET_TDES0_INTC BIT(30) /*!< interrupt on completion */ 543 #define ENET_TDES0_DAV BIT(31) /*!< DAV bit */ 544 545 /* ENET DMA Tx descriptor TDES1 */ 546 #define ENET_TDES1_TB1S BITS(0,12) /*!< transmit buffer 1 size */ 547 #define ENET_TDES1_TB2S BITS(16,28) /*!< transmit buffer 2 size */ 548 549 /* ENET DMA Tx descriptor TDES2 */ 550 #define ENET_TDES2_TB1AP BITS(0,31) /*!< transmit buffer 1 address pointer/transmit frame timestamp low 32-bit value */ 551 552 /* ENET DMA Tx descriptor TDES3 */ 553 #define ENET_TDES3_TB2AP BITS(0,31) /*!< transmit buffer 2 address pointer (or next descriptor address) / transmit frame timestamp high 32-bit value */ 554 555 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE 556 /* ENET DMA Tx descriptor TDES6 */ 557 #define ENET_TDES6_TTSL BITS(0,31) /*!< transmit frame timestamp low 32-bit value */ 558 559 /* ENET DMA Tx descriptor TDES7 */ 560 #define ENET_TDES7_TTSH BITS(0,31) /*!< transmit frame timestamp high 32-bit value */ 561 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ 562 563 /* ENET DMA Rx descriptor RDES0 */ 564 #define ENET_RDES0_PCERR BIT(0) /*!< payload checksum error */ 565 #define ENET_RDES0_EXSV BIT(0) /*!< extended status valid */ 566 #define ENET_RDES0_CERR BIT(1) /*!< CRC error */ 567 #define ENET_RDES0_DBERR BIT(2) /*!< dribble bit error */ 568 #define ENET_RDES0_RERR BIT(3) /*!< receive error */ 569 #define ENET_RDES0_RWDT BIT(4) /*!< receive watchdog timeout */ 570 #define ENET_RDES0_FRMT BIT(5) /*!< frame type */ 571 #define ENET_RDES0_LCO BIT(6) /*!< late collision */ 572 #define ENET_RDES0_IPHERR BIT(7) /*!< IP frame header error */ 573 #define ENET_RDES0_TSV BIT(7) /*!< timestamp valid */ 574 #define ENET_RDES0_LDES BIT(8) /*!< last descriptor */ 575 #define ENET_RDES0_FDES BIT(9) /*!< first descriptor */ 576 #define ENET_RDES0_VTAG BIT(10) /*!< VLAN tag */ 577 #define ENET_RDES0_OERR BIT(11) /*!< overflow Error */ 578 #define ENET_RDES0_LERR BIT(12) /*!< length error */ 579 #define ENET_RDES0_SAFF BIT(13) /*!< SA filter fail */ 580 #define ENET_RDES0_DERR BIT(14) /*!< descriptor error */ 581 #define ENET_RDES0_ERRS BIT(15) /*!< error summary */ 582 #define ENET_RDES0_FRML BITS(16,29) /*!< frame length */ 583 #define ENET_RDES0_DAFF BIT(30) /*!< destination address filter fail */ 584 #define ENET_RDES0_DAV BIT(31) /*!< descriptor available */ 585 586 /* ENET DMA Rx descriptor RDES1 */ 587 #define ENET_RDES1_RB1S BITS(0,12) /*!< receive buffer 1 size */ 588 #define ENET_RDES1_RCHM BIT(14) /*!< receive chained mode for second address */ 589 #define ENET_RDES1_RERM BIT(15) /*!< receive end of ring mode*/ 590 #define ENET_RDES1_RB2S BITS(16,28) /*!< receive buffer 2 size */ 591 #define ENET_RDES1_DINTC BIT(31) /*!< disable interrupt on completion */ 592 593 /* ENET DMA Rx descriptor RDES2 */ 594 #define ENET_RDES2_RB1AP BITS(0,31) /*!< receive buffer 1 address pointer / receive frame timestamp low 32-bit */ 595 596 /* ENET DMA Rx descriptor RDES3 */ 597 #define ENET_RDES3_RB2AP BITS(0,31) /*!< receive buffer 2 address pointer (next descriptor address)/receive frame timestamp high 32-bit value */ 598 599 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE 600 /* ENET DMA Rx descriptor RDES4 */ 601 #define ENET_RDES4_IPPLDT BITS(0,2) /*!< IP frame payload type */ 602 #define ENET_RDES4_IPHERR BIT(3) /*!< IP frame header error */ 603 #define ENET_RDES4_IPPLDERR BIT(4) /*!< IP frame payload error */ 604 #define ENET_RDES4_IPCKSB BIT(5) /*!< IP frame checksum bypassed */ 605 #define ENET_RDES4_IPF4 BIT(6) /*!< IP frame in version 4 */ 606 #define ENET_RDES4_IPF6 BIT(7) /*!< IP frame in version 6 */ 607 #define ENET_RDES4_PTPMT BITS(8,11) /*!< PTP message type */ 608 #define ENET_RDES4_PTPOEF BIT(12) /*!< PTP on ethernet frame */ 609 #define ENET_RDES4_PTPVF BIT(13) /*!< PTP version format */ 610 611 /* ENET DMA Rx descriptor RDES6 */ 612 #define ENET_RDES6_RTSL BITS(0,31) /*!< receive frame timestamp low 32-bit value */ 613 614 /* ENET DMA Rx descriptor RDES7 */ 615 #define ENET_RDES7_RTSH BITS(0,31) /*!< receive frame timestamp high 32-bit value */ 616 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ 617 618 /* constants definitions */ 619 /* define bit position and its register index offset */ 620 #define ENET_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 621 #define ENET_REG_VAL(periph) (REG32(ENET + ((uint32_t)(periph) >> 6))) 622 #define ENET_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 623 624 /* ENET clock range judgement */ 625 #define ENET_RANGE(hclk, n, m) (((hclk) >= (n))&&((hclk) < (m))) 626 627 /* define MAC address configuration and reference address */ 628 #define ENET_SET_MACADDRH(p) (((uint32_t)(p)[5] << 8) | (uint32_t)(p)[4]) 629 #define ENET_SET_MACADDRL(p) (((uint32_t)(p)[3] << 24) | ((uint32_t)(p)[2] << 16) | ((uint32_t)(p)[1] << 8) | (uint32_t)(p)[0]) 630 #define ENET_ADDRH_BASE ((ENET) + 0x40U) 631 #define ENET_ADDRL_BASE ((ENET) + 0x44U) 632 #define ENET_GET_MACADDR(offset, n) ((uint8_t)((REG32((ENET_ADDRL_BASE + (offset)) - (((n) / 4U) * 4U)) >> (8U * ((n) % 4U))) & 0xFFU)) 633 634 /* register offset */ 635 #define MAC_FCTL_REG_OFFSET ((uint16_t)0x0018U) /*!< MAC flow control register offset */ 636 #define MAC_WUM_REG_OFFSET ((uint16_t)0x002CU) /*!< MAC wakeup management register offset */ 637 #define MAC_INTF_REG_OFFSET ((uint16_t)0x0038U) /*!< MAC interrupt flag register offset */ 638 #define MAC_INTMSK_REG_OFFSET ((uint16_t)0x003CU) /*!< MAC interrupt mask register offset */ 639 640 #define MSC_RINTF_REG_OFFSET ((uint16_t)0x0104U) /*!< MSC receive interrupt flag register offset */ 641 #define MSC_TINTF_REG_OFFSET ((uint16_t)0x0108U) /*!< MSC transmit interrupt flag register offset */ 642 #define MSC_RINTMSK_REG_OFFSET ((uint16_t)0x010CU) /*!< MSC receive interrupt mask register offset */ 643 #define MSC_TINTMSK_REG_OFFSET ((uint16_t)0x0110U) /*!< MSC transmit interrupt mask register offset */ 644 #define MSC_SCCNT_REG_OFFSET ((uint16_t)0x014CU) /*!< MSC transmitted good frames after a single collision counter register offset */ 645 #define MSC_MSCCNT_REG_OFFSET ((uint16_t)0x0150U) /*!< MSC transmitted good frames after more than a single collision counter register offset */ 646 #define MSC_TGFCNT_REG_OFFSET ((uint16_t)0x0168U) /*!< MSC transmitted good frames counter register offset */ 647 #define MSC_RFCECNT_REG_OFFSET ((uint16_t)0x0194U) /*!< MSC received frames with CRC error counter register offset */ 648 #define MSC_RFAECNT_REG_OFFSET ((uint16_t)0x0198U) /*!< MSC received frames with alignment error counter register offset */ 649 #define MSC_RGUFCNT_REG_OFFSET ((uint16_t)0x01C4U) /*!< MSC received good unicast frames counter register offset */ 650 651 #define PTP_TSF_REG_OFFSET ((uint16_t)0x0728U) /*!< PTP time stamp flag register offset */ 652 653 #define DMA_STAT_REG_OFFSET ((uint16_t)0x1014U) /*!< DMA status register offset */ 654 #define DMA_INTEN_REG_OFFSET ((uint16_t)0x101CU) /*!< DMA interrupt enable register offset */ 655 #define DMA_TDTADDR_REG_OFFSET ((uint16_t)0x1010U) /*!< DMA transmit descriptor table address register offset */ 656 #define DMA_CTDADDR_REG_OFFSET ((uint16_t)0x1048U) /*!< DMA current transmit descriptor address register */ 657 #define DMA_CTBADDR_REG_OFFSET ((uint16_t)0x1050U) /*!< DMA current transmit buffer address register */ 658 #define DMA_RDTADDR_REG_OFFSET ((uint16_t)0x100CU) /*!< DMA receive descriptor table address register */ 659 #define DMA_CRDADDR_REG_OFFSET ((uint16_t)0x104CU) /*!< DMA current receive descriptor address register */ 660 #define DMA_CRBADDR_REG_OFFSET ((uint16_t)0x1054U) /*!< DMA current receive buffer address register */ 661 662 /* ENET status flag get */ 663 typedef enum 664 { 665 /* ENET_MAC_WUM register */ 666 ENET_MAC_FLAG_MPKR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 5U), /*!< magic packet received flag */ 667 ENET_MAC_FLAG_WUFR = ENET_REGIDX_BIT(MAC_WUM_REG_OFFSET, 6U), /*!< wakeup frame received flag */ 668 /* ENET_MAC_FCTL register */ 669 ENET_MAC_FLAG_FLOWCONTROL = ENET_REGIDX_BIT(MAC_FCTL_REG_OFFSET, 0U), /*!< flow control status flag */ 670 /* ENET_MAC_INTF register */ 671 ENET_MAC_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ 672 ENET_MAC_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ 673 ENET_MAC_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ 674 ENET_MAC_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ 675 ENET_MAC_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ 676 /* ENET_PTP_TSF register */ 677 ENET_PTP_FLAG_TSSCO = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 0U), /*!< timestamp second counter overflow flag */ 678 ENET_PTP_FLAG_TTM = ENET_REGIDX_BIT(PTP_TSF_REG_OFFSET, 1U), /*!< target time match flag */ 679 /* ENET_MSC_RINTF register */ 680 ENET_MSC_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ 681 ENET_MSC_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ 682 ENET_MSC_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ 683 /* ENET_MSC_TINTF register */ 684 ENET_MSC_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ 685 ENET_MSC_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ 686 ENET_MSC_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ 687 /* ENET_DMA_STAT register */ 688 ENET_DMA_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ 689 ENET_DMA_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ 690 ENET_DMA_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ 691 ENET_DMA_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ 692 ENET_DMA_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ 693 ENET_DMA_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ 694 ENET_DMA_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ 695 ENET_DMA_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ 696 ENET_DMA_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ 697 ENET_DMA_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ 698 ENET_DMA_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ 699 ENET_DMA_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ 700 ENET_DMA_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ 701 ENET_DMA_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ 702 ENET_DMA_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ 703 ENET_DMA_FLAG_EB_DMA_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 23U), /*!< error during data transfer by RxDMA/TxDMA flag */ 704 ENET_DMA_FLAG_EB_TRANSFER_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 24U), /*!< error during write/read transfer flag */ 705 ENET_DMA_FLAG_EB_ACCESS_ERROR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 25U), /*!< error during data buffer/descriptor access flag */ 706 ENET_DMA_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ 707 ENET_DMA_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ 708 ENET_DMA_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ 709 }enet_flag_enum; 710 711 /* ENET stutus flag clear */ 712 typedef enum 713 { 714 /* ENET_DMA_STAT register */ 715 ENET_DMA_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ 716 ENET_DMA_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ 717 ENET_DMA_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ 718 ENET_DMA_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ 719 ENET_DMA_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ 720 ENET_DMA_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ 721 ENET_DMA_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ 722 ENET_DMA_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ 723 ENET_DMA_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ 724 ENET_DMA_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ 725 ENET_DMA_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ 726 ENET_DMA_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ 727 ENET_DMA_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ 728 ENET_DMA_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ 729 ENET_DMA_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ 730 }enet_flag_clear_enum; 731 732 /* ENET interrupt enable/disable */ 733 typedef enum 734 { 735 /* ENET_MAC_INTMSK register */ 736 ENET_MAC_INT_WUMIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 3U), /*!< WUM interrupt mask */ 737 ENET_MAC_INT_TMSTIM = ENET_REGIDX_BIT(MAC_INTMSK_REG_OFFSET, 9U), /*!< timestamp trigger interrupt mask */ 738 /* ENET_MSC_RINTMSK register */ 739 ENET_MSC_INT_RFCEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 5U), /*!< received frame CRC error interrupt mask */ 740 ENET_MSC_INT_RFAEIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 6U), /*!< received frames alignment error interrupt mask */ 741 ENET_MSC_INT_RGUFIM = ENET_REGIDX_BIT(MSC_RINTMSK_REG_OFFSET, 17U), /*!< received good unicast frames interrupt mask */ 742 /* ENET_MSC_TINTMSK register */ 743 ENET_MSC_INT_TGFSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 14U), /*!< transmitted good frames single collision interrupt mask */ 744 ENET_MSC_INT_TGFMSCIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 15U), /*!< transmitted good frames more single collision interrupt mask */ 745 ENET_MSC_INT_TGFIM = ENET_REGIDX_BIT(MSC_TINTMSK_REG_OFFSET, 21U), /*!< transmitted good frames interrupt mask */ 746 /* ENET_DMA_INTEN register */ 747 ENET_DMA_INT_TIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 0U), /*!< transmit interrupt enable */ 748 ENET_DMA_INT_TPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 1U), /*!< transmit process stopped interrupt enable */ 749 ENET_DMA_INT_TBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 2U), /*!< transmit buffer unavailable interrupt enable */ 750 ENET_DMA_INT_TJTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 3U), /*!< transmit jabber timeout interrupt enable */ 751 ENET_DMA_INT_ROIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 4U), /*!< receive overflow interrupt enable */ 752 ENET_DMA_INT_TUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 5U), /*!< transmit underflow interrupt enable */ 753 ENET_DMA_INT_RIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 6U), /*!< receive interrupt enable */ 754 ENET_DMA_INT_RBUIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 7U), /*!< receive buffer unavailable interrupt enable */ 755 ENET_DMA_INT_RPSIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 8U), /*!< receive process stopped interrupt enable */ 756 ENET_DMA_INT_RWTIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 9U), /*!< receive watchdog timeout interrupt enable */ 757 ENET_DMA_INT_ETIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 10U), /*!< early transmit interrupt enable */ 758 ENET_DMA_INT_FBEIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 13U), /*!< fatal bus error interrupt enable */ 759 ENET_DMA_INT_ERIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 14U), /*!< early receive interrupt enable */ 760 ENET_DMA_INT_AIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 15U), /*!< abnormal interrupt summary enable */ 761 ENET_DMA_INT_NIE = ENET_REGIDX_BIT(DMA_INTEN_REG_OFFSET, 16U), /*!< normal interrupt summary enable */ 762 }enet_int_enum; 763 764 /* ENET interrupt flag get */ 765 typedef enum 766 { 767 /* ENET_MAC_INTF register */ 768 ENET_MAC_INT_FLAG_WUM = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 3U), /*!< WUM status flag */ 769 ENET_MAC_INT_FLAG_MSC = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 4U), /*!< MSC status flag */ 770 ENET_MAC_INT_FLAG_MSCR = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 5U), /*!< MSC receive status flag */ 771 ENET_MAC_INT_FLAG_MSCT = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 6U), /*!< MSC transmit status flag */ 772 ENET_MAC_INT_FLAG_TMST = ENET_REGIDX_BIT(MAC_INTF_REG_OFFSET, 9U), /*!< timestamp trigger status flag */ 773 /* ENET_MSC_RINTF register */ 774 ENET_MSC_INT_FLAG_RFCE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 5U), /*!< received frames CRC error flag */ 775 ENET_MSC_INT_FLAG_RFAE = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 6U), /*!< received frames alignment error flag */ 776 ENET_MSC_INT_FLAG_RGUF = ENET_REGIDX_BIT(MSC_RINTF_REG_OFFSET, 17U), /*!< received good unicast frames flag */ 777 /* ENET_MSC_TINTF register */ 778 ENET_MSC_INT_FLAG_TGFSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 14U), /*!< transmitted good frames single collision flag */ 779 ENET_MSC_INT_FLAG_TGFMSC = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 15U), /*!< transmitted good frames more single collision flag */ 780 ENET_MSC_INT_FLAG_TGF = ENET_REGIDX_BIT(MSC_TINTF_REG_OFFSET, 21U), /*!< transmitted good frames flag */ 781 /* ENET_DMA_STAT register */ 782 ENET_DMA_INT_FLAG_TS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ 783 ENET_DMA_INT_FLAG_TPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ 784 ENET_DMA_INT_FLAG_TBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ 785 ENET_DMA_INT_FLAG_TJT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ 786 ENET_DMA_INT_FLAG_RO = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ 787 ENET_DMA_INT_FLAG_TU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ 788 ENET_DMA_INT_FLAG_RS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ 789 ENET_DMA_INT_FLAG_RBU = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ 790 ENET_DMA_INT_FLAG_RPS = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ 791 ENET_DMA_INT_FLAG_RWT = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ 792 ENET_DMA_INT_FLAG_ET = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ 793 ENET_DMA_INT_FLAG_FBE = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ 794 ENET_DMA_INT_FLAG_ER = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ 795 ENET_DMA_INT_FLAG_AI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ 796 ENET_DMA_INT_FLAG_NI = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ 797 ENET_DMA_INT_FLAG_MSC = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 27U), /*!< MSC status flag */ 798 ENET_DMA_INT_FLAG_WUM = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 28U), /*!< WUM status flag */ 799 ENET_DMA_INT_FLAG_TST = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 29U), /*!< timestamp trigger status flag */ 800 }enet_int_flag_enum; 801 802 /* ENET interrupt flag clear */ 803 typedef enum 804 { 805 /* ENET_DMA_STAT register */ 806 ENET_DMA_INT_FLAG_TS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 0U), /*!< transmit status flag */ 807 ENET_DMA_INT_FLAG_TPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 1U), /*!< transmit process stopped status flag */ 808 ENET_DMA_INT_FLAG_TBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 2U), /*!< transmit buffer unavailable status flag */ 809 ENET_DMA_INT_FLAG_TJT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 3U), /*!< transmit jabber timeout status flag */ 810 ENET_DMA_INT_FLAG_RO_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 4U), /*!< receive overflow status flag */ 811 ENET_DMA_INT_FLAG_TU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 5U), /*!< transmit underflow status flag */ 812 ENET_DMA_INT_FLAG_RS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 6U), /*!< receive status flag */ 813 ENET_DMA_INT_FLAG_RBU_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 7U), /*!< receive buffer unavailable status flag */ 814 ENET_DMA_INT_FLAG_RPS_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 8U), /*!< receive process stopped status flag */ 815 ENET_DMA_INT_FLAG_RWT_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 9U), /*!< receive watchdog timeout status flag */ 816 ENET_DMA_INT_FLAG_ET_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 10U), /*!< early transmit status flag */ 817 ENET_DMA_INT_FLAG_FBE_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 13U), /*!< fatal bus error status flag */ 818 ENET_DMA_INT_FLAG_ER_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 14U), /*!< early receive status flag */ 819 ENET_DMA_INT_FLAG_AI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 15U), /*!< abnormal interrupt summary flag */ 820 ENET_DMA_INT_FLAG_NI_CLR = ENET_REGIDX_BIT(DMA_STAT_REG_OFFSET, 16U), /*!< normal interrupt summary flag */ 821 }enet_int_flag_clear_enum; 822 823 /* current RX/TX descriptor/buffer/descriptor table address get */ 824 typedef enum 825 { 826 ENET_RX_DESC_TABLE = DMA_RDTADDR_REG_OFFSET, /*!< RX descriptor table */ 827 ENET_RX_CURRENT_DESC = DMA_CRDADDR_REG_OFFSET, /*!< current RX descriptor */ 828 ENET_RX_CURRENT_BUFFER = DMA_CRBADDR_REG_OFFSET, /*!< current RX buffer */ 829 ENET_TX_DESC_TABLE = DMA_TDTADDR_REG_OFFSET, /*!< TX descriptor table */ 830 ENET_TX_CURRENT_DESC = DMA_CTDADDR_REG_OFFSET, /*!< current TX descriptor */ 831 ENET_TX_CURRENT_BUFFER = DMA_CTBADDR_REG_OFFSET /*!< current TX buffer */ 832 }enet_desc_reg_enum; 833 834 /* MAC statistics counter get */ 835 typedef enum 836 { 837 ENET_MSC_TX_SCCNT = MSC_SCCNT_REG_OFFSET, /*!< MSC transmitted good frames after a single collision counter */ 838 ENET_MSC_TX_MSCCNT = MSC_MSCCNT_REG_OFFSET, /*!< MSC transmitted good frames after more than a single collision counter */ 839 ENET_MSC_TX_TGFCNT = MSC_TGFCNT_REG_OFFSET, /*!< MSC transmitted good frames counter */ 840 ENET_MSC_RX_RFCECNT = MSC_RFCECNT_REG_OFFSET, /*!< MSC received frames with CRC error counter */ 841 ENET_MSC_RX_RFAECNT = MSC_RFAECNT_REG_OFFSET, /*!< MSC received frames with alignment error counter */ 842 ENET_MSC_RX_RGUFCNT = MSC_RGUFCNT_REG_OFFSET /*!< MSC received good unicast frames counter */ 843 }enet_msc_counter_enum; 844 845 /* function option, used for ENET initialization */ 846 typedef enum 847 { 848 FORWARD_OPTION = BIT(0), /*!< configure the frame forward related parameters */ 849 DMABUS_OPTION = BIT(1), /*!< configure the DMA bus mode related parameters */ 850 DMA_MAXBURST_OPTION = BIT(2), /*!< configure the DMA max burst related parameters */ 851 DMA_ARBITRATION_OPTION = BIT(3), /*!< configure the DMA arbitration related parameters */ 852 STORE_OPTION = BIT(4), /*!< configure the store forward mode related parameters */ 853 DMA_OPTION = BIT(5), /*!< configure the DMA control related parameters */ 854 VLAN_OPTION = BIT(6), /*!< configure the VLAN tag related parameters */ 855 FLOWCTL_OPTION = BIT(7), /*!< configure the flow control related parameters */ 856 HASHH_OPTION = BIT(8), /*!< configure the hash list high 32-bit related parameters */ 857 HASHL_OPTION = BIT(9), /*!< configure the hash list low 32-bit related parameters */ 858 FILTER_OPTION = BIT(10), /*!< configure the frame filter control related parameters */ 859 HALFDUPLEX_OPTION = BIT(11), /*!< configure the halfduplex related parameters */ 860 TIMER_OPTION = BIT(12), /*!< configure the frame timer related parameters */ 861 INTERFRAMEGAP_OPTION = BIT(13), /*!< configure the inter frame gap related parameters */ 862 }enet_option_enum; 863 864 /* phy mode and mac loopback configurations */ 865 typedef enum 866 { 867 ENET_AUTO_NEGOTIATION = 0x01U, /*!< PHY auto negotiation */ 868 ENET_100M_FULLDUPLEX = (ENET_MAC_CFG_SPD | ENET_MAC_CFG_DPM), /*!< 100Mbit/s, full-duplex */ 869 ENET_100M_HALFDUPLEX = ENET_MAC_CFG_SPD , /*!< 100Mbit/s, half-duplex */ 870 ENET_10M_FULLDUPLEX = ENET_MAC_CFG_DPM, /*!< 10Mbit/s, full-duplex */ 871 ENET_10M_HALFDUPLEX = (uint32_t)0x00000000U, /*!< 10Mbit/s, half-duplex */ 872 ENET_LOOPBACKMODE = (ENET_MAC_CFG_LBM | ENET_MAC_CFG_DPM) /*!< MAC in loopback mode at the MII */ 873 }enet_mediamode_enum; 874 875 /* IP frame checksum function */ 876 typedef enum 877 { 878 ENET_NO_AUTOCHECKSUM = (uint32_t)0x00000000U, /*!< disable IP frame checksum function */ 879 ENET_AUTOCHECKSUM_DROP_FAILFRAMES = ENET_MAC_CFG_IPFCO, /*!< enable IP frame checksum function */ 880 ENET_AUTOCHECKSUM_ACCEPT_FAILFRAMES = (ENET_MAC_CFG_IPFCO|ENET_DMA_CTL_DTCERFD) /*!< enable IP frame checksum function, and the received frame 881 with only payload error but no other errors will not be dropped */ 882 }enet_chksumconf_enum; 883 884 /* received frame filter function */ 885 typedef enum 886 { 887 ENET_PROMISCUOUS_MODE = ENET_MAC_FRMF_PM, /*!< promiscuous mode enabled */ 888 ENET_RECEIVEALL = (int32_t)ENET_MAC_FRMF_FAR, /*!< all received frame are forwarded to application */ 889 ENET_BROADCAST_FRAMES_PASS = (uint32_t)0x00000000U, /*!< the address filters pass all received broadcast frames */ 890 ENET_BROADCAST_FRAMES_DROP = ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ 891 }enet_frmrecept_enum; 892 893 /* register group value get */ 894 typedef enum 895 { 896 ALL_MAC_REG = 0U, /*!< MAC register group */ 897 ALL_MSC_REG = 22U, /*!< MSC register group */ 898 ALL_PTP_REG = 33U, /*!< PTP register group */ 899 ALL_DMA_REG = 44U, /*!< DMA register group */ 900 }enet_registers_type_enum; 901 902 /* dma direction select */ 903 typedef enum 904 { 905 ENET_DMA_TX = ENET_DMA_STAT_TP, /*!< DMA transmit direction */ 906 ENET_DMA_RX = ENET_DMA_STAT_RP /*!< DMA receive direction */ 907 }enet_dmadirection_enum; 908 909 /* PHY operation direction select */ 910 typedef enum 911 { 912 ENET_PHY_READ = (uint32_t)0x00000000, /*!< read PHY */ 913 ENET_PHY_WRITE = ENET_MAC_PHY_CTL_PW /*!< write PHY */ 914 }enet_phydirection_enum; 915 916 /* register operation direction select */ 917 typedef enum 918 { 919 ENET_REG_READ, /*!< read register */ 920 ENET_REG_WRITE /*!< write register */ 921 }enet_regdirection_enum; 922 923 /* ENET MAC addresses */ 924 typedef enum 925 { 926 ENET_MAC_ADDRESS0 = ((uint32_t)0x00000000), /*!< MAC address0 */ 927 ENET_MAC_ADDRESS1 = ((uint32_t)0x00000008), /*!< MAC address1 */ 928 ENET_MAC_ADDRESS2 = ((uint32_t)0x00000010), /*!< MAC address2 */ 929 ENET_MAC_ADDRESS3 = ((uint32_t)0x00000018) /*!< MAC address3 */ 930 }enet_macaddress_enum; 931 932 /* descriptor information */ 933 typedef enum 934 { 935 TXDESC_COLLISION_COUNT, /*!< the number of collisions occurred before the frame was transmitted */ 936 TXDESC_BUFFER_1_ADDR, /*!< transmit frame buffer 1 address */ 937 RXDESC_FRAME_LENGTH, /*!< the byte length of the received frame that was transferred to the buffer */ 938 RXDESC_BUFFER_1_SIZE, /*!< receive buffer 1 size */ 939 RXDESC_BUFFER_2_SIZE, /*!< receive buffer 2 size */ 940 RXDESC_BUFFER_1_ADDR /*!< receive frame buffer 1 address */ 941 }enet_descstate_enum; 942 943 /* MSC counters preset mode */ 944 typedef enum 945 { 946 ENET_MSC_PRESET_NONE = 0U, /*!< do not preset MSC counter */ 947 ENET_MSC_PRESET_HALF = ENET_MSC_CTL_PMC, /*!< preset all MSC counters to almost-half(0x7FFF FFF0) value */ 948 ENET_MSC_PRESET_FULL = ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM /*!< preset all MSC counters to almost-full(0xFFFF FFF0) value */ 949 }enet_msc_preset_enum; 950 951 typedef enum{ 952 ENET_CKNT_ORDINARY = PTP_TSCTL_CKNT(0), /*!< type of ordinary clock node type for timestamp */ 953 ENET_CKNT_BOUNDARY = PTP_TSCTL_CKNT(1), /*!< type of boundary clock node type for timestamp */ 954 ENET_CKNT_END_TO_END = PTP_TSCTL_CKNT(2), /*!< type of end-to-end transparent clock node type for timestamp */ 955 ENET_CKNT_PEER_TO_PEER = PTP_TSCTL_CKNT(3), /*!< type of peer-to-peer transparent clock node type for timestamp */ 956 ENET_PTP_SYSTIME_INIT = ENET_PTP_TSCTL_TMSSTI, /*!< timestamp initialize */ 957 ENET_PTP_SYSTIME_UPDATE = ENET_PTP_TSCTL_TMSSTU, /*!< timestamp update */ 958 ENET_PTP_ADDEND_UPDATE = ENET_PTP_TSCTL_TMSARU, /*!< addend register update */ 959 ENET_PTP_FINEMODE = (int32_t)(ENET_PTP_TSCTL_TMSFCU| BIT(31)), /*!< the system timestamp uses the fine method for updating */ 960 ENET_PTP_COARSEMODE = ENET_PTP_TSCTL_TMSFCU, /*!< the system timestamp uses the coarse method for updating */ 961 ENET_SUBSECOND_DIGITAL_ROLLOVER = (int32_t)(ENET_PTP_TSCTL_SCROM | BIT(31)), /*!< digital rollover mode */ 962 ENET_SUBSECOND_BINARY_ROLLOVER = ENET_PTP_TSCTL_SCROM, /*!< binary rollover mode */ 963 ENET_SNOOPING_PTP_VERSION_2 = (int32_t)(ENET_PTP_TSCTL_PFSV| BIT(31)), /*!< version 2 */ 964 ENET_SNOOPING_PTP_VERSION_1 = ENET_PTP_TSCTL_PFSV, /*!< version 1 */ 965 ENET_EVENT_TYPE_MESSAGES_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_ETMSEN| BIT(31)), /*!< only event type messages are taken snapshot */ 966 ENET_ALL_TYPE_MESSAGES_SNAPSHOT = ENET_PTP_TSCTL_ETMSEN, /*!< all type messages are taken snapshot except announce, management and signaling message */ 967 ENET_MASTER_NODE_MESSAGE_SNAPSHOT = (int32_t)(ENET_PTP_TSCTL_MNMSEN| BIT(31)), /*!< snapshot is only take for master node message */ 968 ENET_SLAVE_NODE_MESSAGE_SNAPSHOT = ENET_PTP_TSCTL_MNMSEN, /*!< snapshot is only taken for slave node message */ 969 }enet_ptp_function_enum; 970 971 /* structure for initialization of the ENET */ 972 typedef struct 973 { 974 uint32_t option_enable; /*!< select which function to configure */ 975 uint32_t forward_frame; /*!< frame forward related parameters */ 976 uint32_t dmabus_mode; /*!< DMA bus mode related parameters */ 977 uint32_t dma_maxburst; /*!< DMA max burst related parameters */ 978 uint32_t dma_arbitration; /*!< DMA Tx and Rx arbitration related parameters */ 979 uint32_t store_forward_mode; /*!< store forward mode related parameters */ 980 uint32_t dma_function; /*!< DMA control related parameters */ 981 uint32_t vlan_config; /*!< VLAN tag related parameters */ 982 uint32_t flow_control; /*!< flow control related parameters */ 983 uint32_t hashtable_high; /*!< hash list high 32-bit related parameters */ 984 uint32_t hashtable_low; /*!< hash list low 32-bit related parameters */ 985 uint32_t framesfilter_mode; /*!< frame filter control related parameters */ 986 uint32_t halfduplex_param; /*!< halfduplex related parameters */ 987 uint32_t timer_config; /*!< frame timer related parameters */ 988 uint32_t interframegap; /*!< inter frame gap related parameters */ 989 }enet_initpara_struct; 990 991 /* structure for ENET DMA desciptors */ 992 typedef struct 993 { 994 uint32_t status; /*!< status */ 995 uint32_t control_buffer_size; /*!< control and buffer1, buffer2 lengths */ 996 uint32_t buffer1_addr; /*!< buffer1 address pointer/timestamp low */ 997 uint32_t buffer2_next_desc_addr; /*!< buffer2 or next descriptor address pointer/timestamp high */ 998 999 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE 1000 uint32_t extended_status; /*!< extended status */ 1001 uint32_t reserved; /*!< reserved */ 1002 uint32_t timestamp_low; /*!< timestamp low */ 1003 uint32_t timestamp_high; /*!< timestamp high */ 1004 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ 1005 1006 } enet_descriptors_struct; 1007 1008 /* structure of PTP system time */ 1009 typedef struct 1010 { 1011 uint32_t second; /*!< second of system time */ 1012 uint32_t subsecond; /*!< subsecond of system time */ 1013 uint32_t sign; /*!< sign of system time */ 1014 }enet_ptp_systime_struct; 1015 1016 /* mac_cfg register value */ 1017 #define MAC_CFG_BOL(regval) (BITS(5,6) & ((uint32_t)(regval) << 5)) /*!< write value to ENET_MAC_CFG_BOL bit field */ 1018 #define ENET_BACKOFFLIMIT_10 MAC_CFG_BOL(0) /*!< min (n, 10) */ 1019 #define ENET_BACKOFFLIMIT_8 MAC_CFG_BOL(1) /*!< min (n, 8) */ 1020 #define ENET_BACKOFFLIMIT_4 MAC_CFG_BOL(2) /*!< min (n, 4) */ 1021 #define ENET_BACKOFFLIMIT_1 MAC_CFG_BOL(3) /*!< min (n, 1) */ 1022 1023 #define MAC_CFG_IGBS(regval) (BITS(17,19) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_MAC_CFG_IGBS bit field */ 1024 #define ENET_INTERFRAMEGAP_96BIT MAC_CFG_IGBS(0) /*!< minimum 96 bit times */ 1025 #define ENET_INTERFRAMEGAP_88BIT MAC_CFG_IGBS(1) /*!< minimum 88 bit times */ 1026 #define ENET_INTERFRAMEGAP_80BIT MAC_CFG_IGBS(2) /*!< minimum 80 bit times */ 1027 #define ENET_INTERFRAMEGAP_72BIT MAC_CFG_IGBS(3) /*!< minimum 72 bit times */ 1028 #define ENET_INTERFRAMEGAP_64BIT MAC_CFG_IGBS(4) /*!< minimum 64 bit times */ 1029 #define ENET_INTERFRAMEGAP_56BIT MAC_CFG_IGBS(5) /*!< minimum 56 bit times */ 1030 #define ENET_INTERFRAMEGAP_48BIT MAC_CFG_IGBS(6) /*!< minimum 48 bit times */ 1031 #define ENET_INTERFRAMEGAP_40BIT MAC_CFG_IGBS(7) /*!< minimum 40 bit times */ 1032 1033 #define ENET_TYPEFRAME_CRC_DROP_ENABLE ENET_MAC_CFG_TFCD /*!< FCS field(last 4 bytes) of frame will be dropped before forwarding */ 1034 #define ENET_TYPEFRAME_CRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< FCS field(last 4 bytes) of frame will not be dropped before forwarding */ 1035 #define ENET_TYPEFRAME_CRC_DROP ENET_MAC_CFG_TFCD /*!< the function that FCS field(last 4 bytes) of frame will be dropped before forwarding */ 1036 1037 #define ENET_WATCHDOG_ENABLE ((uint32_t)0x00000000U) /*!< the MAC allows no more than 2048 bytes of the frame being received */ 1038 #define ENET_WATCHDOG_DISABLE ENET_MAC_CFG_WDD /*!< the MAC disables the watchdog timer on the receiver, and can receive frames of up to 16384 bytes */ 1039 1040 #define ENET_JABBER_ENABLE ((uint32_t)0x00000000U) /*!< the maximum transmission byte is 2048 */ 1041 #define ENET_JABBER_DISABLE ENET_MAC_CFG_JBD /*!< the maximum transmission byte can be 16384 */ 1042 1043 #define ENET_CARRIERSENSE_ENABLE ((uint32_t)0x00000000U) /*!< the MAC transmitter generates carrier sense error and aborts the transmission */ 1044 #define ENET_CARRIERSENSE_DISABLE ENET_MAC_CFG_CSD /*!< the MAC transmitter ignores the MII CRS signal during frame transmission in half-duplex mode */ 1045 1046 #define ENET_SPEEDMODE_10M ((uint32_t)0x00000000U) /*!< 10 Mbit/s */ 1047 #define ENET_SPEEDMODE_100M ENET_MAC_CFG_SPD /*!< 100 Mbit/s */ 1048 1049 #define ENET_RECEIVEOWN_ENABLE ((uint32_t)0x00000000U) /*!< the MAC receives all packets that are given by the PHY while transmitting */ 1050 #define ENET_RECEIVEOWN_DISABLE ENET_MAC_CFG_ROD /*!< the MAC disables the reception of frames in half-duplex mode */ 1051 1052 #define ENET_LOOPBACKMODE_ENABLE ENET_MAC_CFG_LBM /*!< the MAC operates in loopback mode at the MII */ 1053 #define ENET_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000U) /*!< the MAC operates in normal mode */ 1054 1055 #define ENET_MODE_FULLDUPLEX ENET_MAC_CFG_DPM /*!< full-duplex mode enable */ 1056 #define ENET_MODE_HALFDUPLEX ((uint32_t)0x00000000U) /*!< half-duplex mode enable */ 1057 1058 #define ENET_CHECKSUMOFFLOAD_ENABLE ENET_MAC_CFG_IPFCO /*!< IP frame checksum offload function enabled for received IP frame */ 1059 #define ENET_CHECKSUMOFFLOAD_DISABLE ((uint32_t)0x00000000U) /*!< the checksum offload function in the receiver is disabled */ 1060 1061 #define ENET_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000U) /*!< the MAC attempts retries up to 16 times based on the settings of BOL*/ 1062 #define ENET_RETRYTRANSMISSION_DISABLE ENET_MAC_CFG_RTD /*!< the MAC attempts only 1 transmission */ 1063 1064 #define ENET_AUTO_PADCRC_DROP_ENABLE ENET_MAC_CFG_APCD /*!< the MAC strips the Pad/FCS field on received frames */ 1065 #define ENET_AUTO_PADCRC_DROP_DISABLE ((uint32_t)0x00000000U) /*!< the MAC forwards all received frames without modify it */ 1066 #define ENET_AUTO_PADCRC_DROP ENET_MAC_CFG_APCD /*!< the function of the MAC strips the Pad/FCS field on received frames */ 1067 1068 #define ENET_DEFERRALCHECK_ENABLE ENET_MAC_CFG_DFC /*!< the deferral check function is enabled in the MAC */ 1069 #define ENET_DEFERRALCHECK_DISABLE ((uint32_t)0x00000000U) /*!< the deferral check function is disabled */ 1070 1071 /* mac_frmf register value */ 1072 #define MAC_FRMF_PCFRM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_FRMF_PCFRM bit field */ 1073 #define ENET_PCFRM_PREVENT_ALL MAC_FRMF_PCFRM(0) /*!< MAC prevents all control frames from reaching the application */ 1074 #define ENET_PCFRM_PREVENT_PAUSEFRAME MAC_FRMF_PCFRM(1) /*!< MAC only forwards all other control frames except pause control frame */ 1075 #define ENET_PCFRM_FORWARD_ALL MAC_FRMF_PCFRM(2) /*!< MAC forwards all control frames to application even if they fail the address filter */ 1076 #define ENET_PCFRM_FORWARD_FILTERED MAC_FRMF_PCFRM(3) /*!< MAC forwards control frames that only pass the address filter */ 1077 1078 #define ENET_RX_FILTER_DISABLE ENET_MAC_FRMF_FAR /*!< all received frame are forwarded to application */ 1079 #define ENET_RX_FILTER_ENABLE ((uint32_t)0x00000000U) /*!< only the frame passed the filter can be forwarded to application */ 1080 1081 #define ENET_SRC_FILTER_NORMAL_ENABLE ENET_MAC_FRMF_SAFLT /*!< filter source address */ 1082 #define ENET_SRC_FILTER_INVERSE_ENABLE (ENET_MAC_FRMF_SAFLT | ENET_MAC_FRMF_SAIFLT) /*!< inverse source address filtering result */ 1083 #define ENET_SRC_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< source address function in filter disable */ 1084 #define ENET_SRC_FILTER ENET_MAC_FRMF_SAFLT /*!< filter source address function */ 1085 #define ENET_SRC_FILTER_INVERSE ENET_MAC_FRMF_SAIFLT /*!< inverse source address filtering result function */ 1086 1087 #define ENET_BROADCASTFRAMES_ENABLE ((uint32_t)0x00000000U) /*!< the address filters pass all received broadcast frames */ 1088 #define ENET_BROADCASTFRAMES_DISABLE ENET_MAC_FRMF_BFRMD /*!< the address filters filter all incoming broadcast frames */ 1089 1090 #define ENET_DEST_FILTER_INVERSE_ENABLE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result */ 1091 #define ENET_DEST_FILTER_INVERSE_DISABLE ((uint32_t)0x00000000U) /*!< not inverse DA filtering result */ 1092 #define ENET_DEST_FILTER_INVERSE ENET_MAC_FRMF_DAIFLT /*!< inverse DA filtering result function */ 1093 1094 #define ENET_PROMISCUOUS_ENABLE ENET_MAC_FRMF_PM /*!< promiscuous mode enabled */ 1095 #define ENET_PROMISCUOUS_DISABLE ((uint32_t)0x00000000U) /*!< promiscuous mode disabled */ 1096 1097 #define ENET_MULTICAST_FILTER_HASH_OR_PERFECT (ENET_MAC_FRMF_HMF | ENET_MAC_FRMF_HPFLT) /*!< pass multicast frames that match either the perfect or the hash filtering */ 1098 #define ENET_MULTICAST_FILTER_HASH ENET_MAC_FRMF_HMF /*!< pass multicast frames that match the hash filtering */ 1099 #define ENET_MULTICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass multicast frames that match the perfect filtering */ 1100 #define ENET_MULTICAST_FILTER_NONE ENET_MAC_FRMF_MFD /*!< all multicast frames are passed */ 1101 #define ENET_MULTICAST_FILTER_PASS ENET_MAC_FRMF_MFD /*!< pass all multicast frames function */ 1102 #define ENET_MULTICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HMF /*!< HASH multicast filter function */ 1103 #define ENET_FILTER_MODE_EITHER ENET_MAC_FRMF_HPFLT /*!< HASH or perfect filter function */ 1104 1105 #define ENET_UNICAST_FILTER_EITHER (ENET_MAC_FRMF_HUF | ENET_MAC_FRMF_HPFLT) /*!< pass unicast frames that match either the perfect or the hash filtering */ 1106 #define ENET_UNICAST_FILTER_HASH ENET_MAC_FRMF_HUF /*!< pass unicast frames that match the hash filtering */ 1107 #define ENET_UNICAST_FILTER_PERFECT ((uint32_t)0x00000000U) /*!< pass unicast frames that match the perfect filtering */ 1108 #define ENET_UNICAST_FILTER_HASH_MODE ENET_MAC_FRMF_HUF /*!< HASH unicast filter function */ 1109 1110 /* mac_phy_ctl register value */ 1111 #define MAC_PHY_CTL_CLR(regval) (BITS(2,4) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_MAC_PHY_CTL_CLR bit field */ 1112 #define ENET_MDC_HCLK_DIV42 MAC_PHY_CTL_CLR(0) /*!< HCLK:60-100 MHz; MDC clock= HCLK/42 */ 1113 #define ENET_MDC_HCLK_DIV62 MAC_PHY_CTL_CLR(1) /*!< HCLK:100-150 MHz; MDC clock= HCLK/62 */ 1114 #define ENET_MDC_HCLK_DIV16 MAC_PHY_CTL_CLR(2) /*!< HCLK:20-35 MHz; MDC clock= HCLK/16 */ 1115 #define ENET_MDC_HCLK_DIV26 MAC_PHY_CTL_CLR(3) /*!< HCLK:35-60 MHz; MDC clock= HCLK/26 */ 1116 #define ENET_MDC_HCLK_DIV102 MAC_PHY_CTL_CLR(4) /*!< HCLK:150-200 MHz; MDC clock= HCLK/102 */ 1117 1118 #define MAC_PHY_CTL_PR(regval) (BITS(6,10) & ((uint32_t)(regval) << 6)) /*!< write value to ENET_MAC_PHY_CTL_PR bit field */ 1119 1120 #define MAC_PHY_CTL_PA(regval) (BITS(11,15) & ((uint32_t)(regval) << 11)) /*!< write value to ENET_MAC_PHY_CTL_PA bit field */ 1121 1122 /* mac_phy_data register value */ 1123 #define MAC_PHY_DATA_PD(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_PHY_DATA_PD bit field */ 1124 1125 /* mac_fctl register value */ 1126 #define MAC_FCTL_PLTS(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< write value to ENET_MAC_FCTL_PLTS bit field */ 1127 #define ENET_PAUSETIME_MINUS4 MAC_FCTL_PLTS(0) /*!< pause time minus 4 slot times */ 1128 #define ENET_PAUSETIME_MINUS28 MAC_FCTL_PLTS(1) /*!< pause time minus 28 slot times */ 1129 #define ENET_PAUSETIME_MINUS144 MAC_FCTL_PLTS(2) /*!< pause time minus 144 slot times */ 1130 #define ENET_PAUSETIME_MINUS256 MAC_FCTL_PLTS(3) /*!< pause time minus 256 slot times */ 1131 1132 #define ENET_ZERO_QUANTA_PAUSE_ENABLE ((uint32_t)0x00000000U) /*!< enable the automatic zero-quanta generation function */ 1133 #define ENET_ZERO_QUANTA_PAUSE_DISABLE ENET_MAC_FCTL_DZQP /*!< disable the automatic zero-quanta generation function */ 1134 #define ENET_ZERO_QUANTA_PAUSE ENET_MAC_FCTL_DZQP /*!< the automatic zero-quanta generation function */ 1135 1136 #define ENET_MAC0_AND_UNIQUE_ADDRESS_PAUSEDETECT ENET_MAC_FCTL_UPFDT /*!< besides the unique multicast address, MAC also use the MAC0 address to detect pause frame */ 1137 #define ENET_UNIQUE_PAUSEDETECT ((uint32_t)0x00000000U) /*!< only the unique multicast address for pause frame which is specified in IEEE802.3 can be detected */ 1138 1139 #define ENET_RX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_RFCEN /*!< enable decoding function for the received pause frame and process it */ 1140 #define ENET_RX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< decode function for pause frame is disabled */ 1141 #define ENET_RX_FLOWCONTROL ENET_MAC_FCTL_RFCEN /*!< decoding function for the received pause frame and process it */ 1142 1143 #define ENET_TX_FLOWCONTROL_ENABLE ENET_MAC_FCTL_TFCEN /*!< enable the flow control operation in the MAC */ 1144 #define ENET_TX_FLOWCONTROL_DISABLE ((uint32_t)0x00000000U) /*!< disable the flow control operation in the MAC */ 1145 #define ENET_TX_FLOWCONTROL ENET_MAC_FCTL_TFCEN /*!< the flow control operation in the MAC */ 1146 1147 #define ENET_BACK_PRESSURE_ENABLE ENET_MAC_FCTL_FLCBBKPA /*!< enable the back pressure operation in the MAC */ 1148 #define ENET_BACK_PRESSURE_DISABLE ((uint32_t)0x00000000U) /*!< disable the back pressure operation in the MAC */ 1149 #define ENET_BACK_PRESSURE ENET_MAC_FCTL_FLCBBKPA /*!< the back pressure operation in the MAC */ 1150 1151 #define MAC_FCTL_PTM(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) /*!< write value to ENET_MAC_FCTL_PTM bit field */ 1152 /* mac_vlt register value */ 1153 #define MAC_VLT_VLTI(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_VLT_VLTI bit field */ 1154 1155 #define ENET_VLANTAGCOMPARISON_12BIT ENET_MAC_VLT_VLTC /*!< only low 12 bits of the VLAN tag are used for comparison */ 1156 #define ENET_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U) /*!< all 16 bits of the VLAN tag are used for comparison */ 1157 1158 /* mac_wum register value */ 1159 #define ENET_WUM_FLAG_WUFFRPR ENET_MAC_WUM_WUFFRPR /*!< wakeup frame filter register poniter reset */ 1160 #define ENET_WUM_FLAG_WUFR ENET_MAC_WUM_WUFR /*!< wakeup frame received */ 1161 #define ENET_WUM_FLAG_MPKR ENET_MAC_WUM_MPKR /*!< magic packet received */ 1162 #define ENET_WUM_POWER_DOWN ENET_MAC_WUM_PWD /*!< power down mode */ 1163 #define ENET_WUM_MAGIC_PACKET_FRAME ENET_MAC_WUM_MPEN /*!< enable a wakeup event due to magic packet reception */ 1164 #define ENET_WUM_WAKE_UP_FRAME ENET_MAC_WUM_WFEN /*!< enable a wakeup event due to wakeup frame reception */ 1165 #define ENET_WUM_GLOBAL_UNICAST ENET_MAC_WUM_GU /*!< any received unicast frame passed filter is considered to be a wakeup frame */ 1166 1167 /* mac_dbg register value */ 1168 #define ENET_MAC_RECEIVER_NOT_IDLE ENET_MAC_DBG_MRNI /*!< MAC receiver is not in idle state */ 1169 #define ENET_RX_ASYNCHRONOUS_FIFO_STATE ENET_MAC_DBG_RXAFS /*!< Rx asynchronous FIFO status */ 1170 #define ENET_RXFIFO_WRITING ENET_MAC_DBG_RXFW /*!< RxFIFO is doing write operation */ 1171 #define ENET_RXFIFO_READ_STATUS ENET_MAC_DBG_RXFRS /*!< RxFIFO read operation status */ 1172 #define ENET_RXFIFO_STATE ENET_MAC_DBG_RXFS /*!< RxFIFO state */ 1173 #define ENET_MAC_TRANSMITTER_NOT_IDLE ENET_MAC_DBG_MTNI /*!< MAC transmitter is not in idle state */ 1174 #define ENET_MAC_TRANSMITTER_STATUS ENET_MAC_DBG_SOMT /*!< status of MAC transmitter */ 1175 #define ENET_PAUSE_CONDITION_STATUS ENET_MAC_DBG_PCS /*!< pause condition status */ 1176 #define ENET_TXFIFO_READ_STATUS ENET_MAC_DBG_TXFRS /*!< TxFIFO read operation status */ 1177 #define ENET_TXFIFO_WRITING ENET_MAC_DBG_TXFW /*!< TxFIFO is doing write operation */ 1178 #define ENET_TXFIFO_NOT_EMPTY ENET_MAC_DBG_TXFNE /*!< TxFIFO is not empty */ 1179 #define ENET_TXFIFO_FULL ENET_MAC_DBG_TXFF /*!< TxFIFO is full */ 1180 1181 #define GET_MAC_DBG_RXAFS(regval) GET_BITS((regval),1,2) /*!< get value of ENET_MAC_DBG_RXAFS bit field */ 1182 1183 #define GET_MAC_DBG_RXFRS(regval) GET_BITS((regval),5,6) /*!< get value of ENET_MAC_DBG_RXFRS bit field */ 1184 1185 #define GET_MAC_DBG_RXFS(regval) GET_BITS((regval),8,9) /*!< get value of ENET_MAC_DBG_RXFS bit field */ 1186 1187 #define GET_MAC_DBG_SOMT(regval) GET_BITS((regval),17,18) /*!< get value of ENET_MAC_DBG_SOMT bit field */ 1188 1189 #define GET_MAC_DBG_TXFRS(regval) GET_BITS((regval),20,21) /*!< get value of ENET_MAC_DBG_TXFRS bit field */ 1190 1191 /* mac_addr0h register value */ 1192 #define MAC_ADDR0H_ADDR0H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDR0H_ADDR0H bit field */ 1193 1194 /* mac_addrxh register value, x = 1,2,3 */ 1195 #define MAC_ADDR123H_ADDR123H(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_MAC_ADDRxH_ADDRxH(x=1,2,3) bit field */ 1196 1197 #define ENET_ADDRESS_MASK_BYTE0 BIT(24) /*!< low register bits [7:0] */ 1198 #define ENET_ADDRESS_MASK_BYTE1 BIT(25) /*!< low register bits [15:8] */ 1199 #define ENET_ADDRESS_MASK_BYTE2 BIT(26) /*!< low register bits [23:16] */ 1200 #define ENET_ADDRESS_MASK_BYTE3 BIT(27) /*!< low register bits [31:24] */ 1201 #define ENET_ADDRESS_MASK_BYTE4 BIT(28) /*!< high register bits [7:0] */ 1202 #define ENET_ADDRESS_MASK_BYTE5 BIT(29) /*!< high register bits [15:8] */ 1203 1204 #define ENET_ADDRESS_FILTER_SA BIT(30) /*!< use MAC address[47:0] is to compare with the SA fields of the received frame */ 1205 #define ENET_ADDRESS_FILTER_DA ((uint32_t)0x00000000) /*!< use MAC address[47:0] is to compare with the DA fields of the received frame */ 1206 1207 /* mac_fcth register value */ 1208 #define MAC_FCTH_RFA(regval) ((BITS(0,2) & ((uint32_t)(regval) << 0)) << 8) /*!< write value to ENET_MAC_FCTH_RFA bit field */ 1209 #define ENET_ACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFA(0) /*!< threshold level is 256 bytes */ 1210 #define ENET_ACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFA(1) /*!< threshold level is 512 bytes */ 1211 #define ENET_ACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFA(2) /*!< threshold level is 768 bytes */ 1212 #define ENET_ACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFA(3) /*!< threshold level is 1024 bytes */ 1213 #define ENET_ACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFA(4) /*!< threshold level is 1280 bytes */ 1214 #define ENET_ACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFA(5) /*!< threshold level is 1536 bytes */ 1215 #define ENET_ACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFA(6) /*!< threshold level is 1792 bytes */ 1216 1217 #define MAC_FCTH_RFD(regval) ((BITS(4,6) & ((uint32_t)(regval) << 4)) << 8) /*!< write value to ENET_MAC_FCTH_RFD bit field */ 1218 #define ENET_DEACTIVE_THRESHOLD_256BYTES MAC_FCTH_RFD(0) /*!< threshold level is 256 bytes */ 1219 #define ENET_DEACTIVE_THRESHOLD_512BYTES MAC_FCTH_RFD(1) /*!< threshold level is 512 bytes */ 1220 #define ENET_DEACTIVE_THRESHOLD_768BYTES MAC_FCTH_RFD(2) /*!< threshold level is 768 bytes */ 1221 #define ENET_DEACTIVE_THRESHOLD_1024BYTES MAC_FCTH_RFD(3) /*!< threshold level is 1024 bytes */ 1222 #define ENET_DEACTIVE_THRESHOLD_1280BYTES MAC_FCTH_RFD(4) /*!< threshold level is 1280 bytes */ 1223 #define ENET_DEACTIVE_THRESHOLD_1536BYTES MAC_FCTH_RFD(5) /*!< threshold level is 1536 bytes */ 1224 #define ENET_DEACTIVE_THRESHOLD_1792BYTES MAC_FCTH_RFD(6) /*!< threshold level is 1792 bytes */ 1225 1226 /* msc_ctl register value */ 1227 #define ENET_MSC_COUNTER_STOP_ROLLOVER ENET_MSC_CTL_CTSR /*!< counter stop rollover */ 1228 #define ENET_MSC_RESET_ON_READ ENET_MSC_CTL_RTOR /*!< reset on read */ 1229 #define ENET_MSC_COUNTERS_FREEZE ENET_MSC_CTL_MCFZ /*!< MSC counter freeze */ 1230 1231 /* ptp_tsctl register value */ 1232 #define ENET_RXTX_TIMESTAMP ENET_PTP_TSCTL_TMSEN /*!< enable timestamp function for transmit and receive frames */ 1233 #define ENET_PTP_TIMESTAMP_INT ENET_PTP_TSCTL_TMSITEN /*!< timestamp interrupt trigger enable */ 1234 #define ENET_ALL_RX_TIMESTAMP ENET_PTP_TSCTL_ARFSEN /*!< all received frames are taken snapshot */ 1235 #define ENET_NONTYPE_FRAME_SNAPSHOT ENET_PTP_TSCTL_ESEN /*!< take snapshot when received non type frame */ 1236 #define ENET_IPV6_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP6SEN /*!< take snapshot for IPv6 frame */ 1237 #define ENET_IPV4_FRAME_SNAPSHOT ENET_PTP_TSCTL_IP4SEN /*!< take snapshot for IPv4 frame */ 1238 #define ENET_PTP_FRAME_USE_MACADDRESS_FILTER ENET_PTP_TSCTL_MAFEN /*!< enable MAC address1-3 to filter the PTP frame */ 1239 1240 /* ptp_ssinc register value */ 1241 #define PTP_SSINC_STMSSI(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_SSINC_STMSSI bit field */ 1242 1243 /* ptp_tsl register value */ 1244 #define GET_PTP_TSL_STMSS(regval) GET_BITS((uint32_t)(regval),0,30) /*!< get value of ENET_PTP_TSL_STMSS bit field */ 1245 1246 #define ENET_PTP_TIME_POSITIVE ((uint32_t)0x00000000) /*!< time value is positive */ 1247 #define ENET_PTP_TIME_NEGATIVE ENET_PTP_TSL_STS /*!< time value is negative */ 1248 1249 #define GET_PTP_TSL_STS(regval) (((regval) & BIT(31)) >> (31U)) /*!< get value of ENET_PTP_TSL_STS bit field */ 1250 1251 /* ptp_tsul register value */ 1252 #define PTP_TSUL_TMSUSS(regval) (BITS(0,30) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_TSUL_TMSUSS bit field */ 1253 1254 #define ENET_PTP_ADD_TO_TIME ((uint32_t)0x00000000) /*!< timestamp update value is added to system time */ 1255 #define ENET_PTP_SUBSTRACT_FROM_TIME ENET_PTP_TSUL_TMSUPNS /*!< timestamp update value is subtracted from system time */ 1256 1257 /* ptp_ppsctl register value */ 1258 #define PTP_PPSCTL_PPSOFC(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_PTP_PPSCTL_PPSOFC bit field */ 1259 #define ENET_PPSOFC_1HZ PTP_PPSCTL_PPSOFC(0) /*!< PPS output 1Hz frequency */ 1260 #define ENET_PPSOFC_2HZ PTP_PPSCTL_PPSOFC(1) /*!< PPS output 2Hz frequency */ 1261 #define ENET_PPSOFC_4HZ PTP_PPSCTL_PPSOFC(2) /*!< PPS output 4Hz frequency */ 1262 #define ENET_PPSOFC_8HZ PTP_PPSCTL_PPSOFC(3) /*!< PPS output 8Hz frequency */ 1263 #define ENET_PPSOFC_16HZ PTP_PPSCTL_PPSOFC(4) /*!< PPS output 16Hz frequency */ 1264 #define ENET_PPSOFC_32HZ PTP_PPSCTL_PPSOFC(5) /*!< PPS output 32Hz frequency */ 1265 #define ENET_PPSOFC_64HZ PTP_PPSCTL_PPSOFC(6) /*!< PPS output 64Hz frequency */ 1266 #define ENET_PPSOFC_128HZ PTP_PPSCTL_PPSOFC(7) /*!< PPS output 128Hz frequency */ 1267 #define ENET_PPSOFC_256HZ PTP_PPSCTL_PPSOFC(8) /*!< PPS output 256Hz frequency */ 1268 #define ENET_PPSOFC_512HZ PTP_PPSCTL_PPSOFC(9) /*!< PPS output 512Hz frequency */ 1269 #define ENET_PPSOFC_1024HZ PTP_PPSCTL_PPSOFC(10) /*!< PPS output 1024Hz frequency */ 1270 #define ENET_PPSOFC_2048HZ PTP_PPSCTL_PPSOFC(11) /*!< PPS output 2048Hz frequency */ 1271 #define ENET_PPSOFC_4096HZ PTP_PPSCTL_PPSOFC(12) /*!< PPS output 4096Hz frequency */ 1272 #define ENET_PPSOFC_8192HZ PTP_PPSCTL_PPSOFC(13) /*!< PPS output 8192Hz frequency */ 1273 #define ENET_PPSOFC_16384HZ PTP_PPSCTL_PPSOFC(14) /*!< PPS output 16384Hz frequency */ 1274 #define ENET_PPSOFC_32768HZ PTP_PPSCTL_PPSOFC(15) /*!< PPS output 32768Hz frequency */ 1275 1276 /* dma_bctl register value */ 1277 #define DMA_BCTL_DPSL(regval) (BITS(2,6) & ((uint32_t)(regval) << 2)) /*!< write value to ENET_DMA_BCTL_DPSL bit field */ 1278 #define GET_DMA_BCTL_DPSL(regval) GET_BITS((regval),2,6) /*!< get value of ENET_DMA_BCTL_DPSL bit field */ 1279 1280 #define ENET_ENHANCED_DESCRIPTOR ENET_DMA_BCTL_DFM /*!< enhanced mode descriptor */ 1281 #define ENET_NORMAL_DESCRIPTOR ((uint32_t)0x00000000) /*!< normal mode descriptor */ 1282 1283 #define DMA_BCTL_PGBL(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) /*!< write value to ENET_DMA_BCTL_PGBL bit field */ 1284 #define ENET_PGBL_1BEAT DMA_BCTL_PGBL(1) /*!< maximum number of beats is 1 */ 1285 #define ENET_PGBL_2BEAT DMA_BCTL_PGBL(2) /*!< maximum number of beats is 2 */ 1286 #define ENET_PGBL_4BEAT DMA_BCTL_PGBL(4) /*!< maximum number of beats is 4 */ 1287 #define ENET_PGBL_8BEAT DMA_BCTL_PGBL(8) /*!< maximum number of beats is 8 */ 1288 #define ENET_PGBL_16BEAT DMA_BCTL_PGBL(16) /*!< maximum number of beats is 16 */ 1289 #define ENET_PGBL_32BEAT DMA_BCTL_PGBL(32) /*!< maximum number of beats is 32 */ 1290 #define ENET_PGBL_4xPGBL_4BEAT (DMA_BCTL_PGBL(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 4 */ 1291 #define ENET_PGBL_4xPGBL_8BEAT (DMA_BCTL_PGBL(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 8 */ 1292 #define ENET_PGBL_4xPGBL_16BEAT (DMA_BCTL_PGBL(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 16 */ 1293 #define ENET_PGBL_4xPGBL_32BEAT (DMA_BCTL_PGBL(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 32 */ 1294 #define ENET_PGBL_4xPGBL_64BEAT (DMA_BCTL_PGBL(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 64 */ 1295 #define ENET_PGBL_4xPGBL_128BEAT (DMA_BCTL_PGBL(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats is 128 */ 1296 1297 #define DMA_BCTL_RTPR(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_BCTL_RTPR bit field */ 1298 #define ENET_ARBITRATION_RXTX_1_1 DMA_BCTL_RTPR(0) /*!< receive and transmit priority ratio is 1:1*/ 1299 #define ENET_ARBITRATION_RXTX_2_1 DMA_BCTL_RTPR(1) /*!< receive and transmit priority ratio is 2:1*/ 1300 #define ENET_ARBITRATION_RXTX_3_1 DMA_BCTL_RTPR(2) /*!< receive and transmit priority ratio is 3:1 */ 1301 #define ENET_ARBITRATION_RXTX_4_1 DMA_BCTL_RTPR(3) /*!< receive and transmit priority ratio is 4:1 */ 1302 #define ENET_ARBITRATION_RXPRIORTX ENET_DMA_BCTL_DAB /*!< RxDMA has higher priority than TxDMA */ 1303 1304 #define ENET_FIXED_BURST_ENABLE ENET_DMA_BCTL_FB /*!< AHB can only use SINGLE/INCR4/INCR8/INCR16 during start of normal burst transfers */ 1305 #define ENET_FIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB can use SINGLE/INCR burst transfer operations */ 1306 1307 #define DMA_BCTL_RXDP(regval) (BITS(17,22) & ((uint32_t)(regval) << 17)) /*!< write value to ENET_DMA_BCTL_RXDP bit field */ 1308 #define ENET_RXDP_1BEAT DMA_BCTL_RXDP(1) /*!< maximum number of beats 1 */ 1309 #define ENET_RXDP_2BEAT DMA_BCTL_RXDP(2) /*!< maximum number of beats 2 */ 1310 #define ENET_RXDP_4BEAT DMA_BCTL_RXDP(4) /*!< maximum number of beats 4 */ 1311 #define ENET_RXDP_8BEAT DMA_BCTL_RXDP(8) /*!< maximum number of beats 8 */ 1312 #define ENET_RXDP_16BEAT DMA_BCTL_RXDP(16) /*!< maximum number of beats 16 */ 1313 #define ENET_RXDP_32BEAT DMA_BCTL_RXDP(32) /*!< maximum number of beats 32 */ 1314 #define ENET_RXDP_4xPGBL_4BEAT (DMA_BCTL_RXDP(1)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 4 */ 1315 #define ENET_RXDP_4xPGBL_8BEAT (DMA_BCTL_RXDP(2)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 8 */ 1316 #define ENET_RXDP_4xPGBL_16BEAT (DMA_BCTL_RXDP(4)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 16 */ 1317 #define ENET_RXDP_4xPGBL_32BEAT (DMA_BCTL_RXDP(8)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 32 */ 1318 #define ENET_RXDP_4xPGBL_64BEAT (DMA_BCTL_RXDP(16)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 64 */ 1319 #define ENET_RXDP_4xPGBL_128BEAT (DMA_BCTL_RXDP(32)|ENET_DMA_BCTL_FPBL) /*!< maximum number of beats 128 */ 1320 1321 #define ENET_RXTX_DIFFERENT_PGBL ENET_DMA_BCTL_UIP /*!< RxDMA uses the RXDP[5:0], while TxDMA uses the PGBL[5:0] */ 1322 #define ENET_RXTX_SAME_PGBL ((uint32_t)0x00000000) /*!< RxDMA/TxDMA uses PGBL[5:0] */ 1323 1324 #define ENET_ADDRESS_ALIGN_ENABLE ENET_DMA_BCTL_AA /*!< enabled address-aligned */ 1325 #define ENET_ADDRESS_ALIGN_DISABLE ((uint32_t)0x00000000) /*!< disable address-aligned */ 1326 1327 #define ENET_MIXED_BURST_ENABLE ENET_DMA_BCTL_MB /*!< AHB master interface transfer burst length greater than 16 with INCR */ 1328 #define ENET_MIXED_BURST_DISABLE ((uint32_t)0x00000000) /*!< AHB master interface only transfer fixed burst length with 16 and below */ 1329 1330 /* dma_stat register value */ 1331 #define GET_DMA_STAT_RP(regval) GET_BITS((uint32_t)(regval),17,19) /*!< get value of ENET_DMA_STAT_RP bit field */ 1332 #define ENET_RX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop rx command issued */ 1333 #define ENET_RX_STATE_FETCHING BIT(17) /*!< fetching the Rx descriptor */ 1334 #define ENET_RX_STATE_WAITING (BIT(17)|BIT(18)) /*!< waiting for receive packet */ 1335 #define ENET_RX_STATE_SUSPENDED BIT(19) /*!< Rx descriptor unavailable */ 1336 #define ENET_RX_STATE_CLOSING (BIT(17)|BIT(19)) /*!< closing receive descriptor */ 1337 #define ENET_RX_STATE_QUEUING ENET_DMA_STAT_RP /*!< transferring the receive packet data from recevie buffer to host memory */ 1338 1339 #define GET_DMA_STAT_TP(regval) GET_BITS((uint32_t)(regval),20,22) /*!< get value of ENET_DMA_STAT_TP bit field */ 1340 #define ENET_TX_STATE_STOPPED ((uint32_t)0x00000000) /*!< reset or stop Tx Command issued */ 1341 #define ENET_TX_STATE_FETCHING BIT(20) /*!< fetching the Tx descriptor */ 1342 #define ENET_TX_STATE_WAITING BIT(21) /*!< waiting for status */ 1343 #define ENET_TX_STATE_READING (BIT(20)|BIT(21)) /*!< reading the data from host memory buffer and queuing it to transmit buffer */ 1344 #define ENET_TX_STATE_SUSPENDED (BIT(21)|BIT(22)) /*!< Tx descriptor unavailabe or transmit buffer underflow */ 1345 #define ENET_TX_STATE_CLOSING ENET_DMA_STAT_TP /*!< closing Tx descriptor */ 1346 1347 #define GET_DMA_STAT_EB(regval) GET_BITS((uint32_t)(regval),23,25) /*!< get value of ENET_DMA_STAT_EB bit field */ 1348 #define ENET_ERROR_TXDATA_TRANSFER BIT(23) /*!< error during data transfer by TxDMA or RxDMA */ 1349 #define ENET_ERROR_READ_TRANSFER BIT(24) /*!< error during write transfer or read transfer */ 1350 #define ENET_ERROR_DESC_ACCESS BIT(25) /*!< error during descriptor or buffer access */ 1351 1352 /* dma_ctl register value */ 1353 #define DMA_CTL_RTHC(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) /*!< write value to ENET_DMA_CTL_RTHC bit field */ 1354 #define ENET_RX_THRESHOLD_64BYTES DMA_CTL_RTHC(0) /*!< threshold level is 64 Bytes */ 1355 #define ENET_RX_THRESHOLD_32BYTES DMA_CTL_RTHC(1) /*!< threshold level is 32 Bytes */ 1356 #define ENET_RX_THRESHOLD_96BYTES DMA_CTL_RTHC(2) /*!< threshold level is 96 Bytes */ 1357 #define ENET_RX_THRESHOLD_128BYTES DMA_CTL_RTHC(3) /*!< threshold level is 128 Bytes */ 1358 1359 #define DMA_CTL_TTHC(regval) (BITS(14,16) & ((uint32_t)(regval) << 14)) /*!< write value to ENET_DMA_CTL_TTHC bit field */ 1360 #define ENET_TX_THRESHOLD_64BYTES DMA_CTL_TTHC(0) /*!< threshold level is 64 Bytes */ 1361 #define ENET_TX_THRESHOLD_128BYTES DMA_CTL_TTHC(1) /*!< threshold level is 128 Bytes */ 1362 #define ENET_TX_THRESHOLD_192BYTES DMA_CTL_TTHC(2) /*!< threshold level is 192 Bytes */ 1363 #define ENET_TX_THRESHOLD_256BYTES DMA_CTL_TTHC(3) /*!< threshold level is 256 Bytes */ 1364 #define ENET_TX_THRESHOLD_40BYTES DMA_CTL_TTHC(4) /*!< threshold level is 40 Bytes */ 1365 #define ENET_TX_THRESHOLD_32BYTES DMA_CTL_TTHC(5) /*!< threshold level is 32 Bytes */ 1366 #define ENET_TX_THRESHOLD_24BYTES DMA_CTL_TTHC(6) /*!< threshold level is 24 Bytes */ 1367 #define ENET_TX_THRESHOLD_16BYTES DMA_CTL_TTHC(7) /*!< threshold level is 16 Bytes */ 1368 1369 #define ENET_TCPIP_CKSUMERROR_ACCEPT ENET_DMA_CTL_DTCERFD /*!< Rx frame with only payload error but no other errors will not be dropped */ 1370 #define ENET_TCPIP_CKSUMERROR_DROP ((uint32_t)0x00000000) /*!< all error frames will be dropped when FERF = 0 */ 1371 1372 #define ENET_RX_MODE_STOREFORWARD ENET_DMA_CTL_RSFD /*!< RxFIFO operates in store-and-forward mode */ 1373 #define ENET_RX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< RxFIFO operates in cut-through mode */ 1374 1375 #define ENET_FLUSH_RXFRAME_ENABLE ((uint32_t)0x00000000) /*!< RxDMA flushes all frames */ 1376 #define ENET_FLUSH_RXFRAME_DISABLE ENET_DMA_CTL_DAFRF /*!< RxDMA does not flush any frames */ 1377 #define ENET_NO_FLUSH_RXFRAME ENET_DMA_CTL_DAFRF /*!< RxDMA flushes frames function */ 1378 1379 #define ENET_TX_MODE_STOREFORWARD ENET_DMA_CTL_TSFD /*!< TxFIFO operates in store-and-forward mode */ 1380 #define ENET_TX_MODE_CUTTHROUGH ((uint32_t)0x00000000) /*!< TxFIFO operates in cut-through mode */ 1381 1382 #define ENET_FORWARD_ERRFRAMES_ENABLE (ENET_DMA_CTL_FERF << 2) /*!< all frame received with error except runt error are forwarded to memory */ 1383 #define ENET_FORWARD_ERRFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drop error frame */ 1384 #define ENET_FORWARD_ERRFRAMES (ENET_DMA_CTL_FERF << 2) /*!< the function that all frame received with error except runt error are forwarded to memory */ 1385 1386 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_ENABLE (ENET_DMA_CTL_FUF << 2) /*!< forward undersized good frames */ 1387 #define ENET_FORWARD_UNDERSZ_GOODFRAMES_DISABLE ((uint32_t)0x00000000) /*!< RxFIFO drops all frames whose length is less than 64 bytes */ 1388 #define ENET_FORWARD_UNDERSZ_GOODFRAMES (ENET_DMA_CTL_FUF << 2) /*!< the function that forwarding undersized good frames */ 1389 1390 #define ENET_SECONDFRAME_OPT_ENABLE ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame mode enable*/ 1391 #define ENET_SECONDFRAME_OPT_DISABLE ((uint32_t)0x00000000) /*!< TxDMA controller operate on second frame mode disable */ 1392 #define ENET_SECONDFRAME_OPT ENET_DMA_CTL_OSF /*!< TxDMA controller operate on second frame function */ 1393 /* dma_mfbocnt register value */ 1394 #define GET_DMA_MFBOCNT_MSFC(regval) GET_BITS((regval),0,15) /*!< get value of ENET_DMA_MFBOCNT_MSFC bit field */ 1395 1396 #define GET_DMA_MFBOCNT_MSFA(regval) GET_BITS((regval),17,27) /*!< get value of ENET_DMA_MFBOCNT_MSFA bit field */ 1397 1398 /* dma_rswdc register value */ 1399 #define DMA_RSWDC_WDCFRS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) /*!< write value to ENET_DMA_RSWDC_WDCFRS bit field */ 1400 1401 /* dma tx descriptor tdes0 register value */ 1402 #define TDES0_CONT(regval) (BITS(3,6) & ((uint32_t)(regval) << 3)) /*!< write value to ENET DMA TDES0 CONT bit field */ 1403 #define GET_TDES0_COCNT(regval) GET_BITS((regval),3,6) /*!< get value of ENET DMA TDES0 CONT bit field */ 1404 1405 #define TDES0_CM(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) /*!< write value to ENET DMA TDES0 CM bit field */ 1406 #define ENET_CHECKSUM_DISABLE TDES0_CM(0) /*!< checksum insertion disabled */ 1407 #define ENET_CHECKSUM_IPV4HEADER TDES0_CM(1) /*!< only IP header checksum calculation and insertion are enabled */ 1408 #define ENET_CHECKSUM_TCPUDPICMP_SEGMENT TDES0_CM(2) /*!< TCP/UDP/ICMP checksum insertion calculated but pseudo-header */ 1409 #define ENET_CHECKSUM_TCPUDPICMP_FULL TDES0_CM(3) /*!< TCP/UDP/ICMP checksum insertion fully calculated */ 1410 1411 /* dma tx descriptor tdes1 register value */ 1412 #define TDES1_TB1S(regval) (BITS(0,12) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA TDES1 TB1S bit field */ 1413 1414 #define TDES1_TB2S(regval) (BITS(16,28) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA TDES1 TB2S bit field */ 1415 1416 /* dma rx descriptor rdes0 register value */ 1417 #define RDES0_FRML(regval) (BITS(16,29) & ((uint32_t)(regval) << 16)) /*!< write value to ENET DMA RDES0 FRML bit field */ 1418 #define GET_RDES0_FRML(regval) GET_BITS((regval),16,29) /*!< get value of ENET DMA RDES0 FRML bit field */ 1419 1420 /* dma rx descriptor rdes1 register value */ 1421 #define ENET_RECEIVE_COMPLETE_INT_ENABLE ((uint32_t)0x00000000U) /*!< RS bit immediately set after Rx completed */ 1422 #define ENET_RECEIVE_COMPLETE_INT_DISABLE ENET_RDES1_DINTC /*!< RS bit not immediately set after Rx completed */ 1423 1424 #define GET_RDES1_RB1S(regval) GET_BITS((regval),0,12) /*!< get value of ENET DMA RDES1 RB1S bit field */ 1425 1426 #define GET_RDES1_RB2S(regval) GET_BITS((regval),16,28) /*!< get value of ENET DMA RDES1 RB2S bit field */ 1427 1428 /* dma rx descriptor rdes4 register value */ 1429 #define RDES4_IPPLDT(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) /*!< write value to ENET DMA RDES4 IPPLDT bit field */ 1430 #define GET_RDES4_IPPLDT(regval) GET_BITS((regval),0,2) /*!< get value of ENET DMA RDES4 IPPLDT bit field */ 1431 1432 #define RDES4_PTPMT(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) /*!< write value to ENET DMA RDES4 PTPMT bit field */ 1433 #define GET_RDES4_PTPMT(regval) GET_BITS((regval),8,11) /*!< get value of ENET DMA RDES4 PTPMT bit field */ 1434 1435 /* ENET register mask value */ 1436 #define MAC_CFG_MASK ((uint32_t)0xFD30810FU) /*!< ENET_MAC_CFG register mask */ 1437 #define MAC_FCTL_MASK ((uint32_t)0x0000FF41U) /*!< ENET_MAC_FCTL register mask */ 1438 #define DMA_CTL_MASK ((uint32_t)0xF8DE3F23U) /*!< ENET_DMA_CTL register mask */ 1439 #define DMA_BCTL_MASK ((uint32_t)0xF800007DU) /*!< ENET_DMA_BCTL register mask */ 1440 #define ENET_MSC_PRESET_MASK (~(ENET_MSC_CTL_PMC | ENET_MSC_CTL_AFHPM)) /*!< ENET_MSC_CTL preset mask */ 1441 1442 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE 1443 #define ETH_DMATXDESC_SIZE ((uint32_t)0x00000020U) /*!< TxDMA enhanced descriptor size */ 1444 #define ETH_DMARXDESC_SIZE ((uint32_t)0x00000020U) /*!< RxDMA enhanced descriptor size */ 1445 #else 1446 #define ETH_DMATXDESC_SIZE ((uint32_t)0x00000010U) /*!< TxDMA descriptor size */ 1447 #define ETH_DMARXDESC_SIZE ((uint32_t)0x00000010U) /*!< RxDMA descriptor size */ 1448 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ 1449 1450 /* ENET remote wake-up frame register length */ 1451 #define ETH_WAKEUP_REGISTER_LENGTH 8U /*!< remote wake-up frame register length */ 1452 1453 /* ENET frame size */ 1454 #define ENET_MAX_FRAME_SIZE 1524U /*!< header + frame_extra + payload + CRC */ 1455 1456 /* ENET delay timeout */ 1457 #define ENET_DELAY_TO ((uint32_t)0x0004FFFFU) /*!< ENET delay timeout */ 1458 #define ENET_RESET_TO ((uint32_t)0x000004FFU) /*!< ENET reset timeout */ 1459 1460 1461 1462 /* function declarations */ 1463 /* main function */ 1464 /* deinitialize the ENET, and reset structure parameters for ENET initialization */ 1465 void enet_deinit(void); 1466 /* configure the parameters which are usually less cared for initialization */ 1467 void enet_initpara_config(enet_option_enum option, uint32_t para); 1468 /* initialize ENET peripheral with generally concerned parameters and the less cared parameters */ 1469 ErrStatus enet_init(enet_mediamode_enum mediamode, enet_chksumconf_enum checksum, enet_frmrecept_enum recept); 1470 /* reset all core internal registers located in CLK_TX and CLK_RX */ 1471 ErrStatus enet_software_reset(void); 1472 /* check receive frame valid and return frame size */ 1473 uint32_t enet_rxframe_size_get(void); 1474 /* initialize the dma tx/rx descriptors's parameters in chain mode */ 1475 void enet_descriptors_chain_init(enet_dmadirection_enum direction); 1476 /* initialize the dma tx/rx descriptors's parameters in ring mode */ 1477 void enet_descriptors_ring_init(enet_dmadirection_enum direction); 1478 /* handle current received frame data to application buffer */ 1479 ErrStatus enet_frame_receive(uint8_t *buffer, uint32_t bufsize); 1480 /* handle current received frame but without data copy to application buffer */ 1481 #define ENET_NOCOPY_FRAME_RECEIVE() enet_frame_receive(NULL, 0U) 1482 /* handle application buffer data to transmit it */ 1483 ErrStatus enet_frame_transmit(uint8_t *buffer, uint32_t length); 1484 /* handle current transmit frame but without data copy from application buffer */ 1485 #define ENET_NOCOPY_FRAME_TRANSMIT(len) enet_frame_transmit(NULL, (len)) 1486 /* configure the transmit IP frame checksum offload calculation and insertion */ 1487 void enet_transmit_checksum_config(enet_descriptors_struct *desc, uint32_t checksum); 1488 /* ENET Tx and Rx function enable (include MAC and DMA module) */ 1489 void enet_enable(void); 1490 /* ENET Tx and Rx function disable (include MAC and DMA module) */ 1491 void enet_disable(void); 1492 /* configure MAC address */ 1493 void enet_mac_address_set(enet_macaddress_enum mac_addr, uint8_t paddr[]); 1494 /* get MAC address */ 1495 void enet_mac_address_get(enet_macaddress_enum mac_addr, uint8_t paddr[]); 1496 1497 /* get the ENET MAC/MSC/PTP/DMA status flag */ 1498 FlagStatus enet_flag_get(enet_flag_enum enet_flag); 1499 /* clear the ENET DMA status flag */ 1500 void enet_flag_clear(enet_flag_clear_enum enet_flag); 1501 /* enable ENET MAC/MSC/DMA interrupt */ 1502 void enet_interrupt_enable(enet_int_enum enet_int); 1503 /* disable ENET MAC/MSC/DMA interrupt */ 1504 void enet_interrupt_disable(enet_int_enum enet_int); 1505 /* get ENET MAC/MSC/DMA interrupt flag */ 1506 FlagStatus enet_interrupt_flag_get(enet_int_flag_enum int_flag); 1507 /* clear ENET DMA interrupt flag */ 1508 void enet_interrupt_flag_clear(enet_int_flag_clear_enum int_flag_clear); 1509 1510 /* MAC function */ 1511 /* ENET Tx function enable (include MAC and DMA module) */ 1512 void enet_tx_enable(void); 1513 /* ENET Tx function disable (include MAC and DMA module) */ 1514 void enet_tx_disable(void); 1515 /* ENET Rx function enable (include MAC and DMA module) */ 1516 void enet_rx_enable(void); 1517 /* ENET Rx function disable (include MAC and DMA module) */ 1518 void enet_rx_disable(void); 1519 /* put registers value into the application buffer */ 1520 void enet_registers_get(enet_registers_type_enum type, uint32_t *preg, uint32_t num); 1521 /* get the enet debug status from the debug register */ 1522 uint32_t enet_debug_status_get(uint32_t mac_debug); 1523 /* enable the MAC address filter */ 1524 void enet_address_filter_enable(enet_macaddress_enum mac_addr); 1525 /* disable the MAC address filter */ 1526 void enet_address_filter_disable(enet_macaddress_enum mac_addr); 1527 /* configure the MAC address filter */ 1528 void enet_address_filter_config(enet_macaddress_enum mac_addr, uint32_t addr_mask, uint32_t filter_type); 1529 /* PHY interface configuration (configure SMI clock and reset PHY chip) */ 1530 ErrStatus enet_phy_config(void); 1531 /* write to/read from a PHY register */ 1532 ErrStatus enet_phy_write_read(enet_phydirection_enum direction, uint16_t phy_address, uint16_t phy_reg, uint16_t *pvalue); 1533 /* enable the loopback function of phy chip */ 1534 ErrStatus enet_phyloopback_enable(void); 1535 /* disable the loopback function of phy chip */ 1536 ErrStatus enet_phyloopback_disable(void); 1537 /* enable ENET forward feature */ 1538 void enet_forward_feature_enable(uint32_t feature); 1539 /* disable ENET forward feature */ 1540 void enet_forward_feature_disable(uint32_t feature); 1541 /* enable ENET fliter feature */ 1542 void enet_fliter_feature_enable(uint32_t feature); 1543 /* disable ENET fliter feature */ 1544 void enet_fliter_feature_disable(uint32_t feature); 1545 1546 /* flow control function */ 1547 /* generate the pause frame, ENET will send pause frame after enable transmit flow control */ 1548 ErrStatus enet_pauseframe_generate(void); 1549 /* configure the pause frame detect type */ 1550 void enet_pauseframe_detect_config(uint32_t detect); 1551 /* configure the pause frame parameters */ 1552 void enet_pauseframe_config(uint32_t pausetime, uint32_t pause_threshold); 1553 /* configure the threshold of the flow control(deactive and active threshold) */ 1554 void enet_flowcontrol_threshold_config(uint32_t deactive, uint32_t active); 1555 /* enable ENET flow control feature */ 1556 void enet_flowcontrol_feature_enable(uint32_t feature); 1557 /* disable ENET flow control feature */ 1558 void enet_flowcontrol_feature_disable(uint32_t feature); 1559 1560 /* DMA function */ 1561 /* get the dma transmit/receive process state */ 1562 uint32_t enet_dmaprocess_state_get(enet_dmadirection_enum direction); 1563 /* poll the dma transmission/reception enable */ 1564 void enet_dmaprocess_resume(enet_dmadirection_enum direction); 1565 /* check and recover the Rx process */ 1566 void enet_rxprocess_check_recovery(void); 1567 /* flush the ENET transmit fifo, and wait until the flush operation completes */ 1568 ErrStatus enet_txfifo_flush(void); 1569 /* get the transmit/receive address of current descriptor, or current buffer, or descriptor table */ 1570 uint32_t enet_current_desc_address_get(enet_desc_reg_enum addr_get); 1571 /* get the Tx or Rx descriptor information */ 1572 uint32_t enet_desc_information_get(enet_descriptors_struct *desc, enet_descstate_enum info_get); 1573 /* get the number of missed frames during receiving */ 1574 void enet_missed_frame_counter_get(uint32_t *rxfifo_drop, uint32_t *rxdma_drop); 1575 1576 /* descriptor function */ 1577 /* get the bit flag of ENET dma descriptor */ 1578 FlagStatus enet_desc_flag_get(enet_descriptors_struct *desc, uint32_t desc_flag); 1579 /* set the bit flag of ENET dma tx descriptor */ 1580 void enet_desc_flag_set(enet_descriptors_struct *desc, uint32_t desc_flag); 1581 /* clear the bit flag of ENET dma tx descriptor */ 1582 void enet_desc_flag_clear(enet_descriptors_struct *desc, uint32_t desc_flag); 1583 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will immediately set */ 1584 void enet_rx_desc_immediate_receive_complete_interrupt(enet_descriptors_struct *desc); 1585 /* when receiving the completed, set RS bit in ENET_DMA_STAT register will is set after a configurable delay time */ 1586 void enet_rx_desc_delay_receive_complete_interrupt(enet_descriptors_struct *desc, uint32_t delay_time); 1587 /* drop current receive frame */ 1588 void enet_rxframe_drop(void); 1589 /* enable DMA feature */ 1590 void enet_dma_feature_enable(uint32_t feature); 1591 /* disable DMA feature */ 1592 void enet_dma_feature_disable(uint32_t feature); 1593 1594 1595 /* special enhanced mode function */ 1596 #ifdef SELECT_DESCRIPTORS_ENHANCED_MODE 1597 /* get the bit of extended status flag in ENET DMA descriptor */ 1598 uint32_t enet_rx_desc_enhanced_status_get(enet_descriptors_struct *desc, uint32_t desc_status); 1599 /* configure descriptor to work in enhanced mode */ 1600 void enet_desc_select_enhanced_mode(void); 1601 /* initialize the dma Tx/Rx descriptors's parameters in enhanced chain mode with ptp function */ 1602 void enet_ptp_enhanced_descriptors_chain_init(enet_dmadirection_enum direction); 1603 /* initialize the dma Tx/Rx descriptors's parameters in enhanced ring mode with ptp function */ 1604 void enet_ptp_enhanced_descriptors_ring_init(enet_dmadirection_enum direction); 1605 /* receive a packet data with timestamp values to application buffer, when the DMA is in enhanced mode */ 1606 ErrStatus enet_ptpframe_receive_enhanced_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); 1607 /* handle current received frame but without data copy to application buffer in PTP enhanced mode */ 1608 #define ENET_NOCOPY_PTPFRAME_RECEIVE_ENHANCED_MODE(ptr) enet_ptpframe_receive_enhanced_mode(NULL, 0U, (ptr)) 1609 /* send data with timestamp values in application buffer as a transmit packet, when the DMA is in enhanced mode */ 1610 ErrStatus enet_ptpframe_transmit_enhanced_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); 1611 /* handle current transmit frame but without data copy from application buffer in PTP enhanced mode */ 1612 #define ENET_NOCOPY_PTPFRAME_TRANSMIT_ENHANCED_MODE(len, ptr) enet_ptpframe_transmit_enhanced_mode(NULL, (len), (ptr)) 1613 1614 #else 1615 1616 /* configure descriptor to work in normal mode */ 1617 void enet_desc_select_normal_mode(void); 1618 /* initialize the dma Tx/Rx descriptors's parameters in normal chain mode with ptp function */ 1619 void enet_ptp_normal_descriptors_chain_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); 1620 /* initialize the dma Tx/Rx descriptors's parameters in normal ring mode with ptp function */ 1621 void enet_ptp_normal_descriptors_ring_init(enet_dmadirection_enum direction, enet_descriptors_struct *desc_ptptab); 1622 /* receive a packet data with timestamp values to application buffer, when the DMA is in normal mode */ 1623 ErrStatus enet_ptpframe_receive_normal_mode(uint8_t *buffer, uint32_t bufsize, uint32_t timestamp[]); 1624 /* handle current received frame but without data copy to application buffer in PTP normal mode */ 1625 #define ENET_NOCOPY_PTPFRAME_RECEIVE_NORMAL_MODE(ptr) enet_ptpframe_receive_normal_mode(NULL, 0U, (ptr)) 1626 /* send data with timestamp values in application buffer as a transmit packet, when the DMA is in normal mode */ 1627 ErrStatus enet_ptpframe_transmit_normal_mode(uint8_t *buffer, uint32_t length, uint32_t timestamp[]); 1628 /* handle current transmit frame but without data copy from application buffer in PTP normal mode */ 1629 #define ENET_NOCOPY_PTPFRAME_TRANSMIT_NORMAL_MODE(len, ptr) enet_ptpframe_transmit_normal_mode(NULL, (len), (ptr)) 1630 1631 #endif /* SELECT_DESCRIPTORS_ENHANCED_MODE */ 1632 1633 /* WUM function */ 1634 /* wakeup frame filter register pointer reset */ 1635 void enet_wum_filter_register_pointer_reset(void); 1636 /* set the remote wakeup frame registers */ 1637 void enet_wum_filter_config(uint32_t pdata[]); 1638 /* enable wakeup management features */ 1639 void enet_wum_feature_enable(uint32_t feature); 1640 /* disable wakeup management features */ 1641 void enet_wum_feature_disable(uint32_t feature); 1642 1643 /* MSC function */ 1644 /* reset the MAC statistics counters */ 1645 void enet_msc_counters_reset(void); 1646 /* enable the MAC statistics counter features */ 1647 void enet_msc_feature_enable(uint32_t feature); 1648 /* disable the MAC statistics counter features */ 1649 void enet_msc_feature_disable(uint32_t feature); 1650 /* configure MAC statistics counters preset mode */ 1651 void enet_msc_counters_preset_config(enet_msc_preset_enum mode); 1652 /* get MAC statistics counter */ 1653 uint32_t enet_msc_counters_get(enet_msc_counter_enum counter); 1654 1655 /* PTP function */ 1656 /* enable the PTP features */ 1657 void enet_ptp_feature_enable(uint32_t feature); 1658 /* disable the PTP features */ 1659 void enet_ptp_feature_disable(uint32_t feature); 1660 /* configure the PTP timestamp function */ 1661 ErrStatus enet_ptp_timestamp_function_config(enet_ptp_function_enum func); 1662 /* configure the PTP system time subsecond increment value */ 1663 void enet_ptp_subsecond_increment_config(uint32_t subsecond); 1664 /* adjusting the PTP clock frequency only in fine update mode */ 1665 void enet_ptp_timestamp_addend_config(uint32_t add); 1666 /* initializing or adding/subtracting to second of the PTP system time */ 1667 void enet_ptp_timestamp_update_config(uint32_t sign, uint32_t second, uint32_t subsecond); 1668 /* configure the PTP expected target time */ 1669 void enet_ptp_expected_time_config(uint32_t second, uint32_t nanosecond); 1670 /* get the PTP current system time */ 1671 void enet_ptp_system_time_get(enet_ptp_systime_struct *systime_struct); 1672 /* configure the PPS output frequency */ 1673 void enet_ptp_pps_output_frequency_config(uint32_t freq); 1674 1675 1676 /* internal function */ 1677 /* reset the ENET initpara struct, call it before using enet_initpara_config() */ 1678 void enet_initpara_reset(void); 1679 1680 1681 #endif /* GD32F4XX_ENET_H */ 1682
