1 /*!
2 \file gd32f4xx_dbg.c
3 \brief DBG driver
4
5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
9 */
10
11 /*
12 Copyright (c) 2022, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32f4xx_dbg.h"
39
40 #define DBG_RESET_VAL 0x00000000U
41
42 /*!
43 \brief deinitialize the DBG
44 \param[in] none
45 \param[out] none
46 \retval none
47 */
dbg_deinit(void)48 void dbg_deinit(void)
49 {
50 DBG_CTL0 = DBG_RESET_VAL;
51 DBG_CTL1 = DBG_RESET_VAL;
52 }
53
54 /*!
55 \brief read DBG_ID code register
56 \param[in] none
57 \param[out] none
58 \retval DBG_ID code
59 */
dbg_id_get(void)60 uint32_t dbg_id_get(void)
61 {
62 return DBG_ID;
63 }
64
65 /*!
66 \brief enable low power behavior when the mcu is in debug mode
67 \param[in] dbg_low_power:
68 this parameter can be any combination of the following values:
69 \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
70 \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
71 \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
72 \param[out] none
73 \retval none
74 */
dbg_low_power_enable(uint32_t dbg_low_power)75 void dbg_low_power_enable(uint32_t dbg_low_power)
76 {
77 DBG_CTL0 |= dbg_low_power;
78 }
79
80 /*!
81 \brief disable low power behavior when the mcu is in debug mode
82 \param[in] dbg_low_power:
83 this parameter can be any combination of the following values:
84 \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
85 \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
86 \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
87 \param[out] none
88 \retval none
89 */
dbg_low_power_disable(uint32_t dbg_low_power)90 void dbg_low_power_disable(uint32_t dbg_low_power)
91 {
92 DBG_CTL0 &= ~dbg_low_power;
93 }
94
95 /*!
96 \brief enable peripheral behavior when the mcu is in debug mode
97 \param[in] dbg_periph: dbg_periph_enum
98 only one parameter can be selected which is shown as below:
99 \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted
100 \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted
101 \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted
102 \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted
103 \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
104 \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted
105 \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted
106 \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted
107 \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
108 \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
109 \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
110 \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
111 \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted
112 \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted
113 \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted
114 \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted
115 \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted
116 \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted
117 \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted
118 \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
119 \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
120 \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
121 \retval none
122 */
dbg_periph_enable(dbg_periph_enum dbg_periph)123 void dbg_periph_enable(dbg_periph_enum dbg_periph)
124 {
125 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
126 }
127
128 /*!
129 \brief disable peripheral behavior when the mcu is in debug mode
130 \param[in] dbg_periph: dbg_periph_enum
131 only one parameter can be selected which is shown as below:
132 \arg DBG_TIMER1_HOLD: hold TIMER1 counter when core is halted
133 \arg DBG_TIMER2_HOLD: hold TIMER2 counter when core is halted
134 \arg DBG_TIMER3_HOLD: hold TIMER3 counter when core is halted
135 \arg DBG_TIMER4_HOLD: hold TIMER4 counter when core is halted
136 \arg DBG_TIMER5_HOLD: hold TIMER5 counter when core is halted
137 \arg DBG_TIMER6_HOLD: hold TIMER6 counter when core is halted
138 \arg DBG_TIMER11_HOLD: hold TIMER11 counter when core is halted
139 \arg DBG_TIMER12_HOLD: hold TIMER12 counter when core is halted
140 \arg DBG_TIMER13_HOLD: hold TIMER13 counter when core is halted
141 \arg DBG_RTC_HOLD: hold RTC calendar and wakeup counter when core is halted
142 \arg DBG_WWDGT_HOLD: debug WWDGT kept when core is halted
143 \arg DBG_FWDGT_HOLD: debug FWDGT kept when core is halted
144 \arg DBG_I2C0_HOLD: hold I2C0 smbus when core is halted
145 \arg DBG_I2C1_HOLD: hold I2C1 smbus when core is halted
146 \arg DBG_I2C2_HOLD: hold I2C2 smbus when core is halted
147 \arg DBG_CAN0_HOLD: debug CAN0 kept when core is halted
148 \arg DBG_CAN1_HOLD: debug CAN1 kept when core is halted
149 \arg DBG_TIMER0_HOLD: hold TIMER0 counter when core is halted
150 \arg DBG_TIMER7_HOLD: hold TIMER7 counter when core is halted
151 \arg DBG_TIMER8_HOLD: hold TIMER8 counter when core is halted
152 \arg DBG_TIMER9_HOLD: hold TIMER9 counter when core is halted
153 \arg DBG_TIMER10_HOLD: hold TIMER10 counter when core is halted
154 \param[out] none
155 \retval none
156 */
dbg_periph_disable(dbg_periph_enum dbg_periph)157 void dbg_periph_disable(dbg_periph_enum dbg_periph)
158 {
159 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
160 }
161
162 /*!
163 \brief enable trace pin assignment
164 \param[in] none
165 \param[out] none
166 \retval none
167 */
dbg_trace_pin_enable(void)168 void dbg_trace_pin_enable(void)
169 {
170 DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
171 }
172
173 /*!
174 \brief disable trace pin assignment
175 \param[in] none
176 \param[out] none
177 \retval none
178 */
dbg_trace_pin_disable(void)179 void dbg_trace_pin_disable(void)
180 {
181 DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
182 }
183
184
