1 /*! 2 \file gd32f4xx_can.h 3 \brief definitions for the CAN 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2019-11-27, V2.0.1, firmware for GD32F4xx 8 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 9 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 10 */ 11 12 /* 13 Copyright (c) 2022, GigaDevice Semiconductor Inc. 14 15 Redistribution and use in source and binary forms, with or without modification, 16 are permitted provided that the following conditions are met: 17 18 1. Redistributions of source code must retain the above copyright notice, this 19 list of conditions and the following disclaimer. 20 2. Redistributions in binary form must reproduce the above copyright notice, 21 this list of conditions and the following disclaimer in the documentation 22 and/or other materials provided with the distribution. 23 3. Neither the name of the copyright holder nor the names of its contributors 24 may be used to endorse or promote products derived from this software without 25 specific prior written permission. 26 27 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 34 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 36 OF SUCH DAMAGE. 37 */ 38 39 40 #ifndef GD32F4XX_CAN_H 41 #define GD32F4XX_CAN_H 42 43 #include "gd32f4xx.h" 44 45 /* CAN definitions */ 46 #define CAN0 CAN_BASE /*!< CAN0 base address */ 47 #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ 48 49 /* registers definitions */ 50 #define CAN_CTL(canx) REG32((canx) + 0x00000000U) /*!< CAN control register */ 51 #define CAN_STAT(canx) REG32((canx) + 0x00000004U) /*!< CAN status register */ 52 #define CAN_TSTAT(canx) REG32((canx) + 0x00000008U) /*!< CAN transmit status register*/ 53 #define CAN_RFIFO0(canx) REG32((canx) + 0x0000000CU) /*!< CAN receive FIFO0 register */ 54 #define CAN_RFIFO1(canx) REG32((canx) + 0x00000010U) /*!< CAN receive FIFO1 register */ 55 #define CAN_INTEN(canx) REG32((canx) + 0x00000014U) /*!< CAN interrupt enable register */ 56 #define CAN_ERR(canx) REG32((canx) + 0x00000018U) /*!< CAN error register */ 57 #define CAN_BT(canx) REG32((canx) + 0x0000001CU) /*!< CAN bit timing register */ 58 #define CAN_TMI0(canx) REG32((canx) + 0x00000180U) /*!< CAN transmit mailbox0 identifier register */ 59 #define CAN_TMP0(canx) REG32((canx) + 0x00000184U) /*!< CAN transmit mailbox0 property register */ 60 #define CAN_TMDATA00(canx) REG32((canx) + 0x00000188U) /*!< CAN transmit mailbox0 data0 register */ 61 #define CAN_TMDATA10(canx) REG32((canx) + 0x0000018CU) /*!< CAN transmit mailbox0 data1 register */ 62 #define CAN_TMI1(canx) REG32((canx) + 0x00000190U) /*!< CAN transmit mailbox1 identifier register */ 63 #define CAN_TMP1(canx) REG32((canx) + 0x00000194U) /*!< CAN transmit mailbox1 property register */ 64 #define CAN_TMDATA01(canx) REG32((canx) + 0x00000198U) /*!< CAN transmit mailbox1 data0 register */ 65 #define CAN_TMDATA11(canx) REG32((canx) + 0x0000019CU) /*!< CAN transmit mailbox1 data1 register */ 66 #define CAN_TMI2(canx) REG32((canx) + 0x000001A0U) /*!< CAN transmit mailbox2 identifier register */ 67 #define CAN_TMP2(canx) REG32((canx) + 0x000001A4U) /*!< CAN transmit mailbox2 property register */ 68 #define CAN_TMDATA02(canx) REG32((canx) + 0x000001A8U) /*!< CAN transmit mailbox2 data0 register */ 69 #define CAN_TMDATA12(canx) REG32((canx) + 0x000001ACU) /*!< CAN transmit mailbox2 data1 register */ 70 #define CAN_RFIFOMI0(canx) REG32((canx) + 0x000001B0U) /*!< CAN receive FIFO0 mailbox identifier register */ 71 #define CAN_RFIFOMP0(canx) REG32((canx) + 0x000001B4U) /*!< CAN receive FIFO0 mailbox property register */ 72 #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x000001B8U) /*!< CAN receive FIFO0 mailbox data0 register */ 73 #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x000001BCU) /*!< CAN receive FIFO0 mailbox data1 register */ 74 #define CAN_RFIFOMI1(canx) REG32((canx) + 0x000001C0U) /*!< CAN receive FIFO1 mailbox identifier register */ 75 #define CAN_RFIFOMP1(canx) REG32((canx) + 0x000001C4U) /*!< CAN receive FIFO1 mailbox property register */ 76 #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x000001C8U) /*!< CAN receive FIFO1 mailbox data0 register */ 77 #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x000001CCU) /*!< CAN receive FIFO1 mailbox data1 register */ 78 #define CAN_FCTL(canx) REG32((canx) + 0x00000200U) /*!< CAN filter control register */ 79 #define CAN_FMCFG(canx) REG32((canx) + 0x00000204U) /*!< CAN filter mode register */ 80 #define CAN_FSCFG(canx) REG32((canx) + 0x0000020CU) /*!< CAN filter scale register */ 81 #define CAN_FAFIFO(canx) REG32((canx) + 0x00000214U) /*!< CAN filter associated FIFO register */ 82 #define CAN_FW(canx) REG32((canx) + 0x0000021CU) /*!< CAN filter working register */ 83 #define CAN_F0DATA0(canx) REG32((canx) + 0x00000240U) /*!< CAN filter 0 data 0 register */ 84 #define CAN_F1DATA0(canx) REG32((canx) + 0x00000248U) /*!< CAN filter 1 data 0 register */ 85 #define CAN_F2DATA0(canx) REG32((canx) + 0x00000250U) /*!< CAN filter 2 data 0 register */ 86 #define CAN_F3DATA0(canx) REG32((canx) + 0x00000258U) /*!< CAN filter 3 data 0 register */ 87 #define CAN_F4DATA0(canx) REG32((canx) + 0x00000260U) /*!< CAN filter 4 data 0 register */ 88 #define CAN_F5DATA0(canx) REG32((canx) + 0x00000268U) /*!< CAN filter 5 data 0 register */ 89 #define CAN_F6DATA0(canx) REG32((canx) + 0x00000270U) /*!< CAN filter 6 data 0 register */ 90 #define CAN_F7DATA0(canx) REG32((canx) + 0x00000278U) /*!< CAN filter 7 data 0 register */ 91 #define CAN_F8DATA0(canx) REG32((canx) + 0x00000280U) /*!< CAN filter 8 data 0 register */ 92 #define CAN_F9DATA0(canx) REG32((canx) + 0x00000288U) /*!< CAN filter 9 data 0 register */ 93 #define CAN_F10DATA0(canx) REG32((canx) + 0x00000290U) /*!< CAN filter 10 data 0 register */ 94 #define CAN_F11DATA0(canx) REG32((canx) + 0x00000298U) /*!< CAN filter 11 data 0 register */ 95 #define CAN_F12DATA0(canx) REG32((canx) + 0x000002A0U) /*!< CAN filter 12 data 0 register */ 96 #define CAN_F13DATA0(canx) REG32((canx) + 0x000002A8U) /*!< CAN filter 13 data 0 register */ 97 #define CAN_F14DATA0(canx) REG32((canx) + 0x000002B0U) /*!< CAN filter 14 data 0 register */ 98 #define CAN_F15DATA0(canx) REG32((canx) + 0x000002B8U) /*!< CAN filter 15 data 0 register */ 99 #define CAN_F16DATA0(canx) REG32((canx) + 0x000002C0U) /*!< CAN filter 16 data 0 register */ 100 #define CAN_F17DATA0(canx) REG32((canx) + 0x000002C8U) /*!< CAN filter 17 data 0 register */ 101 #define CAN_F18DATA0(canx) REG32((canx) + 0x000002D0U) /*!< CAN filter 18 data 0 register */ 102 #define CAN_F19DATA0(canx) REG32((canx) + 0x000002D8U) /*!< CAN filter 19 data 0 register */ 103 #define CAN_F20DATA0(canx) REG32((canx) + 0x000002E0U) /*!< CAN filter 20 data 0 register */ 104 #define CAN_F21DATA0(canx) REG32((canx) + 0x000002E8U) /*!< CAN filter 21 data 0 register */ 105 #define CAN_F22DATA0(canx) REG32((canx) + 0x000002F0U) /*!< CAN filter 22 data 0 register */ 106 #define CAN_F23DATA0(canx) REG32((canx) + 0x000003F8U) /*!< CAN filter 23 data 0 register */ 107 #define CAN_F24DATA0(canx) REG32((canx) + 0x00000300U) /*!< CAN filter 24 data 0 register */ 108 #define CAN_F25DATA0(canx) REG32((canx) + 0x00000308U) /*!< CAN filter 25 data 0 register */ 109 #define CAN_F26DATA0(canx) REG32((canx) + 0x00000310U) /*!< CAN filter 26 data 0 register */ 110 #define CAN_F27DATA0(canx) REG32((canx) + 0x00000318U) /*!< CAN filter 27 data 0 register */ 111 #define CAN_F0DATA1(canx) REG32((canx) + 0x00000244U) /*!< CAN filter 0 data 1 register */ 112 #define CAN_F1DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 1 data 1 register */ 113 #define CAN_F2DATA1(canx) REG32((canx) + 0x00000254U) /*!< CAN filter 2 data 1 register */ 114 #define CAN_F3DATA1(canx) REG32((canx) + 0x0000025CU) /*!< CAN filter 3 data 1 register */ 115 #define CAN_F4DATA1(canx) REG32((canx) + 0x00000264U) /*!< CAN filter 4 data 1 register */ 116 #define CAN_F5DATA1(canx) REG32((canx) + 0x0000026CU) /*!< CAN filter 5 data 1 register */ 117 #define CAN_F6DATA1(canx) REG32((canx) + 0x00000274U) /*!< CAN filter 6 data 1 register */ 118 #define CAN_F7DATA1(canx) REG32((canx) + 0x0000027CU) /*!< CAN filter 7 data 1 register */ 119 #define CAN_F8DATA1(canx) REG32((canx) + 0x00000284U) /*!< CAN filter 8 data 1 register */ 120 #define CAN_F9DATA1(canx) REG32((canx) + 0x0000028CU) /*!< CAN filter 9 data 1 register */ 121 #define CAN_F10DATA1(canx) REG32((canx) + 0x00000294U) /*!< CAN filter 10 data 1 register */ 122 #define CAN_F11DATA1(canx) REG32((canx) + 0x0000029CU) /*!< CAN filter 11 data 1 register */ 123 #define CAN_F12DATA1(canx) REG32((canx) + 0x000002A4U) /*!< CAN filter 12 data 1 register */ 124 #define CAN_F13DATA1(canx) REG32((canx) + 0x000002ACU) /*!< CAN filter 13 data 1 register */ 125 #define CAN_F14DATA1(canx) REG32((canx) + 0x000002B4U) /*!< CAN filter 14 data 1 register */ 126 #define CAN_F15DATA1(canx) REG32((canx) + 0x000002BCU) /*!< CAN filter 15 data 1 register */ 127 #define CAN_F16DATA1(canx) REG32((canx) + 0x000002C4U) /*!< CAN filter 16 data 1 register */ 128 #define CAN_F17DATA1(canx) REG32((canx) + 0x0000024CU) /*!< CAN filter 17 data 1 register */ 129 #define CAN_F18DATA1(canx) REG32((canx) + 0x000002D4U) /*!< CAN filter 18 data 1 register */ 130 #define CAN_F19DATA1(canx) REG32((canx) + 0x000002DCU) /*!< CAN filter 19 data 1 register */ 131 #define CAN_F20DATA1(canx) REG32((canx) + 0x000002E4U) /*!< CAN filter 20 data 1 register */ 132 #define CAN_F21DATA1(canx) REG32((canx) + 0x000002ECU) /*!< CAN filter 21 data 1 register */ 133 #define CAN_F22DATA1(canx) REG32((canx) + 0x000002F4U) /*!< CAN filter 22 data 1 register */ 134 #define CAN_F23DATA1(canx) REG32((canx) + 0x000002FCU) /*!< CAN filter 23 data 1 register */ 135 #define CAN_F24DATA1(canx) REG32((canx) + 0x00000304U) /*!< CAN filter 24 data 1 register */ 136 #define CAN_F25DATA1(canx) REG32((canx) + 0x0000030CU) /*!< CAN filter 25 data 1 register */ 137 #define CAN_F26DATA1(canx) REG32((canx) + 0x00000314U) /*!< CAN filter 26 data 1 register */ 138 #define CAN_F27DATA1(canx) REG32((canx) + 0x0000031CU) /*!< CAN filter 27 data 1 register */ 139 140 /* CAN transmit mailbox bank */ 141 #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ 142 #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ 143 #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ 144 #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ 145 146 /* CAN filter bank */ 147 #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ 148 #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ 149 150 /* CAN receive FIFO mailbox bank */ 151 #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ 152 #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ 153 #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ 154 #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ 155 156 /* bits definitions */ 157 /* CAN_CTL */ 158 #define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ 159 #define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ 160 #define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ 161 #define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ 162 #define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ 163 #define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ 164 #define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ 165 #define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ 166 #define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ 167 #define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ 168 169 /* CAN_STAT */ 170 #define CAN_STAT_IWS BIT(0) /*!< initial working state */ 171 #define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ 172 #define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ 173 #define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ 174 #define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ 175 #define CAN_STAT_TS BIT(8) /*!< transmitting state */ 176 #define CAN_STAT_RS BIT(9) /*!< receiving state */ 177 #define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ 178 #define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ 179 180 /* CAN_TSTAT */ 181 #define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ 182 #define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ 183 #define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ 184 #define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ 185 #define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ 186 #define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ 187 #define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ 188 #define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ 189 #define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ 190 #define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ 191 #define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ 192 #define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ 193 #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ 194 #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ 195 #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ 196 #define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ 197 #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ 198 #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ 199 #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ 200 #define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ 201 #define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ 202 #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ 203 204 /* CAN_RFIFO0 */ 205 #define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ 206 #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ 207 #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ 208 #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ 209 210 /* CAN_RFIFO1 */ 211 #define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ 212 #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ 213 #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ 214 #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ 215 216 /* CAN_INTEN */ 217 #define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ 218 #define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ 219 #define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ 220 #define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ 221 #define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ 222 #define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ 223 #define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ 224 #define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ 225 #define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ 226 #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ 227 #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ 228 #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ 229 #define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ 230 #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ 231 232 /* CAN_ERR */ 233 #define CAN_ERR_WERR BIT(0) /*!< warning error */ 234 #define CAN_ERR_PERR BIT(1) /*!< passive error */ 235 #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ 236 #define CAN_ERR_ERRN BITS(4,6) /*!< error number */ 237 #define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ 238 #define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ 239 240 /* CAN_BT */ 241 #define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ 242 #define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ 243 #define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ 244 #define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ 245 #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ 246 #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ 247 248 /* CAN_TMIx */ 249 #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ 250 #define CAN_TMI_FT BIT(1) /*!< frame type */ 251 #define CAN_TMI_FF BIT(2) /*!< frame format */ 252 #define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ 253 #define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ 254 255 /* CAN_TMPx */ 256 #define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ 257 #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ 258 #define CAN_TMP_TS BITS(16,31) /*!< time stamp */ 259 260 /* CAN_TMDATA0x */ 261 #define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ 262 #define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ 263 #define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ 264 #define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ 265 266 /* CAN_TMDATA1x */ 267 #define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ 268 #define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ 269 #define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ 270 #define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ 271 272 /* CAN_RFIFOMIx */ 273 #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ 274 #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ 275 #define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ 276 #define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ 277 278 /* CAN_RFIFOMPx */ 279 #define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ 280 #define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ 281 #define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ 282 283 /* CAN_RFIFOMDATA0x */ 284 #define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ 285 #define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ 286 #define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ 287 #define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ 288 289 /* CAN_RFIFOMDATA1x */ 290 #define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ 291 #define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ 292 #define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ 293 #define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ 294 295 /* CAN_FCTL */ 296 #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ 297 #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ 298 299 /* CAN_FMCFG */ 300 #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask */ 301 302 /* CAN_FSCFG */ 303 #define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits */ 304 305 /* CAN_FAFIFO */ 306 #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ 307 308 /* CAN_FW */ 309 #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ 310 311 /* CAN_FxDATAy */ 312 #define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ 313 314 /* constants definitions */ 315 /* define the CAN bit position and its register index offset */ 316 #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 317 #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) 318 #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 319 320 #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) 321 #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) 322 #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) 323 #define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) 324 325 /* register offset */ 326 #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ 327 #define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ 328 #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ 329 #define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ 330 #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ 331 332 /* CAN flags */ 333 typedef enum { 334 /* flags in STAT register */ 335 CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ 336 CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ 337 CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ 338 CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ 339 CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ 340 CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ 341 CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ 342 CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ 343 CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ 344 /* flags in TSTAT register */ 345 CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in TX FIFO */ 346 CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in TX FIFO */ 347 CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in TX FIFO */ 348 CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ 349 CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ 350 CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ 351 CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ 352 CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ 353 CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ 354 CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ 355 CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ 356 CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ 357 CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ 358 CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ 359 CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ 360 CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ 361 CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ 362 CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ 363 /* flags in RFIFO0 register */ 364 CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ 365 CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ 366 /* flags in RFIFO1 register */ 367 CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ 368 CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ 369 /* flags in ERR register */ 370 CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ 371 CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ 372 CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ 373 } can_flag_enum; 374 375 /* CAN interrupt flags */ 376 typedef enum { 377 /* interrupt flags in STAT register */ 378 CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ 379 CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ 380 CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ 381 /* interrupt flags in TSTAT register */ 382 CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ 383 CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ 384 CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ 385 /* interrupt flags in RFIFO0 register */ 386 CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ 387 CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ 388 CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ 389 /* interrupt flags in RFIFO0 register */ 390 CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ 391 CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ 392 CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ 393 /* interrupt flags in ERR register */ 394 CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ 395 CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ 396 CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ 397 CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ 398 } can_interrupt_flag_enum; 399 400 /* CAN initiliaze parameters structure */ 401 typedef struct { 402 uint8_t working_mode; /*!< CAN working mode */ 403 uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ 404 uint8_t time_segment_1; /*!< time segment 1 */ 405 uint8_t time_segment_2; /*!< time segment 2 */ 406 ControlStatus time_triggered; /*!< time triggered communication mode */ 407 ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ 408 ControlStatus auto_wake_up; /*!< automatic wake-up mode */ 409 ControlStatus auto_retrans; /*!< automatic retransmission mode disable */ 410 ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode disable */ 411 ControlStatus trans_fifo_order; /*!< transmit FIFO order */ 412 uint16_t prescaler; /*!< baudrate prescaler */ 413 } can_parameter_struct; 414 415 /* CAN transmit message structure */ 416 typedef struct { 417 uint32_t tx_sfid; /*!< standard format frame identifier */ 418 uint32_t tx_efid; /*!< extended format frame identifier */ 419 uint8_t tx_ff; /*!< format of frame, standard or extended format */ 420 uint8_t tx_ft; /*!< type of frame, data or remote */ 421 uint8_t tx_dlen; /*!< data length */ 422 uint8_t tx_data[8]; /*!< transmit data */ 423 } can_trasnmit_message_struct; 424 425 /* CAN receive message structure */ 426 typedef struct { 427 uint32_t rx_sfid; /*!< standard format frame identifier */ 428 uint32_t rx_efid; /*!< extended format frame identifier */ 429 uint8_t rx_ff; /*!< format of frame, standard or extended format */ 430 uint8_t rx_ft; /*!< type of frame, data or remote */ 431 uint8_t rx_dlen; /*!< data length */ 432 uint8_t rx_data[8]; /*!< receive data */ 433 uint8_t rx_fi; /*!< filtering index */ 434 } can_receive_message_struct; 435 436 /* CAN filter parameters structure */ 437 typedef struct { 438 uint16_t filter_list_high; /*!< filter list number high bits */ 439 uint16_t filter_list_low; /*!< filter list number low bits */ 440 uint16_t filter_mask_high; /*!< filter mask number high bits */ 441 uint16_t filter_mask_low; /*!< filter mask number low bits */ 442 uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ 443 uint16_t filter_number; /*!< filter number */ 444 uint16_t filter_mode; /*!< filter mode, list or mask */ 445 uint16_t filter_bits; /*!< filter scale */ 446 ControlStatus filter_enable; /*!< filter work or not */ 447 } can_filter_parameter_struct; 448 449 /* CAN errors */ 450 typedef enum { 451 CAN_ERROR_NONE = 0, /*!< no error */ 452 CAN_ERROR_FILL, /*!< fill error */ 453 CAN_ERROR_FORMATE, /*!< format error */ 454 CAN_ERROR_ACK, /*!< ACK error */ 455 CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ 456 CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ 457 CAN_ERROR_CRC, /*!< CRC error */ 458 CAN_ERROR_SOFTWARECFG, /*!< software configure */ 459 } can_error_enum; 460 461 /* transmit states */ 462 typedef enum { 463 CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ 464 CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ 465 CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ 466 CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ 467 } can_transmit_state_enum; 468 469 typedef enum { 470 CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ 471 CAN_FILTER_STRUCT, /* CAN filter parameters struct */ 472 CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ 473 CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ 474 } can_struct_type_enum; 475 476 /* CAN baudrate prescaler */ 477 #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) 478 479 /* CAN bit segment 1 */ 480 #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) 481 482 /* CAN bit segment 2 */ 483 #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) 484 485 /* CAN resynchronization jump width */ 486 #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) 487 488 /* CAN communication mode */ 489 #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) 490 491 /* CAN FDATA high 16 bits */ 492 #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) 493 494 /* CAN FDATA low 16 bits */ 495 #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) 496 497 /* CAN1 filter start bank_number */ 498 #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) 499 500 /* CAN transmit mailbox extended identifier */ 501 #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) 502 503 /* CAN transmit mailbox standard identifier */ 504 #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) 505 506 /* transmit data byte 0 */ 507 #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 508 509 /* transmit data byte 1 */ 510 #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 511 512 /* transmit data byte 2 */ 513 #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 514 515 /* transmit data byte 3 */ 516 #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 517 518 /* transmit data byte 4 */ 519 #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 520 521 /* transmit data byte 5 */ 522 #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 523 524 /* transmit data byte 6 */ 525 #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 526 527 /* transmit data byte 7 */ 528 #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 529 530 /* receive mailbox extended identifier */ 531 #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) 532 533 /* receive mailbox standard identifier */ 534 #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) 535 536 /* receive data length */ 537 #define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) 538 539 /* the index of the filter by which the frame is passed */ 540 #define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 541 542 /* receive data byte 0 */ 543 #define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) 544 545 /* receive data byte 1 */ 546 #define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 547 548 /* receive data byte 2 */ 549 #define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 550 551 /* receive data byte 3 */ 552 #define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 553 554 /* receive data byte 4 */ 555 #define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) 556 557 /* receive data byte 5 */ 558 #define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 559 560 /* receive data byte 6 */ 561 #define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 562 563 /* receive data byte 7 */ 564 #define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 565 566 /* error number */ 567 #define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) 568 569 /* transmit error count */ 570 #define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 571 572 /* receive error count */ 573 #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 574 575 /* CAN errors */ 576 #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 577 #define CAN_ERRN_0 ERR_ERRN(0U) /*!< no error */ 578 #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ 579 #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ 580 #define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ 581 #define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ 582 #define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ 583 #define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ 584 #define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ 585 586 #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ 587 588 /* CAN communication mode */ 589 #define GD32_CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ 590 #define GD32_CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ 591 #define GD32_CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ 592 #define GD32_CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ 593 594 /* CAN resynchronisation jump width */ 595 #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 596 #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 597 #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 598 #define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 599 600 /* CAN time segment 1 */ 601 #define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 602 #define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 603 #define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 604 #define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 605 #define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 606 #define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 607 #define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 608 #define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 609 #define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ 610 #define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ 611 #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ 612 #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ 613 #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ 614 #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ 615 #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ 616 #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ 617 618 /* CAN time segment 2 */ 619 #define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 620 #define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 621 #define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 622 #define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 623 #define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 624 #define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 625 #define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 626 #define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 627 628 /* CAN mailbox number */ 629 #define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ 630 #define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ 631 #define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ 632 #define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ 633 634 /* CAN frame format */ 635 #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ 636 #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ 637 638 /* CAN receive FIFO */ 639 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ 640 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ 641 642 /* frame number of receive FIFO */ 643 #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ 644 645 #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ 646 #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ 647 648 /* CAN working mode */ 649 #define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ 650 #define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ 651 #define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ 652 653 /* filter bits */ 654 #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ 655 #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ 656 657 /* filter mode */ 658 #define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ 659 #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ 660 661 /* filter 16 bits mask */ 662 #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ 663 664 /* frame type */ 665 #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ 666 #define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ 667 668 /* CAN timeout */ 669 #define GD32_CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ 670 671 /* interrupt enable bits */ 672 #define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ 673 #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ 674 #define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ 675 #define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ 676 #define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ 677 #define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ 678 #define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ 679 #define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ 680 #define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ 681 #define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ 682 #define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ 683 #define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ 684 #define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ 685 #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ 686 687 /* function declarations */ 688 /* initialization functions */ 689 /* deinitialize CAN */ 690 void can_deinit(uint32_t can_periph); 691 /* initialize CAN structure */ 692 void can_struct_para_init(can_struct_type_enum type, void *p_struct); 693 /* initialize CAN */ 694 ErrStatus can_init(uint32_t can_periph, can_parameter_struct *can_parameter_init); 695 /* CAN filter initialization */ 696 void can_filter_init(can_filter_parameter_struct *can_filter_parameter_init); 697 698 /* function configuration */ 699 /* set can1 filter start bank number */ 700 void can1_filter_start_bank(uint8_t start_bank); 701 /* enable functions */ 702 /* CAN debug freeze enable */ 703 void can_debug_freeze_enable(uint32_t can_periph); 704 /* CAN debug freeze disable */ 705 void can_debug_freeze_disable(uint32_t can_periph); 706 /* CAN time trigger mode enable */ 707 void can_time_trigger_mode_enable(uint32_t can_periph); 708 /* CAN time trigger mode disable */ 709 void can_time_trigger_mode_disable(uint32_t can_periph); 710 711 /* transmit functions */ 712 /* transmit CAN message */ 713 uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct *transmit_message); 714 /* get CAN transmit state */ 715 can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); 716 /* stop CAN transmission */ 717 void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); 718 /* CAN receive message */ 719 void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct *receive_message); 720 /* CAN release FIFO */ 721 void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); 722 /* CAN receive message length */ 723 uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); 724 /* CAN working mode */ 725 ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); 726 /* CAN wakeup from sleep mode */ 727 ErrStatus can_wakeup(uint32_t can_periph); 728 729 /* CAN get error type */ 730 can_error_enum can_error_get(uint32_t can_periph); 731 /* get CAN receive error number */ 732 uint8_t can_receive_error_number_get(uint32_t can_periph); 733 /* get CAN transmit error number */ 734 uint8_t can_transmit_error_number_get(uint32_t can_periph); 735 736 /* interrupt & flag functions */ 737 /* CAN get flag state */ 738 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); 739 /* CAN clear flag state */ 740 void can_flag_clear(uint32_t can_periph, can_flag_enum flag); 741 /* CAN interrupt enable */ 742 void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); 743 /* CAN interrupt disable */ 744 void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); 745 /* CAN get interrupt flag state */ 746 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); 747 /* CAN clear interrupt flag state */ 748 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); 749 750 #endif /* GD32F4XX_CAN_H */ 751
