1 /*! 2 \file gd32f403_usart.h 3 \brief general definitions for GD32F403 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F403_USART_H 38 #define GD32F403_USART_H 39 40 #include "gd32f403.h" 41 42 /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ 43 #define USART1 USART_BASE /*!< USART1 base address */ 44 #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ 45 #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ 46 #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ 47 #define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ 48 49 /* registers definitions */ 50 #define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ 51 #define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ 52 #define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ 53 #define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ 54 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ 55 #define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ 56 #define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ 57 #define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ 58 #define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ 59 #define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ 60 61 /* bits definitions */ 62 /* USARTx_STAT0 */ 63 #define USART_STAT0_PERR BIT(0) /*!< parity error flag */ 64 #define USART_STAT0_FERR BIT(1) /*!< frame error flag */ 65 #define USART_STAT0_NERR BIT(2) /*!< noise error flag */ 66 #define USART_STAT0_ORERR BIT(3) /*!< overrun error */ 67 #define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ 68 #define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ 69 #define USART_STAT0_TC BIT(6) /*!< transmission complete */ 70 #define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ 71 #define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ 72 #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ 73 74 /* USARTx_DATA */ 75 #define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ 76 77 /* USARTx_BAUD */ 78 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ 79 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ 80 81 /* USARTx_CTL0 */ 82 #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ 83 #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ 84 #define USART_CTL0_REN BIT(2) /*!< receiver enable */ 85 #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ 86 #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 87 #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 88 #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 89 #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 90 #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 91 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 92 #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ 93 #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 94 #define USART_CTL0_WL BIT(12) /*!< word length */ 95 #define USART_CTL0_UEN BIT(13) /*!< USART enable */ 96 97 /* USARTx_CTL1 */ 98 #define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ 99 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 100 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ 101 #define USART_CTL1_CLEN BIT(8) /*!< CK length */ 102 #define USART_CTL1_CPH BIT(9) /*!< CK phase */ 103 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ 104 #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ 105 #define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ 106 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 107 108 /* USARTx_CTL2 */ 109 #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ 110 #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 111 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 112 #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 113 #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 114 #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 115 #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ 116 #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ 117 #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 118 #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 119 #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 120 121 /* USARTx_GP */ 122 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 123 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 124 125 /* USARTx_CTL3 */ 126 #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ 127 #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ 128 #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ 129 #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ 130 #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ 131 #define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ 132 #define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ 133 #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ 134 135 /* USARTx_RT */ 136 #define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 137 #define USART_RT_BL BITS(24,31) /*!< block length */ 138 139 /* USARTx_STAT1 */ 140 #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ 141 #define USART_STAT1_EBF BIT(12) /*!< end of block flag */ 142 #define USART_STAT1_BSY BIT(16) /*!< busy flag */ 143 144 /* constants definitions */ 145 /* define the USART bit position and its register index offset */ 146 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 147 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) 148 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 149 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 150 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 151 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 152 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) 153 154 /* register offset */ 155 #define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ 156 #define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ 157 #define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ 158 #define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ 159 #define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ 160 #define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ 161 162 /* USART flags */ 163 typedef enum 164 { 165 /* flags in STAT0 register */ 166 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ 167 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ 168 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 169 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ 170 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ 171 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ 172 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ 173 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ 174 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ 175 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ 176 /* flags in STAT1 register */ 177 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ 178 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ 179 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ 180 }usart_flag_enum; 181 182 /* USART interrupt flags */ 183 typedef enum 184 { 185 /* interrupt flags in CTL0 register */ 186 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 187 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 188 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 189 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 190 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 191 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 192 /* interrupt flags in CTL1 register */ 193 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 194 /* interrupt flags in CTL2 register */ 195 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 196 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 197 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 198 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 199 /* interrupt flags in CTL3 register */ 200 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ 201 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ 202 }usart_interrupt_flag_enum; 203 204 /* USART interrupt enable or disable */ 205 typedef enum 206 { 207 /* interrupt in CTL0 register */ 208 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 209 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 210 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 211 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 212 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 213 /* interrupt in CTL1 register */ 214 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 215 /* interrupt in CTL2 register */ 216 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 217 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 218 /* interrupt in CTL3 register */ 219 USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ 220 USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ 221 }usart_interrupt_enum; 222 223 /* USART invert configure */ 224 typedef enum 225 { 226 /* data bit level inversion */ 227 USART_DINV_ENABLE, /*!< data bit level inversion */ 228 USART_DINV_DISABLE, /*!< data bit level not inversion */ 229 /* TX pin level inversion */ 230 USART_TXPIN_ENABLE, /*!< TX pin level inversion */ 231 USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 232 /* RX pin level inversion */ 233 USART_RXPIN_ENABLE, /*!< RX pin level inversion */ 234 USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 235 }usart_invert_enum; 236 237 /* USART receiver configure */ 238 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 239 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 240 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 241 242 /* USART transmitter configure */ 243 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 244 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 245 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 246 247 /* USART parity bits definitions */ 248 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 249 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 250 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 251 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 252 253 /* USART wakeup method in mute mode */ 254 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 255 #define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ 256 #define USART_WM_ADDR CTL0_WM(1) /*!< address match */ 257 258 /* USART word length definitions */ 259 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 260 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 261 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 262 263 /* USART stop bits definitions */ 264 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 265 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 266 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 267 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 268 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 269 270 /* USART LIN break frame length */ 271 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 272 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ 273 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ 274 275 /* USART CK length */ 276 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 277 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ 278 #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ 279 280 /* USART clock phase */ 281 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 282 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 283 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 284 285 /* USART clock polarity */ 286 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 287 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 288 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 289 290 /* USART DMA request for receive configure */ 291 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 292 #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ 293 #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ 294 295 /* USART DMA request for transmission configure */ 296 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 297 #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ 298 #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ 299 300 /* USART RTS configure */ 301 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 302 #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ 303 #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ 304 305 /* USART CTS configure */ 306 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 307 #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ 308 #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ 309 310 /* USART IrDA low-power enable */ 311 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 312 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 313 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 314 315 /* USART data is transmitted/received with the LSB/MSB first */ 316 #define CTL3_MSBF(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 317 #define USART_MSBF_LSB CTL3_MSBF(0) /*!< LSB first */ 318 #define USART_MSBF_MSB CTL3_MSBF(1) /*!< MSB first */ 319 320 /* function declarations */ 321 /* initialization functions */ 322 /* reset USART */ 323 void usart_deinit(uint32_t usart_periph); 324 /* configure USART baud rate value */ 325 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 326 /* configure USART parity function */ 327 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 328 /* configure USART word length */ 329 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 330 /* configure USART stop bit length */ 331 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 332 /* enable USART */ 333 void usart_enable(uint32_t usart_periph); 334 /* disable USART */ 335 void usart_disable(uint32_t usart_periph); 336 /* configure USART transmitter */ 337 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 338 /* configure USART receiver */ 339 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 340 341 /* USART normal mode communication */ 342 /* data is transmitted/received with the LSB/MSB first */ 343 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); 344 /* configure USART inverted */ 345 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); 346 /* enable receiver timeout */ 347 void usart_receiver_timeout_enable(uint32_t usart_periph); 348 /* disable receiver timeout */ 349 void usart_receiver_timeout_disable(uint32_t usart_periph); 350 /* configure receiver timeout threshold */ 351 void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); 352 /* USART transmit data function */ 353 void usart_data_transmit(uint32_t usart_periph, uint32_t data); 354 /* USART receive data function */ 355 uint16_t usart_data_receive(uint32_t usart_periph); 356 357 /* multi-processor communication */ 358 /* configure address of the USART */ 359 void usart_address_config(uint32_t usart_periph, uint8_t addr); 360 /* enable mute mode */ 361 void usart_mute_mode_enable(uint32_t usart_periph); 362 /* disable mute mode */ 363 void usart_mute_mode_disable(uint32_t usart_periph); 364 /* configure wakeup method in mute mode */ 365 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); 366 367 /* LIN mode communication */ 368 /* enable LIN mode */ 369 void usart_lin_mode_enable(uint32_t usart_periph); 370 /* disable LIN mode */ 371 void usart_lin_mode_disable(uint32_t usart_periph); 372 /* LIN break detection length */ 373 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 374 /* send break frame */ 375 void usart_send_break(uint32_t usart_periph); 376 377 /* half-duplex communication */ 378 /* enable half-duplex mode */ 379 void usart_halfduplex_enable(uint32_t usart_periph); 380 /* disable half-duplex mode */ 381 void usart_halfduplex_disable(uint32_t usart_periph); 382 383 /* synchronous communication */ 384 /* enable CK pin in synchronous mode */ 385 void usart_synchronous_clock_enable(uint32_t usart_periph); 386 /* disable CK pin in synchronous mode */ 387 void usart_synchronous_clock_disable(uint32_t usart_periph); 388 /* configure usart synchronous mode parameters */ 389 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 390 391 /* smartcard communication */ 392 /* configure guard time value in smartcard mode */ 393 void usart_guard_time_config(uint32_t usart_periph,uint32_t guat); 394 /* enable smartcard mode */ 395 void usart_smartcard_mode_enable(uint32_t usart_periph); 396 /* disable smartcard mode */ 397 void usart_smartcard_mode_disable(uint32_t usart_periph); 398 /* enable NACK in smartcard mode */ 399 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 400 /* disable NACK in smartcard mode */ 401 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 402 /* configure smartcard auto-retry number */ 403 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); 404 /* configure block length */ 405 void usart_block_length_config(uint32_t usart_periph, uint32_t bl); 406 407 /* IrDA communication */ 408 /* enable IrDA mode */ 409 void usart_irda_mode_enable(uint32_t usart_periph); 410 /* disable IrDA mode */ 411 void usart_irda_mode_disable(uint32_t usart_periph); 412 /* configure the peripheral clock prescaler */ 413 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); 414 /* configure IrDA low-power */ 415 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 416 417 /* hardware flow communication */ 418 /* configure hardware flow control RTS */ 419 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 420 /* configure hardware flow control CTS */ 421 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 422 423 /* DMA communication */ 424 /* configure USART DMA for reception */ 425 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); 426 /* configure USART DMA for transmission */ 427 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); 428 429 /* flag & interrupt functions */ 430 /* get flag in STAT0/STAT1 register */ 431 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 432 /* clear flag in STAT0/STAT1 register */ 433 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 434 /* enable USART interrupt */ 435 void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); 436 /* disable USART interrupt */ 437 void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); 438 /* get USART interrupt and flag status */ 439 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 440 /* clear interrupt flag in STAT0/STAT1 register */ 441 void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 442 443 #endif /* GD32F403_USART_H */ 444
