1 /*! 2 \file gd32f403_rtc.h 3 \brief definitions for the RTC 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F403_RTC_H 38 #define GD32F403_RTC_H 39 40 #include "gd32f403.h" 41 42 /* RTC definitions */ 43 #define RTC RTC_BASE 44 45 /* registers definitions */ 46 #define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ 47 #define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ 48 #define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ 49 #define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ 50 #define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ 51 #define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ 52 #define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ 53 #define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ 54 #define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ 55 #define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ 56 57 /* bits definitions */ 58 /* RTC_INTEN */ 59 #define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ 60 #define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ 61 #define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ 62 63 /* RTC_CTL */ 64 #define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ 65 #define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ 66 #define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ 67 #define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ 68 #define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ 69 #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ 70 71 /* RTC_PSC */ 72 #define RTC_PSCH_PSC BITS(0, 3) /*!< prescaler high value */ 73 #define RTC_PSCL_PSC BITS(0, 15) /*!< prescaler low value */ 74 75 /* RTC_DIV */ 76 #define RTC_DIVH_DIV BITS(0, 3) /*!< divider high value */ 77 #define RTC_DIVL_DIV BITS(0, 15) /*!< divider low value */ 78 79 /* RTC_CNT */ 80 #define RTC_CNTH_CNT BITS(0, 15) /*!< counter high value */ 81 #define RTC_CNTL_CNT BITS(0, 15) /*!< counter low value */ 82 83 /* RTC_ALRM */ 84 #define RTC_ALRMH_ALRM BITS(0, 15) /*!< alarm high value */ 85 #define RTC_ALRML_ALRM BITS(0, 15) /*!< alarm low value */ 86 87 /* constants definitions */ 88 #define RTC_HIGH_VALUE 0x000F0000U /*!< RTC high value */ 89 #define RTC_LOW_VALUE 0x0000FFFFU /*!< RTC low value */ 90 91 /* RTC interrupt definitions */ 92 #define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ 93 #define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ 94 #define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ 95 96 /* RTC flag definitions */ 97 #define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ 98 #define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ 99 #define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ 100 #define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ 101 #define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ 102 103 /* function declarations */ 104 /* enable RTC interrupt */ 105 void rtc_interrupt_enable(uint32_t interrupt); 106 /* disable RTC interrupt */ 107 void rtc_interrupt_disable(uint32_t interrupt); 108 109 /* enter RTC configuration mode */ 110 void rtc_configuration_mode_enter(void); 111 /* exit RTC configuration mode */ 112 void rtc_configuration_mode_exit(void); 113 114 /* wait RTC last write operation finished flag set */ 115 void rtc_lwoff_wait(void); 116 /* wait RTC registers synchronized flag set */ 117 void rtc_register_sync_wait(void); 118 119 /* get RTC counter value */ 120 uint32_t rtc_counter_get(void); 121 /* set RTC counter value */ 122 void rtc_counter_set(uint32_t cnt); 123 124 /* set RTC prescaler value */ 125 void rtc_prescaler_set(uint32_t psc); 126 /* set RTC alarm value */ 127 void rtc_alarm_config(uint32_t alarm); 128 /* get RTC divider value */ 129 uint32_t rtc_divider_get(void); 130 131 /* get RTC flag status */ 132 FlagStatus rtc_flag_get(uint32_t flag); 133 /* clear RTC flag status */ 134 void rtc_flag_clear(uint32_t flag); 135 136 #endif /* GD32F403_RTC_H */ 137
