1 /*! 2 \file gd32f403_rcu.h 3 \brief definitions for the RCU 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F403_RCU_H 38 #define GD32F403_RCU_H 39 40 #include "gd32f403.h" 41 42 /* RCU definitions */ 43 #define RCU RCU_BASE 44 45 /* registers definitions */ 46 #define RCU_CTL REG32(RCU + 0x00U) /*!< control register */ 47 #define RCU_CFG0 REG32(RCU + 0x04U) /*!< clock configuration register 0 */ 48 #define RCU_INT REG32(RCU + 0x08U) /*!< clock interrupt register */ 49 #define RCU_APB2RST REG32(RCU + 0x0CU) /*!< APB2 reset register */ 50 #define RCU_APB1RST REG32(RCU + 0x10U) /*!< APB1 reset register */ 51 #define RCU_AHBEN REG32(RCU + 0x14U) /*!< AHB1 enable register */ 52 #define RCU_APB2EN REG32(RCU + 0x18U) /*!< APB2 enable register */ 53 #define RCU_APB1EN REG32(RCU + 0x1CU) /*!< APB1 enable register */ 54 #define RCU_BDCTL REG32(RCU + 0x20U) /*!< backup domain control register */ 55 #define RCU_RSTSCK REG32(RCU + 0x24U) /*!< reset source / clock register */ 56 #define RCU_AHBRST REG32(RCU + 0x28U) /*!< AHB reset register */ 57 #define RCU_CFG1 REG32(RCU + 0x2CU) /*!< clock configuration register 1 */ 58 #define RCU_DSV REG32(RCU + 0x34U) /*!< deep-sleep mode voltage register */ 59 #define RCU_ADDCTL REG32(RCU + 0xC0U) /*!< Additional clock control register */ 60 #define RCU_ADDINT REG32(RCU + 0xCCU) /*!< Additional clock interrupt register */ 61 #define RCU_ADDAPB1RST REG32(RCU + 0xE0U) /*!< APB1 additional reset register */ 62 #define RCU_ADDAPB1EN REG32(RCU + 0xE4U) /*!< APB1 additional enable register */ 63 64 /* bits definitions */ 65 /* RCU_CTL */ 66 #define RCU_CTL_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 67 #define RCU_CTL_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 68 #define RCU_CTL_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 69 #define RCU_CTL_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 70 #define RCU_CTL_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 71 #define RCU_CTL_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 72 #define RCU_CTL_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 73 #define RCU_CTL_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 74 #define RCU_CTL_PLLEN BIT(24) /*!< PLL enable */ 75 #define RCU_CTL_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 76 #define RCU_CTL_PLL1EN BIT(26) /*!< PLL1 enable */ 77 #define RCU_CTL_PLL1STB BIT(27) /*!< PLL1 clock stabilization flag */ 78 #define RCU_CTL_PLL2EN BIT(28) /*!< PLL2 enable */ 79 #define RCU_CTL_PLL2STB BIT(29) /*!< PLL2 clock stabilization flag */ 80 81 /* RCU_CFG0 */ 82 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 83 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 84 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 85 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 86 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 87 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC prescaler selection */ 88 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 89 #define RCU_CFG0_PREDV0_LSB BIT(17) /*!< the LSB of PREDV0 division factor */ 90 #define RCU_CFG0_PLLMF BITS(18,21) /*!< PLL clock multiplication factor */ 91 #define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ 92 #define RCU_CFG0_CKOUT0SEL BITS(24,27) /*!< CKOUT0 clock source selection */ 93 #define RCU_CFG0_ADCPSC_2 BIT(28) /*!< bit 2 of ADCPSC */ 94 #define RCU_CFG0_PLLMF_4 BIT(29) /*!< bit 4 of PLLMF */ 95 #define RCU_CFG0_PLLMF_5 BIT(30) /*!< bit 5 of PLLMF */ 96 #define RCU_CFG0_USBFSPSC_2 BIT(31) /*!< bit 2 of USBFSPSC */ 97 98 /* RCU_INT */ 99 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 100 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 101 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 102 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 103 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 104 #define RCU_INT_PLL1STBIF BIT(5) /*!< PLL1 stabilization interrupt flag */ 105 #define RCU_INT_PLL2STBIF BIT(6) /*!< PLL2 stabilization interrupt flag */ 106 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 107 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 108 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 109 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 110 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 111 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 112 #define RCU_INT_PLL1STBIE BIT(13) /*!< PLL1 stabilization interrupt enable */ 113 #define RCU_INT_PLL2STBIE BIT(14) /*!< PLL2 stabilization interrupt enable */ 114 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ 115 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 116 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ 117 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 118 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 119 #define RCU_INT_PLL1STBIC BIT(21) /*!< PLL1 stabilization interrupt clear */ 120 #define RCU_INT_PLL2STBIC BIT(22) /*!< PLL2 stabilization interrupt clear */ 121 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 122 123 /* RCU_APB2RST */ 124 #define RCU_APB2RST_AFRST BIT(0) /*!< alternate function I/O reset */ 125 #define RCU_APB2RST_PARST BIT(2) /*!< GPIO port A reset */ 126 #define RCU_APB2RST_PBRST BIT(3) /*!< GPIO port B reset */ 127 #define RCU_APB2RST_PCRST BIT(4) /*!< GPIO port C reset */ 128 #define RCU_APB2RST_PDRST BIT(5) /*!< GPIO port D reset */ 129 #define RCU_APB2RST_PERST BIT(6) /*!< GPIO port E reset */ 130 #define RCU_APB2RST_PFRST BIT(7) /*!< GPIO port F reset */ 131 #define RCU_APB2RST_PGRST BIT(8) /*!< GPIO port G reset */ 132 #define RCU_APB2RST_ADC0RST BIT(9) /*!< ADC0 reset */ 133 #define RCU_APB2RST_ADC1RST BIT(10) /*!< ADC1 reset */ 134 #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ 135 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 136 #define RCU_APB2RST_TIMER7RST BIT(13) /*!< TIMER7 reset */ 137 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 138 #define RCU_APB2RST_ADC2RST BIT(15) /*!< ADC2 reset */ 139 #define RCU_APB2RST_TIMER8RST BIT(19) /*!< TIMER8 reset */ 140 #define RCU_APB2RST_TIMER9RST BIT(20) /*!< TIMER9 reset */ 141 #define RCU_APB2RST_TIMER10RST BIT(21) /*!< TIMER10 reset */ 142 143 /* RCU_APB1RST */ 144 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 reset */ 145 #define RCU_APB1RST_TIMER3RST BIT(2) /*!< TIMER3 reset */ 146 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 reset */ 147 #define RCU_APB1RST_TIMER6RST BIT(5) /*!< TIMER6 reset */ 148 #define RCU_APB1RST_TIMER11RST BIT(6) /*!< TIMER11 reset */ 149 #define RCU_APB1RST_TIMER12RST BIT(7) /*!< TIMER12 reset */ 150 #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 reset */ 151 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< WWDGT reset */ 152 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 153 #define RCU_APB1RST_SPI2RST BIT(15) /*!< SPI2 reset */ 154 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 155 #define RCU_APB1RST_USART2RST BIT(18) /*!< USART2 reset */ 156 #define RCU_APB1RST_UART3RST BIT(19) /*!< UART3 reset */ 157 #define RCU_APB1RST_UART4RST BIT(20) /*!< UART4 reset */ 158 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 159 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 160 #define RCU_APB1RST_CAN0RST BIT(25) /*!< CAN0 reset */ 161 #define RCU_APB1RST_CAN1RST BIT(26) /*!< CAN1 reset */ 162 #define RCU_APB1RST_BKPIRST BIT(27) /*!< backup interface reset */ 163 #define RCU_APB1RST_PMURST BIT(28) /*!< PMU reset */ 164 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 165 166 /* RCU_AHBEN */ 167 #define RCU_AHBEN_DMA0EN BIT(0) /*!< DMA0 clock enable */ 168 #define RCU_AHBEN_DMA1EN BIT(1) /*!< DMA1 clock enable */ 169 #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM clock enable when sleep mode */ 170 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable when sleep mode */ 171 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 172 #define RCU_AHBEN_EXMCEN BIT(8) /*!< EXMC clock enable */ 173 #define RCU_AHBEN_SDIOEN BIT(10) /*!< SDIO clock enable */ 174 #define RCU_AHBEN_USBFSEN BIT(12) /*!< USBFS clock enable */ 175 176 /* RCU_APB2EN */ 177 #define RCU_APB2EN_AFEN BIT(0) /*!< alternate function IO clock enable */ 178 #define RCU_APB2EN_PAEN BIT(2) /*!< GPIO port A clock enable */ 179 #define RCU_APB2EN_PBEN BIT(3) /*!< GPIO port B clock enable */ 180 #define RCU_APB2EN_PCEN BIT(4) /*!< GPIO port C clock enable */ 181 #define RCU_APB2EN_PDEN BIT(5) /*!< GPIO port D clock enable */ 182 #define RCU_APB2EN_PEEN BIT(6) /*!< GPIO port E clock enable */ 183 #define RCU_APB2EN_PFEN BIT(7) /*!< GPIO port F clock enable */ 184 #define RCU_APB2EN_PGEN BIT(8) /*!< GPIO port G clock enable */ 185 #define RCU_APB2EN_ADC0EN BIT(9) /*!< ADC0 clock enable */ 186 #define RCU_APB2EN_ADC1EN BIT(10) /*!< ADC1 clock enable */ 187 #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 clock enable */ 188 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 189 #define RCU_APB2EN_TIMER7EN BIT(13) /*!< TIMER7 clock enable */ 190 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 191 #define RCU_APB2EN_ADC2EN BIT(15) /*!< ADC2 clock enable */ 192 #define RCU_APB2EN_TIMER8EN BIT(19) /*!< TIMER8 clock enable */ 193 #define RCU_APB2EN_TIMER9EN BIT(20) /*!< TIMER9 clock enable */ 194 #define RCU_APB2EN_TIMER10EN BIT(21) /*!< TIMER10 clock enable */ 195 196 /* RCU_APB1EN */ 197 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 clock enable */ 198 #define RCU_APB1EN_TIMER3EN BIT(2) /*!< TIMER3 clock enable */ 199 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 clock enable */ 200 #define RCU_APB1EN_TIMER6EN BIT(5) /*!< TIMER6 clock enable */ 201 #define RCU_APB1EN_TIMER11EN BIT(6) /*!< TIMER11 clock enable */ 202 #define RCU_APB1EN_TIMER12EN BIT(7) /*!< TIMER12 clock enable */ 203 #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 clock enable */ 204 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< WWDGT clock enable */ 205 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 206 #define RCU_APB1EN_SPI2EN BIT(15) /*!< SPI2 clock enable */ 207 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 208 #define RCU_APB1EN_USART2EN BIT(18) /*!< USART2 clock enable */ 209 #define RCU_APB1EN_UART3EN BIT(19) /*!< UART3 clock enable */ 210 #define RCU_APB1EN_UART4EN BIT(20) /*!< UART4 clock enable */ 211 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 212 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 213 #define RCU_APB1EN_CAN0EN BIT(25) /*!< CAN0 clock enable */ 214 #define RCU_APB1EN_CAN1EN BIT(26) /*!< CAN1 clock enable */ 215 #define RCU_APB1EN_BKPIEN BIT(27) /*!< backup interface clock enable */ 216 #define RCU_APB1EN_PMUEN BIT(28) /*!< PMU clock enable */ 217 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC clock enable */ 218 219 /* RCU_BDCTL */ 220 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 221 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< low speed crystal oscillator stabilization flag */ 222 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 223 #define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ 224 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 225 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 226 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 227 228 /* RCU_RSTSCK */ 229 #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ 230 #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization flag */ 231 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 232 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 233 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 234 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 235 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 236 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 237 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 238 239 /* RCU_AHBRST */ 240 #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ 241 242 /* RCU_CFG1 */ 243 #define RCU_CFG1_PREDV0 BITS(0,3) /*!< PREDV0 division factor */ 244 #define RCU_CFG1_PREDV1 BITS(4,7) /*!< PREDV1 division factor */ 245 #define RCU_CFG1_PLL1MF BITS(8,11) /*!< PLL1 clock multiplication factor */ 246 #define RCU_CFG1_PLL2MF BITS(12,15) /*!< PLL2 clock multiplication factor */ 247 #define RCU_CFG1_PREDV0SEL BIT(16) /*!< PREDV0 input clock source selection */ 248 #define RCU_CFG1_I2S1SEL BIT(17) /*!< I2S1 clock source selection */ 249 #define RCU_CFG1_I2S2SEL BIT(18) /*!< I2S2 clock source selection */ 250 #define RCU_CFG1_ADCPSC_3 BIT(29) /*!< bit 4 of ADCPSC */ 251 #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source selection */ 252 #define RCU_CFG1_PLL2MF_4 BIT(31) /*!< bit 5 of PLL2MF */ 253 254 /* RCU_DSV */ 255 #define RCU_DSV_DSLPVS BITS(0,2) /*!< deep-sleep mode voltage select */ 256 257 /* RCU_ADDCTL */ 258 #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48MHz clock selection */ 259 #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< internal 48MHz RC oscillator enable */ 260 #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48MHz RC oscillator clock stabilization flag */ 261 #define RCU_ADDCTL_IRC48MCAL BITS(24,31) /*!< internal 48MHz RC oscillator calibration value register */ 262 263 /* RCU_ADDINT */ 264 #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ 265 #define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< internal 48 MHz RC oscillator stabilization interrupt enable */ 266 #define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 267 268 /* RCU_ADDAPB1RST */ 269 #define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC reset */ 270 271 /* RCU_ADDAPB1EN */ 272 #define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC clock enable */ 273 274 275 /* constants definitions */ 276 /* define the peripheral clock enable bit position and its register index offset */ 277 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 278 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph) >> 6))) 279 #define RCU_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 280 281 /* register offset */ 282 /* peripherals enable */ 283 #define AHBEN_REG_OFFSET 0x14U /*!< AHB enable register offset */ 284 #define APB1EN_REG_OFFSET 0x1CU /*!< APB1 enable register offset */ 285 #define APB2EN_REG_OFFSET 0x18U /*!< APB2 enable register offset */ 286 #define ADD_APB1EN_REG_OFFSET 0xE4U /*!< APB1 additional enable register offset */ 287 288 /* peripherals reset */ 289 #define AHBRST_REG_OFFSET 0x28U /*!< AHB reset register offset */ 290 #define APB1RST_REG_OFFSET 0x10U /*!< APB1 reset register offset */ 291 #define APB2RST_REG_OFFSET 0x0CU /*!< APB2 reset register offset */ 292 #define ADD_APB1RST_REG_OFFSET 0xE0U /*!< APB1 additional reset register offset */ 293 #define RSTSCK_REG_OFFSET 0x24U /*!< reset source/clock register offset */ 294 295 /* clock control */ 296 #define CTL_REG_OFFSET 0x00U /*!< control register offset */ 297 #define BDCTL_REG_OFFSET 0x20U /*!< backup domain control register offset */ 298 #define ADDCTL_REG_OFFSET 0xC0U /*!< additional clock control register offset */ 299 300 /* clock stabilization and stuck interrupt */ 301 #define INT_REG_OFFSET 0x08U /*!< clock interrupt register offset */ 302 #define ADDINT_REG_OFFSET 0xCCU /*!< additional clock interrupt register offset */ 303 304 /* configuration register */ 305 #define CFG0_REG_OFFSET 0x04U /*!< clock configuration register 0 offset */ 306 #define CFG1_REG_OFFSET 0x2CU /*!< clock configuration register 1 offset */ 307 308 /* peripheral clock enable */ 309 typedef enum 310 { 311 /* AHB peripherals */ 312 RCU_DMA0 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 0U), /*!< DMA0 clock */ 313 RCU_DMA1 = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 1U), /*!< DMA1 clock */ 314 RCU_CRC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 6U), /*!< CRC clock */ 315 RCU_EXMC = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 8U), /*!< EXMC clock */ 316 RCU_SDIO = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 10U), /*!< SDIO clock */ 317 RCU_USBFS = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 12U), /*!< USBFS clock */ 318 319 /* APB1 peripherals */ 320 RCU_TIMER2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 1U), /*!< TIMER2 clock */ 321 RCU_TIMER3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 2U), /*!< TIMER3 clock */ 322 RCU_TIMER5 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 4U), /*!< TIMER5 clock */ 323 RCU_TIMER6 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 5U), /*!< TIMER6 clock */ 324 RCU_TIMER11 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 6U), /*!< TIMER11 clock */ 325 RCU_TIMER12 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 7U), /*!< TIMER12 clock */ 326 RCU_TIMER13 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 8U), /*!< TIMER13 clock */ 327 RCU_WWDGT = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 11U), /*!< WWDGT clock */ 328 RCU_SPI1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 14U), /*!< SPI1 clock */ 329 RCU_SPI2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 15U), /*!< SPI2 clock */ 330 RCU_USART1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 17U), /*!< USART1 clock */ 331 RCU_USART2 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 18U), /*!< USART2 clock */ 332 RCU_UART3 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 19U), /*!< UART3 clock */ 333 RCU_UART4 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 20U), /*!< UART4 clock */ 334 RCU_I2C0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 21U), /*!< I2C0 clock */ 335 RCU_I2C1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 22U), /*!< I2C1 clock */ 336 RCU_CAN0 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 25U), /*!< CAN0 clock */ 337 RCU_CAN1 = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 26U), /*!< CAN1 clock */ 338 RCU_BKPI = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 27U), /*!< BKPI clock */ 339 RCU_PMU = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 28U), /*!< PMU clock */ 340 RCU_DAC = RCU_REGIDX_BIT(APB1EN_REG_OFFSET, 29U), /*!< DAC clock */ 341 RCU_RTC = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 15U), /*!< RTC clock */ 342 RCU_CTC = RCU_REGIDX_BIT(ADD_APB1EN_REG_OFFSET, 27U), /*!< CTC clock */ 343 344 /* APB2 peripherals */ 345 RCU_AF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 0U), /*!< alternate function clock */ 346 RCU_GPIOA = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 2U), /*!< GPIOA clock */ 347 RCU_GPIOB = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 3U), /*!< GPIOB clock */ 348 RCU_GPIOC = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 4U), /*!< GPIOC clock */ 349 RCU_GPIOD = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 5U), /*!< GPIOD clock */ 350 RCU_GPIOE = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 6U), /*!< GPIOE clock */ 351 RCU_GPIOF = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 7U), /*!< GPIOF clock */ 352 RCU_GPIOG = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 8U), /*!< GPIOG clock */ 353 RCU_ADC0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 9U), /*!< ADC0 clock */ 354 RCU_ADC1 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 10U), /*!< ADC1 clock */ 355 RCU_TIMER0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 11U), /*!< TIMER0 clock */ 356 RCU_SPI0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 12U), /*!< SPI0 clock */ 357 RCU_TIMER7 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 13U), /*!< TIMER7 clock */ 358 RCU_USART0 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 14U), /*!< USART0 clock */ 359 RCU_ADC2 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 15U), /*!< ADC2 clock */ 360 RCU_TIMER8 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 19U), /*!< TIMER8 clock */ 361 RCU_TIMER9 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 20U), /*!< TIMER9 clock */ 362 RCU_TIMER10 = RCU_REGIDX_BIT(APB2EN_REG_OFFSET, 21U), /*!< TIMER10 clock */ 363 }rcu_periph_enum; 364 365 /* peripheral clock enable when sleep mode*/ 366 typedef enum 367 { 368 /* AHB peripherals */ 369 RCU_SRAM_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 2U), /*!< SRAM clock */ 370 RCU_FMC_SLP = RCU_REGIDX_BIT(AHBEN_REG_OFFSET, 4U), /*!< FMC clock */ 371 }rcu_periph_sleep_enum; 372 373 /* peripherals reset */ 374 typedef enum 375 { 376 /* AHB peripherals */ 377 RCU_USBFSRST = RCU_REGIDX_BIT(AHBRST_REG_OFFSET, 12U), /*!< USBFS clock reset */ 378 379 /* APB1 peripherals */ 380 RCU_TIMER2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 1U), /*!< TIMER2 clock reset */ 381 RCU_TIMER3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 2U), /*!< TIMER3 clock reset */ 382 RCU_TIMER5RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 4U), /*!< TIMER5 clock reset */ 383 RCU_TIMER6RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 5U), /*!< TIMER6 clock reset */ 384 RCU_TIMER11RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 6U), /*!< TIMER11 clock reset */ 385 RCU_TIMER12RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 7U), /*!< TIMER12 clock reset */ 386 RCU_TIMER13RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 8U), /*!< TIMER13 clock reset */ 387 RCU_WWDGTRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 11U), /*!< WWDGT clock reset */ 388 RCU_SPI1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 14U), /*!< SPI1 clock reset */ 389 RCU_SPI2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 15U), /*!< SPI2 clock reset */ 390 RCU_USART1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 17U), /*!< USART1 clock reset */ 391 RCU_USART2RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 18U), /*!< USART2 clock reset */ 392 RCU_UART3RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 19U), /*!< UART3 clock reset */ 393 RCU_UART4RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 20U), /*!< UART4 clock reset */ 394 RCU_I2C0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 21U), /*!< I2C0 clock reset */ 395 RCU_I2C1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 22U), /*!< I2C1 clock reset */ 396 RCU_CAN0RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 25U), /*!< CAN0 clock reset */ 397 RCU_CAN1RST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 26U), /*!< CAN1 clock reset */ 398 RCU_BKPIRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 27U), /*!< BKPI clock reset */ 399 RCU_PMURST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 28U), /*!< PMU clock reset */ 400 RCU_DACRST = RCU_REGIDX_BIT(APB1RST_REG_OFFSET, 29U), /*!< DAC clock reset */ 401 RCU_CTCRST = RCU_REGIDX_BIT(ADD_APB1RST_REG_OFFSET, 27U), /*!< RTC clock reset */ 402 403 /* APB2 peripherals */ 404 RCU_AFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 0U), /*!< alternate function clock reset */ 405 RCU_GPIOARST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 2U), /*!< GPIOA clock reset */ 406 RCU_GPIOBRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 3U), /*!< GPIOB clock reset */ 407 RCU_GPIOCRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 4U), /*!< GPIOC clock reset */ 408 RCU_GPIODRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 5U), /*!< GPIOD clock reset */ 409 RCU_GPIOERST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 6U), /*!< GPIOE clock reset */ 410 RCU_GPIOFRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 7U), /*!< GPIOF clock reset */ 411 RCU_GPIOGRST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 8U), /*!< GPIOG clock reset */ 412 RCU_ADC0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 9U), /*!< ADC0 clock reset */ 413 RCU_ADC1RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 10U), /*!< ADC1 clock reset */ 414 RCU_TIMER0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 11U), /*!< TIMER0 clock reset */ 415 RCU_SPI0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 12U), /*!< SPI0 clock reset */ 416 RCU_TIMER7RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 13U), /*!< TIMER7 clock reset */ 417 RCU_USART0RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 14U), /*!< USART0 clock reset */ 418 RCU_ADC2RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 15U), /*!< ADC2 clock reset */ 419 RCU_TIMER8RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 19U), /*!< TIMER8 clock reset */ 420 RCU_TIMER9RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 20U), /*!< TIMER9 clock reset */ 421 RCU_TIMER10RST = RCU_REGIDX_BIT(APB2RST_REG_OFFSET, 21U), /*!< TIMER10 clock reset */ 422 }rcu_periph_reset_enum; 423 424 /* clock stabilization and peripheral reset flags */ 425 typedef enum 426 { 427 /* clock stabilization flags */ 428 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 1U), /*!< IRC8M stabilization flags */ 429 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 17U), /*!< HXTAL stabilization flags */ 430 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 25U), /*!< PLL stabilization flags */ 431 RCU_FLAG_PLL1STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 27U), /*!< PLL1 stabilization flags */ 432 RCU_FLAG_PLL2STB = RCU_REGIDX_BIT(CTL_REG_OFFSET, 29U), /*!< PLL2 stabilization flags */ 433 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 1U), /*!< LXTAL stabilization flags */ 434 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 1U), /*!< IRC40K stabilization flags */ 435 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 17U), /*!< IRC48M stabilization flags */ 436 /* reset source flags */ 437 RCU_FLAG_EPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 26U), /*!< external PIN reset flags */ 438 RCU_FLAG_PORRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 27U), /*!< power reset flags */ 439 RCU_FLAG_SWRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 28U), /*!< software reset flags */ 440 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 29U), /*!< FWDGT reset flags */ 441 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 30U), /*!< WWDGT reset flags */ 442 RCU_FLAG_LPRST = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 31U), /*!< low-power reset flags */ 443 }rcu_flag_enum; 444 445 /* clock stabilization and ckm interrupt flags */ 446 typedef enum 447 { 448 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 0U), /*!< IRC40K stabilization interrupt flag */ 449 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 1U), /*!< LXTAL stabilization interrupt flag */ 450 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 2U), /*!< IRC8M stabilization interrupt flag */ 451 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 3U), /*!< HXTAL stabilization interrupt flag */ 452 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 4U), /*!< PLL stabilization interrupt flag */ 453 RCU_INT_FLAG_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 5U), /*!< PLL1 stabilization interrupt flag */ 454 RCU_INT_FLAG_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 6U), /*!< PLL2 stabilization interrupt flag */ 455 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(INT_REG_OFFSET, 7U), /*!< HXTAL clock stuck interrupt flag */ 456 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 6U), /*!< IRC48M stabilization interrupt flag */ 457 }rcu_int_flag_enum; 458 459 /* clock stabilization and stuck interrupt flags clear */ 460 typedef enum 461 { 462 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 16U), /*!< IRC40K stabilization interrupt flags clear */ 463 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 17U), /*!< LXTAL stabilization interrupt flags clear */ 464 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 18U), /*!< IRC8M stabilization interrupt flags clear */ 465 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 19U), /*!< HXTAL stabilization interrupt flags clear */ 466 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 20U), /*!< PLL stabilization interrupt flags clear */ 467 RCU_INT_FLAG_PLL1STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 21U), /*!< PLL1 stabilization interrupt flags clear */ 468 RCU_INT_FLAG_PLL2STB_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 22U), /*!< PLL2 stabilization interrupt flags clear */ 469 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(INT_REG_OFFSET, 23U), /*!< CKM interrupt flags clear */ 470 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 22U), /*!< internal 48 MHz RC oscillator stabilization interrupt clear */ 471 }rcu_int_flag_clear_enum; 472 473 /* clock stabilization interrupt enable or disable */ 474 typedef enum 475 { 476 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 8U), /*!< IRC40K stabilization interrupt */ 477 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 9U), /*!< LXTAL stabilization interrupt */ 478 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 10U), /*!< IRC8M stabilization interrupt */ 479 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 11U), /*!< HXTAL stabilization interrupt */ 480 RCU_INT_PLLSTB = RCU_REGIDX_BIT(INT_REG_OFFSET, 12U), /*!< PLL stabilization interrupt */ 481 RCU_INT_PLL1STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 13U), /*!< PLL1 stabilization interrupt */ 482 RCU_INT_PLL2STB = RCU_REGIDX_BIT(INT_REG_OFFSET, 14U), /*!< PLL2 stabilization interrupt */ 483 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(ADDINT_REG_OFFSET, 14U), /*!< internal 48 MHz RC oscillator stabilization interrupt */ 484 }rcu_int_enum; 485 486 /* oscillator types */ 487 typedef enum 488 { 489 RCU_HXTAL = RCU_REGIDX_BIT(CTL_REG_OFFSET, 16U), /*!< HXTAL */ 490 RCU_LXTAL = RCU_REGIDX_BIT(BDCTL_REG_OFFSET, 0U), /*!< LXTAL */ 491 RCU_IRC8M = RCU_REGIDX_BIT(CTL_REG_OFFSET, 0U), /*!< IRC8M */ 492 RCU_IRC48M = RCU_REGIDX_BIT(ADDCTL_REG_OFFSET, 16U), /*!< IRC48M */ 493 RCU_IRC40K = RCU_REGIDX_BIT(RSTSCK_REG_OFFSET, 0U), /*!< IRC40K */ 494 RCU_PLL_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 24U), /*!< PLL */ 495 RCU_PLL1_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 26U), /*!< PLL1 */ 496 RCU_PLL2_CK = RCU_REGIDX_BIT(CTL_REG_OFFSET, 28U), /*!< PLL2 */ 497 }rcu_osci_type_enum; 498 499 /* rcu clock frequency */ 500 typedef enum 501 { 502 CK_SYS = 0, /*!< system clock */ 503 CK_AHB, /*!< AHB clock */ 504 CK_APB1, /*!< APB1 clock */ 505 CK_APB2, /*!< APB2 clock */ 506 }rcu_clock_freq_enum; 507 508 /* RCU_CFG0 register bit define */ 509 /* system clock source select */ 510 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 511 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ 512 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 513 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 514 515 /* system clock source select status */ 516 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 517 #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ 518 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 519 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLLP */ 520 521 /* AHB prescaler selection */ 522 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 523 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 524 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 525 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 526 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 527 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 528 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 529 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 530 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 531 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 532 533 /* APB1 prescaler selection */ 534 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 535 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 536 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 537 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 538 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 539 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 540 541 /* APB2 prescaler selection */ 542 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) 543 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 544 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 545 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 546 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 547 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 548 549 /* ADC prescaler select */ 550 #define RCU_CKADC_CKAPB2_DIV2 ((uint32_t)0x00000000U) /*!< ADC prescaler select CK_APB2/2 */ 551 #define RCU_CKADC_CKAPB2_DIV4 ((uint32_t)0x00000001U) /*!< ADC prescaler select CK_APB2/4 */ 552 #define RCU_CKADC_CKAPB2_DIV6 ((uint32_t)0x00000002U) /*!< ADC prescaler select CK_APB2/6 */ 553 #define RCU_CKADC_CKAPB2_DIV8 ((uint32_t)0x00000003U) /*!< ADC prescaler select CK_APB2/8 */ 554 #define RCU_CKADC_CKAPB2_DIV12 ((uint32_t)0x00000005U) /*!< ADC prescaler select CK_APB2/12 */ 555 #define RCU_CKADC_CKAPB2_DIV16 ((uint32_t)0x00000007U) /*!< ADC prescaler select CK_APB2/16 */ 556 #define RCU_CKADC_CKAHB_DIV5 ((uint32_t)0x00000008U) /*!< ADC prescaler select CK_AHB/5 */ 557 #define RCU_CKADC_CKAHB_DIV6 ((uint32_t)0x00000009U) /*!< ADC prescaler select CK_AHB/6 */ 558 #define RCU_CKADC_CKAHB_DIV10 ((uint32_t)0x0000000AU) /*!< ADC prescaler select CK_AHB/10 */ 559 #define RCU_CKADC_CKAHB_DIV20 ((uint32_t)0x0000000BU) /*!< ADC prescaler select CK_AHB/20 */ 560 561 /* PLL clock source selection */ 562 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< IRC8M/2 clock selected as source clock of PLL */ 563 #define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< HXTAL or IRC48M selected as source clock of PLL */ 564 565 /* PLL clock multiplication factor */ 566 #define PLLMF_4 RCU_CFG0_PLLMF_4 /* bit 4 of PLLMF */ 567 #define PLLMF_5 RCU_CFG0_PLLMF_5 /* bit 5 of PLLMF */ 568 #define PLLMF_4_5 (PLLMF_4 | PLLMF_5) /* bit 4 and 5 of PLLMF */ 569 570 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) 571 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ 572 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ 573 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ 574 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ 575 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ 576 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ 577 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ 578 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ 579 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ 580 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ 581 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ 582 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ 583 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ 584 #define RCU_PLL_MUL6_5 CFG0_PLLMF(13) /*!< PLL source clock multiply by 6.5 */ 585 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ 586 #define RCU_PLL_MUL17 (PLLMF_4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ 587 #define RCU_PLL_MUL18 (PLLMF_4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ 588 #define RCU_PLL_MUL19 (PLLMF_4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ 589 #define RCU_PLL_MUL20 (PLLMF_4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ 590 #define RCU_PLL_MUL21 (PLLMF_4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ 591 #define RCU_PLL_MUL22 (PLLMF_4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ 592 #define RCU_PLL_MUL23 (PLLMF_4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ 593 #define RCU_PLL_MUL24 (PLLMF_4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ 594 #define RCU_PLL_MUL25 (PLLMF_4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ 595 #define RCU_PLL_MUL26 (PLLMF_4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ 596 #define RCU_PLL_MUL27 (PLLMF_4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ 597 #define RCU_PLL_MUL28 (PLLMF_4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ 598 #define RCU_PLL_MUL29 (PLLMF_4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ 599 #define RCU_PLL_MUL30 (PLLMF_4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ 600 #define RCU_PLL_MUL31 (PLLMF_4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ 601 #define RCU_PLL_MUL32 (PLLMF_4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ 602 #define RCU_PLL_MUL33 (PLLMF_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 33 */ 603 #define RCU_PLL_MUL34 (PLLMF_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 34 */ 604 #define RCU_PLL_MUL35 (PLLMF_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 35 */ 605 #define RCU_PLL_MUL36 (PLLMF_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 36 */ 606 #define RCU_PLL_MUL37 (PLLMF_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 37 */ 607 #define RCU_PLL_MUL38 (PLLMF_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 38 */ 608 #define RCU_PLL_MUL39 (PLLMF_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 39 */ 609 #define RCU_PLL_MUL40 (PLLMF_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 40 */ 610 #define RCU_PLL_MUL41 (PLLMF_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 41 */ 611 #define RCU_PLL_MUL42 (PLLMF_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 42 */ 612 #define RCU_PLL_MUL43 (PLLMF_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 43 */ 613 #define RCU_PLL_MUL44 (PLLMF_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 44 */ 614 #define RCU_PLL_MUL45 (PLLMF_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 45 */ 615 #define RCU_PLL_MUL46 (PLLMF_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 46 */ 616 #define RCU_PLL_MUL47 (PLLMF_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 47 */ 617 #define RCU_PLL_MUL48 (PLLMF_5 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 48 */ 618 #define RCU_PLL_MUL49 (PLLMF_4_5 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 49 */ 619 #define RCU_PLL_MUL50 (PLLMF_4_5 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 50 */ 620 #define RCU_PLL_MUL51 (PLLMF_4_5 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 51 */ 621 #define RCU_PLL_MUL52 (PLLMF_4_5 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 52 */ 622 #define RCU_PLL_MUL53 (PLLMF_4_5 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 53 */ 623 #define RCU_PLL_MUL54 (PLLMF_4_5 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 54 */ 624 #define RCU_PLL_MUL55 (PLLMF_4_5 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 55 */ 625 #define RCU_PLL_MUL56 (PLLMF_4_5 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 56 */ 626 #define RCU_PLL_MUL57 (PLLMF_4_5 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 57 */ 627 #define RCU_PLL_MUL58 (PLLMF_4_5 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 58 */ 628 #define RCU_PLL_MUL59 (PLLMF_4_5 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 59 */ 629 #define RCU_PLL_MUL60 (PLLMF_4_5 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 60 */ 630 #define RCU_PLL_MUL61 (PLLMF_4_5 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 61 */ 631 #define RCU_PLL_MUL62 (PLLMF_4_5 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 62 */ 632 #define RCU_PLL_MUL63 (PLLMF_4_5 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 63 */ 633 634 #define USBPSC_2 RCU_CFG0_USBFSPSC_2 635 /* USBD/USBFS prescaler select */ 636 #define CFG0_USBPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) 637 #define RCU_CKUSB_CKPLL_DIV1_5 CFG0_USBPSC(0) /*!< USBFS prescaler select CK_PLL/1.5 */ 638 #define RCU_CKUSB_CKPLL_DIV1 CFG0_USBPSC(1) /*!< USBFS prescaler select CK_PLL/1 */ 639 #define RCU_CKUSB_CKPLL_DIV2_5 CFG0_USBPSC(2) /*!< USBFS prescaler select CK_PLL/2.5 */ 640 #define RCU_CKUSB_CKPLL_DIV2 CFG0_USBPSC(3) /*!< USBFS prescaler select CK_PLL/2 */ 641 #define RCU_CKUSB_CKPLL_DIV3 (USBPSC_2 |CFG0_USBPSC(0)) /*!< USBFS prescaler select CK_PLL/3 */ 642 #define RCU_CKUSB_CKPLL_DIV3_5 (USBPSC_2 |CFG0_USBPSC(1)) /*!< USBFS prescaler select CK_PLL/3.5 */ 643 #define RCU_CKUSB_CKPLL_DIV4 (USBPSC_2 |CFG0_USBPSC(2)) /*!< USBFS prescaler select CK_PLL/4 */ 644 645 /* CKOUT0 Clock source selection */ 646 #define CFG0_CKOUT0SEL(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 647 #define RCU_CKOUT0SRC_NONE CFG0_CKOUT0SEL(0) /*!< no clock selected */ 648 #define RCU_CKOUT0SRC_CKSYS CFG0_CKOUT0SEL(4) /*!< system clock selected */ 649 #define RCU_CKOUT0SRC_IRC8M CFG0_CKOUT0SEL(5) /*!< internal 8M RC oscillator clock selected */ 650 #define RCU_CKOUT0SRC_HXTAL CFG0_CKOUT0SEL(6) /*!< high speed crystal oscillator clock (HXTAL) selected */ 651 #define RCU_CKOUT0SRC_CKPLL_DIV2 CFG0_CKOUT0SEL(7) /*!< CK_PLL/2 clock selected */ 652 #define RCU_CKOUT0SRC_CKPLL1 CFG0_CKOUT0SEL(8) /*!< CK_PLL1 clock selected */ 653 #define RCU_CKOUT0SRC_CKPLL2_DIV2 CFG0_CKOUT0SEL(9) /*!< CK_PLL2/2 clock selected */ 654 #define RCU_CKOUT0SRC_EXT1 CFG0_CKOUT0SEL(10) /*!< EXT1 selected, to provide the external clock for ENET */ 655 #define RCU_CKOUT0SRC_CKPLL2 CFG0_CKOUT0SEL(11) /*!< CK_PLL2 clock selected */ 656 657 /* LXTAL drive capability */ 658 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) 659 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ 660 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ 661 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ 662 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ 663 664 /* RTC clock entry selection */ 665 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 666 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 667 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< RTC source clock select LXTAL */ 668 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< RTC source clock select IRC40K */ 669 #define RCU_RTCSRC_HXTAL_DIV_128 BDCTL_RTCSRC(3) /*!< RTC source clock select HXTAL/128 */ 670 671 /* PREDV0 division factor */ 672 #define CFG1_PREDV0(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 673 #define RCU_PREDV0_DIV1 CFG1_PREDV0(0) /*!< PREDV0 input source clock not divided */ 674 #define RCU_PREDV0_DIV2 CFG1_PREDV0(1) /*!< PREDV0 input source clock divided by 2 */ 675 #define RCU_PREDV0_DIV3 CFG1_PREDV0(2) /*!< PREDV0 input source clock divided by 3 */ 676 #define RCU_PREDV0_DIV4 CFG1_PREDV0(3) /*!< PREDV0 input source clock divided by 4 */ 677 #define RCU_PREDV0_DIV5 CFG1_PREDV0(4) /*!< PREDV0 input source clock divided by 5 */ 678 #define RCU_PREDV0_DIV6 CFG1_PREDV0(5) /*!< PREDV0 input source clock divided by 6 */ 679 #define RCU_PREDV0_DIV7 CFG1_PREDV0(6) /*!< PREDV0 input source clock divided by 7 */ 680 #define RCU_PREDV0_DIV8 CFG1_PREDV0(7) /*!< PREDV0 input source clock divided by 8 */ 681 #define RCU_PREDV0_DIV9 CFG1_PREDV0(8) /*!< PREDV0 input source clock divided by 9 */ 682 #define RCU_PREDV0_DIV10 CFG1_PREDV0(9) /*!< PREDV0 input source clock divided by 10 */ 683 #define RCU_PREDV0_DIV11 CFG1_PREDV0(10) /*!< PREDV0 input source clock divided by 11 */ 684 #define RCU_PREDV0_DIV12 CFG1_PREDV0(11) /*!< PREDV0 input source clock divided by 12 */ 685 #define RCU_PREDV0_DIV13 CFG1_PREDV0(12) /*!< PREDV0 input source clock divided by 13 */ 686 #define RCU_PREDV0_DIV14 CFG1_PREDV0(13) /*!< PREDV0 input source clock divided by 14 */ 687 #define RCU_PREDV0_DIV15 CFG1_PREDV0(14) /*!< PREDV0 input source clock divided by 15 */ 688 #define RCU_PREDV0_DIV16 CFG1_PREDV0(15) /*!< PREDV0 input source clock divided by 16 */ 689 690 /* PREDV1 division factor */ 691 #define CFG1_PREDV1(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 692 #define RCU_PREDV1_DIV1 CFG1_PREDV1(0) /*!< PREDV1 input source clock not divided */ 693 #define RCU_PREDV1_DIV2 CFG1_PREDV1(1) /*!< PREDV1 input source clock divided by 2 */ 694 #define RCU_PREDV1_DIV3 CFG1_PREDV1(2) /*!< PREDV1 input source clock divided by 3 */ 695 #define RCU_PREDV1_DIV4 CFG1_PREDV1(3) /*!< PREDV1 input source clock divided by 4 */ 696 #define RCU_PREDV1_DIV5 CFG1_PREDV1(4) /*!< PREDV1 input source clock divided by 5 */ 697 #define RCU_PREDV1_DIV6 CFG1_PREDV1(5) /*!< PREDV1 input source clock divided by 6 */ 698 #define RCU_PREDV1_DIV7 CFG1_PREDV1(6) /*!< PREDV1 input source clock divided by 7 */ 699 #define RCU_PREDV1_DIV8 CFG1_PREDV1(7) /*!< PREDV1 input source clock divided by 8 */ 700 #define RCU_PREDV1_DIV9 CFG1_PREDV1(8) /*!< PREDV1 input source clock divided by 9 */ 701 #define RCU_PREDV1_DIV10 CFG1_PREDV1(9) /*!< PREDV1 input source clock divided by 10 */ 702 #define RCU_PREDV1_DIV11 CFG1_PREDV1(10) /*!< PREDV1 input source clock divided by 11 */ 703 #define RCU_PREDV1_DIV12 CFG1_PREDV1(11) /*!< PREDV1 input source clock divided by 12 */ 704 #define RCU_PREDV1_DIV13 CFG1_PREDV1(12) /*!< PREDV1 input source clock divided by 13 */ 705 #define RCU_PREDV1_DIV14 CFG1_PREDV1(13) /*!< PREDV1 input source clock divided by 14 */ 706 #define RCU_PREDV1_DIV15 CFG1_PREDV1(14) /*!< PREDV1 input source clock divided by 15 */ 707 #define RCU_PREDV1_DIV16 CFG1_PREDV1(15) /*!< PREDV1 input source clock divided by 16 */ 708 709 /* PLL1 clock multiplication factor */ 710 #define CFG1_PLL1MF(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) 711 #define RCU_PLL1_MUL8 CFG1_PLL1MF(6) /*!< PLL1 source clock multiply by 8 */ 712 #define RCU_PLL1_MUL9 CFG1_PLL1MF(7) /*!< PLL1 source clock multiply by 9 */ 713 #define RCU_PLL1_MUL10 CFG1_PLL1MF(8) /*!< PLL1 source clock multiply by 10 */ 714 #define RCU_PLL1_MUL11 CFG1_PLL1MF(9) /*!< PLL1 source clock multiply by 11 */ 715 #define RCU_PLL1_MUL12 CFG1_PLL1MF(10) /*!< PLL1 source clock multiply by 12 */ 716 #define RCU_PLL1_MUL13 CFG1_PLL1MF(11) /*!< PLL1 source clock multiply by 13 */ 717 #define RCU_PLL1_MUL14 CFG1_PLL1MF(12) /*!< PLL1 source clock multiply by 14 */ 718 #define RCU_PLL1_MUL15 CFG1_PLL1MF(13) /*!< PLL1 source clock multiply by 15 */ 719 #define RCU_PLL1_MUL16 CFG1_PLL1MF(14) /*!< PLL1 source clock multiply by 16 */ 720 #define RCU_PLL1_MUL20 CFG1_PLL1MF(15) /*!< PLL1 source clock multiply by 20 */ 721 722 /* PLL2 clock multiplication factor */ 723 #define PLL2MF_4 RCU_CFG1_PLL2MF_4 /* bit 4 of PLL2MF */ 724 725 #define CFG1_PLL2MF(regval) (BITS(12,15) & ((uint32_t)(regval) << 12)) 726 #define RCU_PLL2_MUL8 CFG1_PLL2MF(6) /*!< PLL2 source clock multiply by 8 */ 727 #define RCU_PLL2_MUL9 CFG1_PLL2MF(7) /*!< PLL2 source clock multiply by 9 */ 728 #define RCU_PLL2_MUL10 CFG1_PLL2MF(8) /*!< PLL2 source clock multiply by 10 */ 729 #define RCU_PLL2_MUL11 CFG1_PLL2MF(9) /*!< PLL2 source clock multiply by 11 */ 730 #define RCU_PLL2_MUL12 CFG1_PLL2MF(10) /*!< PLL2 source clock multiply by 12 */ 731 #define RCU_PLL2_MUL13 CFG1_PLL2MF(11) /*!< PLL2 source clock multiply by 13 */ 732 #define RCU_PLL2_MUL14 CFG1_PLL2MF(12) /*!< PLL2 source clock multiply by 14 */ 733 #define RCU_PLL2_MUL15 CFG1_PLL2MF(13) /*!< PLL2 source clock multiply by 15 */ 734 #define RCU_PLL2_MUL16 CFG1_PLL2MF(14) /*!< PLL2 source clock multiply by 16 */ 735 #define RCU_PLL2_MUL20 CFG1_PLL2MF(15) /*!< PLL2 source clock multiply by 20 */ 736 #define RCU_PLL2_MUL18 (PLL2MF_4 | CFG1_PLL2MF(0)) /*!< PLL2 source clock multiply by 18 */ 737 #define RCU_PLL2_MUL19 (PLL2MF_4 | CFG1_PLL2MF(1)) /*!< PLL2 source clock multiply by 19 */ 738 #define RCU_PLL2_MUL21 (PLL2MF_4 | CFG1_PLL2MF(3)) /*!< PLL2 source clock multiply by 21 */ 739 #define RCU_PLL2_MUL22 (PLL2MF_4 | CFG1_PLL2MF(4)) /*!< PLL2 source clock multiply by 22 */ 740 #define RCU_PLL2_MUL23 (PLL2MF_4 | CFG1_PLL2MF(5)) /*!< PLL2 source clock multiply by 23 */ 741 #define RCU_PLL2_MUL24 (PLL2MF_4 | CFG1_PLL2MF(6)) /*!< PLL2 source clock multiply by 24 */ 742 #define RCU_PLL2_MUL25 (PLL2MF_4 | CFG1_PLL2MF(7)) /*!< PLL2 source clock multiply by 25 */ 743 #define RCU_PLL2_MUL26 (PLL2MF_4 | CFG1_PLL2MF(8)) /*!< PLL2 source clock multiply by 26 */ 744 #define RCU_PLL2_MUL27 (PLL2MF_4 | CFG1_PLL2MF(9)) /*!< PLL2 source clock multiply by 27 */ 745 #define RCU_PLL2_MUL28 (PLL2MF_4 | CFG1_PLL2MF(10)) /*!< PLL2 source clock multiply by 28 */ 746 #define RCU_PLL2_MUL29 (PLL2MF_4 | CFG1_PLL2MF(11)) /*!< PLL2 source clock multiply by 29 */ 747 #define RCU_PLL2_MUL30 (PLL2MF_4 | CFG1_PLL2MF(12)) /*!< PLL2 source clock multiply by 30 */ 748 #define RCU_PLL2_MUL31 (PLL2MF_4 | CFG1_PLL2MF(13)) /*!< PLL2 source clock multiply by 31 */ 749 #define RCU_PLL2_MUL32 (PLL2MF_4 | CFG1_PLL2MF(14)) /*!< PLL2 source clock multiply by 32 */ 750 #define RCU_PLL2_MUL40 (PLL2MF_4 | CFG1_PLL2MF(15)) /*!< PLL2 source clock multiply by 40 */ 751 752 /* PREDV0 input clock source selection */ 753 #define RCU_PREDV0SRC_HXTAL_IRC48M ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M selected as PREDV0 input source clock */ 754 #define RCU_PREDV0SRC_CKPLL1 RCU_CFG1_PREDV0SEL /*!< CK_PLL1 selected as PREDV0 input source clock */ 755 756 /* I2S1 clock source selection */ 757 #define RCU_I2S1SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S1 source clock */ 758 #define RCU_I2S1SRC_CKPLL2_MUL2 RCU_CFG1_I2S1SEL /*!< (CK_PLL2 x 2) selected as I2S1 source clock */ 759 760 /* I2S2 clock source selection */ 761 #define RCU_I2S2SRC_CKSYS ((uint32_t)0x00000000U) /*!< system clock selected as I2S2 source clock */ 762 #define RCU_I2S2SRC_CKPLL2_MUL2 RCU_CFG1_I2S2SEL /*!< (CK_PLL2 x 2) selected as I2S2 source clock */ 763 764 /* PLL input clock source selection */ 765 #define RCU_PLLPRESRC_HXTAL ((uint32_t)0x00000000U) /*!< HXTAL selected as PLL source clock */ 766 #define RCU_PLLPRESRC_IRC48M RCU_CFG1_PLLPRESEL /*!< CK_PLL selected as PREDV0 input source clock */ 767 768 /* deep-sleep mode voltage */ 769 #define DSV_DSLPVS(regval) (BITS(0,2) & ((uint32_t)(regval) << 0)) 770 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ 771 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ 772 #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ 773 #define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ 774 775 /* 48MHz clock selection */ 776 #define RCU_CK48MSRC_CKPLL ((uint32_t)0x00000000U) /*!< use CK_PLL clock */ 777 #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< select IRC48M clock */ 778 779 /* function declarations */ 780 /* deinitialize the RCU */ 781 void rcu_deinit(void); 782 /* enable the peripherals clock */ 783 void rcu_periph_clock_enable(rcu_periph_enum periph); 784 /* disable the peripherals clock */ 785 void rcu_periph_clock_disable(rcu_periph_enum periph); 786 /* enable the peripherals clock when sleep mode */ 787 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 788 /* disable the peripherals clock when sleep mode */ 789 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 790 /* reset the peripherals */ 791 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 792 /* disable reset the peripheral */ 793 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 794 /* reset the BKP domain */ 795 void rcu_bkp_reset_enable(void); 796 /* disable the BKP domain reset */ 797 void rcu_bkp_reset_disable(void); 798 799 /* configure the system clock source */ 800 void rcu_system_clock_source_config(uint32_t ck_sys); 801 /* get the system clock source */ 802 uint32_t rcu_system_clock_source_get(void); 803 /* configure the AHB prescaler selection */ 804 void rcu_ahb_clock_config(uint32_t ck_ahb); 805 /* configure the APB1 prescaler selection */ 806 void rcu_apb1_clock_config(uint32_t ck_apb1); 807 /* configure the APB2 prescaler selection */ 808 void rcu_apb2_clock_config(uint32_t ck_apb2); 809 /* configure the CK_OUT0 clock source and divider */ 810 void rcu_ckout0_config(uint32_t ckout0_src); 811 /* configure the PLL clock source selection and PLL multiply factor */ 812 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 813 /* configure the PLL clock source preselection */ 814 void rcu_pllpresel_config(uint32_t pll_presel); 815 /* configure the PREDV0 division factor and clock source */ 816 void rcu_predv0_config(uint32_t predv0_source, uint32_t predv0_div); 817 /* configure the PREDV1 division factor */ 818 void rcu_predv1_config(uint32_t predv1_div); 819 /* configure the PLL1 clock */ 820 void rcu_pll1_config(uint32_t pll_mul); 821 /* configure the PLL2 clock */ 822 void rcu_pll2_config(uint32_t pll_mul); 823 824 /* configure the ADC division factor */ 825 void rcu_adc_clock_config(uint32_t adc_psc); 826 /* configure the USBD/USBFS prescaler factor */ 827 void rcu_usb_clock_config(uint32_t usb_psc); 828 /* configure the RTC clock source selection */ 829 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 830 /* configure the I2S1 clock source selection */ 831 void rcu_i2s1_clock_config(uint32_t i2s_clock_source); 832 /* configure the I2S2 clock source selection */ 833 void rcu_i2s2_clock_config(uint32_t i2s_clock_source); 834 /* configure the CK48M clock selection */ 835 void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); 836 837 838 /* get the clock stabilization and periphral reset flags */ 839 FlagStatus rcu_flag_get(rcu_flag_enum flag); 840 /* clear the reset flag */ 841 void rcu_all_reset_flag_clear(void); 842 /* get the clock stabilization interrupt and ckm flags */ 843 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 844 /* clear the interrupt flags */ 845 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag); 846 /* enable the stabilization interrupt */ 847 void rcu_interrupt_enable(rcu_int_enum interrupt); 848 /* disable the stabilization interrupt */ 849 void rcu_interrupt_disable(rcu_int_enum interrupt); 850 851 /* configure the LXTAL drive capability */ 852 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 853 /* wait for oscillator stabilization flags is SET or oscillator startup is timeout */ 854 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 855 /* turn on the oscillator */ 856 void rcu_osci_on(rcu_osci_type_enum osci); 857 /* turn off the oscillator */ 858 void rcu_osci_off(rcu_osci_type_enum osci); 859 /* enable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 860 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 861 /* disable the oscillator bypass mode, HXTALEN or LXTALEN must be reset before it */ 862 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 863 /* enable the HXTAL clock monitor */ 864 void rcu_hxtal_clock_monitor_enable(void); 865 /* disable the HXTAL clock monitor */ 866 void rcu_hxtal_clock_monitor_disable(void); 867 868 /* set the IRC8M adjust value */ 869 void rcu_irc8m_adjust_value_set(uint32_t irc8m_adjval); 870 871 /* set the deep sleep mode voltage */ 872 void rcu_deepsleep_voltage_set(uint32_t dsvol); 873 874 /* get the system clock, bus and peripheral clock frequency */ 875 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 876 877 #endif /* GD32F403_RCU_H */ 878
