1 /*! 2 \file gd32f403_fmc.h 3 \brief definitions for the FMC 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F403_FMC_H 38 #define GD32F403_FMC_H 39 40 #include "gd32f403.h" 41 42 /* FMC and option byte definition */ 43 #define FMC FMC_BASE /*!< FMC register base address */ 44 #define OB OB_BASE /*!< option bytes base address */ 45 46 /* registers definitions */ 47 #define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */ 48 #define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */ 49 #define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */ 50 #define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */ 51 #define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */ 52 #define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */ 53 #define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */ 54 #define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */ 55 #define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */ 56 #define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */ 57 #define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */ 58 #define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */ 59 #define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */ 60 #define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */ 61 62 #define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */ 63 #define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/ 64 #define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */ 65 #define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */ 66 #define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */ 67 #define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */ 68 69 /* bits definitions */ 70 /* FMC_WS */ 71 #define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */ 72 73 /* FMC_KEY0 */ 74 #define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */ 75 76 /* FMC_OBKEY */ 77 #define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */ 78 79 /* FMC_STAT0 */ 80 #define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */ 81 #define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */ 82 #define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */ 83 #define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */ 84 85 /* FMC_CTL0 */ 86 #define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */ 87 #define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */ 88 #define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */ 89 #define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */ 90 #define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */ 91 #define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */ 92 #define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */ 93 #define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */ 94 #define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */ 95 #define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ 96 97 /* FMC_ADDR0 */ 98 #define FMC_ADDR0_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ 99 100 /* FMC_OBSTAT */ 101 #define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */ 102 #define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */ 103 #define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */ 104 #define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */ 105 106 /* FMC_WP */ 107 #define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */ 108 109 /* FMC_KEY1 */ 110 #define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */ 111 112 /* FMC_STAT1 */ 113 #define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */ 114 #define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */ 115 #define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */ 116 #define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */ 117 118 /* FMC_CTL1 */ 119 #define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */ 120 #define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */ 121 #define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */ 122 #define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */ 123 #define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */ 124 #define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */ 125 #define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */ 126 127 /* FMC_ADDR1 */ 128 #define FMC_ADDR1_ADDR BITS(0,31) /*!< Flash erase/program command address bits */ 129 130 /* FMC_WSEN */ 131 #define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */ 132 #define FMC_WSEN_BPEN BIT(1) /*!< FMC bit program enable bit */ 133 134 /* FMC_PID */ 135 #define FMC_PID_PID BITS(0,31) /*!< product ID bits */ 136 137 /* constants definitions */ 138 /* define the FMC bit position and its register index offset */ 139 #define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 140 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) 141 #define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 142 #define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) 143 #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) 144 #define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) 145 #define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) 146 #define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12) 147 148 /* configuration register */ 149 #define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */ 150 #define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */ 151 #define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */ 152 #define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */ 153 #define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */ 154 155 /* fmc state */ 156 typedef enum 157 { 158 FMC_READY, /*!< the operation has been completed */ 159 FMC_BUSY, /*!< the operation is in progress */ 160 FMC_PGERR, /*!< program error */ 161 FMC_WPERR, /*!< erase/program protection error */ 162 FMC_TOERR, /*!< timeout error */ 163 }fmc_state_enum; 164 165 /* FMC interrupt enable */ 166 typedef enum 167 { 168 FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */ 169 FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */ 170 FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */ 171 FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */ 172 }fmc_int_enum; 173 174 /* FMC flags */ 175 typedef enum 176 { 177 FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */ 178 FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */ 179 FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */ 180 FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */ 181 FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */ 182 FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */ 183 FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */ 184 FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */ 185 FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */ 186 }fmc_flag_enum; 187 188 /* FMC interrupt flags */ 189 typedef enum 190 { 191 FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */ 192 FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */ 193 FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */ 194 FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */ 195 FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */ 196 FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */ 197 }fmc_interrupt_flag_enum; 198 199 /* unlock key */ 200 #define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */ 201 #define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */ 202 203 /* FMC wait state counter */ 204 #define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval))) 205 #define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */ 206 #define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */ 207 #define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */ 208 209 /* option bytes software/hardware free watch dog timer */ 210 #define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */ 211 #define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */ 212 213 /* option bytes reset or not entering deep sleep mode */ 214 #define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */ 215 #define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */ 216 217 /* option bytes reset or not entering standby mode */ 218 #define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */ 219 #define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */ 220 221 /* option bytes boot bank value */ 222 #define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */ 223 #define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */ 224 225 #define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */ 226 227 /* read protect configure */ 228 #define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */ 229 #define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */ 230 231 /* OB_SPC */ 232 #define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */ 233 #define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */ 234 235 /* OB_USER */ 236 #define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */ 237 #define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */ 238 239 /* OB_WP0 */ 240 #define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */ 241 242 /* OB_WP1 */ 243 #define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */ 244 245 /* OB_WP2 */ 246 #define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */ 247 248 /* OB_WP3 */ 249 #define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */ 250 251 /* option bytes write protection */ 252 #define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */ 253 #define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */ 254 #define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */ 255 #define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */ 256 #define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */ 257 #define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */ 258 #define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */ 259 #define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */ 260 #define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */ 261 #define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */ 262 #define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */ 263 #define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */ 264 #define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */ 265 #define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */ 266 #define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */ 267 #define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */ 268 #define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */ 269 #define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */ 270 #define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */ 271 #define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */ 272 #define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */ 273 #define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */ 274 #define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */ 275 #define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */ 276 #define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */ 277 #define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */ 278 #define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */ 279 #define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */ 280 #define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */ 281 #define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */ 282 #define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */ 283 #define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */ 284 #define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */ 285 286 /* FMC timeout */ 287 #define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */ 288 289 /* FMC BANK address */ 290 #define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */ 291 #define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */ 292 #define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */ 293 294 /* function declarations */ 295 /* FMC main memory programming functions */ 296 /* set the FMC wait state counter */ 297 void fmc_wscnt_set(uint32_t wscnt); 298 /* unlock the main FMC operation */ 299 void fmc_unlock(void); 300 /* unlock the FMC bank0 operation */ 301 void fmc_bank0_unlock(void); 302 /* unlock the FMC bank1 operation */ 303 void fmc_bank1_unlock(void); 304 /* lock the main FMC operation */ 305 void fmc_lock(void); 306 /* lock the bank0 FMC operation */ 307 void fmc_bank0_lock(void); 308 /* lock the bank1 FMC operation */ 309 void fmc_bank1_lock(void); 310 /* FMC erase page */ 311 fmc_state_enum fmc_page_erase(uint32_t page_address); 312 /* FMC erase whole chip */ 313 fmc_state_enum fmc_mass_erase(void); 314 /* FMC erase whole bank0 */ 315 fmc_state_enum fmc_bank0_erase(void); 316 /* FMC erase whole bank1 */ 317 fmc_state_enum fmc_bank1_erase(void); 318 /* FMC program a word at the corresponding address */ 319 fmc_state_enum fmc_word_program(uint32_t address, uint32_t data); 320 /* FMC program a half word at the corresponding address */ 321 fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data); 322 /* FMC reprogram a word at the corresponding address without erasing */ 323 fmc_state_enum fmc_word_reprogram(uint32_t address, uint32_t data); 324 325 /* FMC option bytes programming functions */ 326 /* unlock the option byte operation */ 327 void ob_unlock(void); 328 /* lock the option byte operation */ 329 void ob_lock(void); 330 /* erase the option byte */ 331 fmc_state_enum ob_erase(void); 332 /* enable write protect */ 333 fmc_state_enum ob_write_protection_enable(uint32_t ob_wp); 334 /* configure the option byte security protection */ 335 fmc_state_enum ob_security_protection_config(uint8_t ob_spc); 336 /* write the FMC option byte */ 337 fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot); 338 /* program option bytes data */ 339 fmc_state_enum ob_data_program(uint32_t address, uint8_t data); 340 /* get the FMC option byte user */ 341 uint8_t ob_user_get(void); 342 /* get OB_DATA in register FMC_OBSTAT */ 343 uint16_t ob_data_get(void); 344 /* get the FMC option byte write protection */ 345 uint32_t ob_write_protection_get(void); 346 /* get option byte security protection code value */ 347 FlagStatus ob_spc_get(void); 348 349 /* FMC interrupts and flags management functions */ 350 /* enable FMC interrupt */ 351 void fmc_interrupt_enable(uint32_t interrupt); 352 /* disable FMC interrupt */ 353 void fmc_interrupt_disable(uint32_t interrupt); 354 /* check flag is set or not */ 355 FlagStatus fmc_flag_get(uint32_t flag); 356 /* clear the FMC flag */ 357 void fmc_flag_clear(uint32_t flag); 358 /* get FMC interrupt flag state */ 359 FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag); 360 /* clear FMC interrupt flag state */ 361 void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag); 362 /* return the FMC bank0 state */ 363 fmc_state_enum fmc_bank0_state_get(void); 364 /* return the FMC bank1 state */ 365 fmc_state_enum fmc_bank1_state_get(void); 366 /* check FMC bank0 ready or not */ 367 fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout); 368 /* check FMC bank1 ready or not */ 369 fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout); 370 371 #endif /* GD32F403_FMC_H */ 372
