1 /*! 2 \file gd32f403_dbg.h 3 \brief definitions for the DBG 4 5 \version 2017-02-10, V1.0.0, firmware for gd32f403 6 \version 2018-12-25, V2.0.0, firmware for gd32f403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 \version 2020-12-14, V2.1.1, firmware for gd32f403 9 */ 10 11 /* 12 Copyright (c) 2020, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F403_DBG_H 39 #define GD32F403_DBG_H 40 41 #include "gd32f403.h" 42 43 /* DBG definitions */ 44 #define DBG DBG_BASE 45 46 /* registers definitions */ 47 #define DBG_ID REG32(DBG + 0x00U) /*!< DBG_ID code register */ 48 #define DBG_CTL0 REG32(DBG + 0x04U) /*!< DBG control register 0 */ 49 50 /* bits definitions */ 51 /* DBG_ID */ 52 #define DBG_ID_ID_CODE BITS(0,31) /*!< DBG ID code values */ 53 54 /* DBG_CTL0 */ 55 #define DBG_CTL0_SLP_HOLD BIT(0) /*!< keep debugger connection during sleep mode */ 56 #define DBG_CTL0_DSLP_HOLD BIT(1) /*!< keep debugger connection during deepsleep mode */ 57 #define DBG_CTL0_STB_HOLD BIT(2) /*!< keep debugger connection during standby mode */ 58 #define DBG_CTL0_TRACE_IOEN BIT(5) /*!< enable trace pin assignment */ 59 #define DBG_CTL0_TRACE_MODE BITS(6,7) /*!< trace pin mode selection */ 60 #define DBG_CTL0_FWDGT_HOLD BIT(8) /*!< debug FWDGT kept when core is halted */ 61 #define DBG_CTL0_WWDGT_HOLD BIT(9) /*!< debug WWDGT kept when core is halted */ 62 #define DBG_CTL0_TIMER0_HOLD BIT(10) /*!< hold TIMER0 counter when core is halted */ 63 #define DBG_CTL0_TIMER2_HOLD BIT(12) /*!< hold TIMER2 counter when core is halted */ 64 #define DBG_CTL0_TIMER3_HOLD BIT(13) /*!< hold TIMER3 counter when core is halted */ 65 #define DBG_CTL0_CAN0_HOLD BIT(14) /*!< debug CAN0 kept when core is halted */ 66 #define DBG_CTL0_I2C0_HOLD BIT(15) /*!< hold I2C0 smbus when core is halted */ 67 #define DBG_CTL0_I2C1_HOLD BIT(16) /*!< hold I2C1 smbus when core is halted */ 68 #define DBG_CTL0_TIMER7_HOLD BIT(17) /*!< hold TIMER7 counter when core is halted */ 69 #define DBG_CTL0_TIMER5_HOLD BIT(19) /*!< hold TIMER5 counter when core is halted */ 70 #define DBG_CTL0_TIMER6_HOLD BIT(20) /*!< hold TIMER6 counter when core is halted */ 71 #define DBG_CTL0_CAN1_HOLD BIT(21) /*!< debug CAN1 kept when core is halted */ 72 #define DBG_CTL0_TIMER11_HOLD BIT(25) /*!< hold TIMER11 counter when core is halted */ 73 #define DBG_CTL0_TIMER12_HOLD BIT(26) /*!< hold TIMER12 counter when core is halted */ 74 #define DBG_CTL0_TIMER13_HOLD BIT(27) /*!< hold TIMER13 counter when core is halted */ 75 #define DBG_CTL0_TIMER8_HOLD BIT(28) /*!< hold TIMER8 counter when core is halted */ 76 #define DBG_CTL0_TIMER9_HOLD BIT(29) /*!< hold TIMER9 counter when core is halted */ 77 #define DBG_CTL0_TIMER10_HOLD BIT(30) /*!< hold TIMER10 counter when core is halted */ 78 79 /* constants definitions */ 80 #define DBG_LOW_POWER_SLEEP DBG_CTL0_SLP_HOLD /*!< keep debugger connection during sleep mode */ 81 #define DBG_LOW_POWER_DEEPSLEEP DBG_CTL0_DSLP_HOLD /*!< keep debugger connection during deepsleep mode */ 82 #define DBG_LOW_POWER_STANDBY DBG_CTL0_STB_HOLD /*!< keep debugger connection during standby mode */ 83 84 /* define the peripheral debug hold bit position and its register index offset */ 85 #define DBG_REGIDX_BIT(regidx, bitpos) (((regidx) << 6) | (bitpos)) 86 #define DBG_REG_VAL(periph) (REG32(DBG + ((uint32_t)(periph) >> 6))) 87 #define DBG_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 88 89 /* register index */ 90 enum dbg_reg_idx 91 { 92 DBG_IDX_CTL0 = 0x04U 93 }; 94 95 typedef enum 96 { 97 DBG_FWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 8U), /*!< debug FWDGT kept when core is halted */ 98 DBG_WWDGT_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 9U), /*!< debug WWDGT kept when core is halted */ 99 DBG_TIMER0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 10U), /*!< hold TIMER0 counter when core is halted */ 100 DBG_TIMER2_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 12U), /*!< hold TIMER2 counter when core is halted */ 101 DBG_TIMER3_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 13U), /*!< hold TIMER3 counter when core is halted */ 102 DBG_CAN0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 14U), /*!< debug CAN0 kept when core is halted */ 103 DBG_I2C0_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 15U), /*!< hold I2C0 smbus when core is halted */ 104 DBG_I2C1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 16U), /*!< hold I2C1 smbus when core is halted */ 105 DBG_TIMER7_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 17U), /*!< hold TIMER7 counter when core is halted */ 106 DBG_TIMER5_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 19U), /*!< hold TIMER5 counter when core is halted */ 107 DBG_TIMER6_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 20U), /*!< hold TIMER6 counter when core is halted */ 108 DBG_CAN1_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 21U), /*!< debug CAN1 kept when core is halted */ 109 DBG_TIMER11_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 25U), /*!< hold TIMER11 counter when core is halted */ 110 DBG_TIMER12_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 26U), /*!< hold TIMER12 counter when core is halted */ 111 DBG_TIMER13_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 27U), /*!< hold TIMER13 counter when core is halted */ 112 DBG_TIMER8_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 28U), /*!< hold TIMER8 counter when core is halted */ 113 DBG_TIMER9_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 29U), /*!< hold TIMER9 counter when core is halted */ 114 DBG_TIMER10_HOLD = DBG_REGIDX_BIT(DBG_IDX_CTL0, 30U) /*!< hold TIMER10 counter when core is halted */ 115 }dbg_periph_enum; 116 117 #define CTL0_TRACE_MODE(regval) (BITS(6,7)&((uint32_t)(regval)<<6)) 118 #define TRACE_MODE_ASYNC CTL0_TRACE_MODE(0) /*!< trace pin used for async mode */ 119 #define TRACE_MODE_SYNC_DATASIZE_1 CTL0_TRACE_MODE(1) /*!< trace pin used for sync mode and data size is 1 */ 120 #define TRACE_MODE_SYNC_DATASIZE_2 CTL0_TRACE_MODE(2) /*!< trace pin used for sync mode and data size is 2 */ 121 #define TRACE_MODE_SYNC_DATASIZE_4 CTL0_TRACE_MODE(3) /*!< trace pin used for sync mode and data size is 4 */ 122 123 /* function declarations */ 124 /* deinitialize the DBG */ 125 void dbg_deinit(void); 126 /* read DBG_ID code register */ 127 uint32_t dbg_id_get(void); 128 129 /* enable low power behavior when the MCU is in debug mode */ 130 void dbg_low_power_enable(uint32_t dbg_low_power); 131 /* disable low power behavior when the MCU is in debug mode */ 132 void dbg_low_power_disable(uint32_t dbg_low_power); 133 134 /* enable peripheral behavior when the MCU is in debug mode */ 135 void dbg_periph_enable(dbg_periph_enum dbg_periph); 136 /* disable peripheral behavior when the MCU is in debug mode */ 137 void dbg_periph_disable(dbg_periph_enum dbg_periph); 138 139 /* enable trace pin assignment */ 140 void dbg_trace_pin_enable(void); 141 /* disable trace pin assignment */ 142 void dbg_trace_pin_disable(void); 143 /* set trace pin mode */ 144 void dbg_trace_pin_mode_set(uint32_t trace_mode); 145 146 #endif /* GD32F403_DBG_H */ 147
