1 /*!
2 \file gd32f403_dbg.c
3 \brief DBG driver
4
5 \version 2017-02-10, V1.0.0, firmware for gd32f403
6 \version 2018-12-25, V2.0.0, firmware for gd32f403
7 \version 2020-09-30, V2.1.0, firmware for GD32F403
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f403_dbg.h"
38 #define DBG_RESET_VAL 0x00000000U
39
40 /*!
41 \brief deinitialize the DBG
42 \param[in] none
43 \param[out] none
44 \retval none
45 */
dbg_deinit(void)46 void dbg_deinit(void)
47 {
48 DBG_CTL0 = DBG_RESET_VAL;
49 }
50
51 /*!
52 \brief read DBG_ID code register
53 \param[in] none
54 \param[out] none
55 \retval DBG_ID code
56 */
dbg_id_get(void)57 uint32_t dbg_id_get(void)
58 {
59 return DBG_ID;
60 }
61
62 /*!
63 \brief enable low power behavior when the mcu is in debug mode
64 \param[in] dbg_low_power:
65 this parameter can be any combination of the following values:
66 \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
67 \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
68 \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
69 \param[out] none
70 \retval none
71 */
dbg_low_power_enable(uint32_t dbg_low_power)72 void dbg_low_power_enable(uint32_t dbg_low_power)
73 {
74 DBG_CTL0 |= dbg_low_power;
75 }
76
77 /*!
78 \brief disable low power behavior when the mcu is in debug mode
79 \param[in] dbg_low_power:
80 this parameter can be any combination of the following values:
81 \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
82 \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
83 \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
84 \param[out] none
85 \retval none
86 */
dbg_low_power_disable(uint32_t dbg_low_power)87 void dbg_low_power_disable(uint32_t dbg_low_power)
88 {
89 DBG_CTL0 &= ~dbg_low_power;
90 }
91
92 /*!
93 \brief enable peripheral behavior when the mcu is in debug mode
94 \param[in] dbg_periph: refer to dbg_periph_enum
95 only one parameter can be selected which is shown as below:
96 \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
97 \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
98 \arg DBG_CANx_HOLD (x=0,1): debug CANx kept when core is halted
99 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
100 \arg DBG_TIMERx_HOLD (x=0,2,3,5..13): hold TIMERx counter when core is halted
101 \param[out] none
102 \retval none
103 */
dbg_periph_enable(dbg_periph_enum dbg_periph)104 void dbg_periph_enable(dbg_periph_enum dbg_periph)
105 {
106 DBG_REG_VAL(dbg_periph) |= BIT(DBG_BIT_POS(dbg_periph));
107 }
108
109 /*!
110 \brief disable peripheral behavior when the mcu is in debug mode
111 \param[in] dbg_periph: refer to dbg_periph_enum
112 only one parameter can be selected which is shown as below:
113 \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
114 \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
115 \arg DBG_CANx_HOLD (x=0,1): debug CANx kept when core is halted
116 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
117 \arg DBG_TIMERx_HOLD (x=0,2,3,5..13): hold TIMERx counter when core is halted
118 \param[out] none
119 \retval none
120 */
dbg_periph_disable(dbg_periph_enum dbg_periph)121 void dbg_periph_disable(dbg_periph_enum dbg_periph)
122 {
123 DBG_REG_VAL(dbg_periph) &= ~BIT(DBG_BIT_POS(dbg_periph));
124 }
125
126 /*!
127 \brief enable trace pin assignment
128 \param[in] none
129 \param[out] none
130 \retval none
131 */
dbg_trace_pin_enable(void)132 void dbg_trace_pin_enable(void)
133 {
134 DBG_CTL0 |= DBG_CTL0_TRACE_IOEN;
135 }
136
137 /*!
138 \brief disable trace pin assignment
139 \param[in] none
140 \param[out] none
141 \retval none
142 */
dbg_trace_pin_disable(void)143 void dbg_trace_pin_disable(void)
144 {
145 DBG_CTL0 &= ~DBG_CTL0_TRACE_IOEN;
146 }
147
148 /*!
149 \brief trace pin mode selection
150 \param[in] trace_mode:
151 \arg TRACE_MODE_ASYNC: trace pin used for async mode
152 \arg TRACE_MODE_SYNC_DATASIZE_1: trace pin used for sync mode and data size is 1
153 \arg TRACE_MODE_SYNC_DATASIZE_2: trace pin used for sync mode and data size is 2
154 \arg TRACE_MODE_SYNC_DATASIZE_4: trace pin used for sync mode and data size is 4
155 \param[out] none
156 \retval none
157 */
dbg_trace_pin_mode_set(uint32_t trace_mode)158 void dbg_trace_pin_mode_set(uint32_t trace_mode)
159 {
160 DBG_CTL0 &= ~DBG_CTL0_TRACE_MODE;
161 DBG_CTL0 |= trace_mode;
162 }
163
