1 /*! 2 \file gd32f403_can.h 3 \brief definitions for the CAN 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2019-11-27, V2.0.1, firmware for GD32F403 8 \version 2020-09-30, V2.1.0, firmware for GD32F403 9 */ 10 11 /* 12 Copyright (c) 2020, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32F403_CAN_H 39 #define GD32F403_CAN_H 40 41 #include "gd32f403.h" 42 43 /* CAN definitions */ 44 #define CAN0 CAN_BASE /*!< CAN0 base address */ 45 #define CAN1 (CAN0 + 0x00000400U) /*!< CAN1 base address */ 46 47 /* registers definitions */ 48 #define CAN_CTL(canx) REG32((canx) + 0x00U) /*!< CAN control register */ 49 #define CAN_STAT(canx) REG32((canx) + 0x04U) /*!< CAN status register */ 50 #define CAN_TSTAT(canx) REG32((canx) + 0x08U) /*!< CAN transmit status register*/ 51 #define CAN_RFIFO0(canx) REG32((canx) + 0x0CU) /*!< CAN receive FIFO0 register */ 52 #define CAN_RFIFO1(canx) REG32((canx) + 0x10U) /*!< CAN receive FIFO1 register */ 53 #define CAN_INTEN(canx) REG32((canx) + 0x14U) /*!< CAN interrupt enable register */ 54 #define CAN_ERR(canx) REG32((canx) + 0x18U) /*!< CAN error register */ 55 #define CAN_BT(canx) REG32((canx) + 0x1CU) /*!< CAN bit timing register */ 56 #define CAN_TMI0(canx) REG32((canx) + 0x180U) /*!< CAN transmit mailbox0 identifier register */ 57 #define CAN_TMP0(canx) REG32((canx) + 0x184U) /*!< CAN transmit mailbox0 property register */ 58 #define CAN_TMDATA00(canx) REG32((canx) + 0x188U) /*!< CAN transmit mailbox0 data0 register */ 59 #define CAN_TMDATA10(canx) REG32((canx) + 0x18CU) /*!< CAN transmit mailbox0 data1 register */ 60 #define CAN_TMI1(canx) REG32((canx) + 0x190U) /*!< CAN transmit mailbox1 identifier register */ 61 #define CAN_TMP1(canx) REG32((canx) + 0x194U) /*!< CAN transmit mailbox1 property register */ 62 #define CAN_TMDATA01(canx) REG32((canx) + 0x198U) /*!< CAN transmit mailbox1 data0 register */ 63 #define CAN_TMDATA11(canx) REG32((canx) + 0x19CU) /*!< CAN transmit mailbox1 data1 register */ 64 #define CAN_TMI2(canx) REG32((canx) + 0x1A0U) /*!< CAN transmit mailbox2 identifier register */ 65 #define CAN_TMP2(canx) REG32((canx) + 0x1A4U) /*!< CAN transmit mailbox2 property register */ 66 #define CAN_TMDATA02(canx) REG32((canx) + 0x1A8U) /*!< CAN transmit mailbox2 data0 register */ 67 #define CAN_TMDATA12(canx) REG32((canx) + 0x1ACU) /*!< CAN transmit mailbox2 data1 register */ 68 #define CAN_RFIFOMI0(canx) REG32((canx) + 0x1B0U) /*!< CAN receive FIFO0 mailbox identifier register */ 69 #define CAN_RFIFOMP0(canx) REG32((canx) + 0x1B4U) /*!< CAN receive FIFO0 mailbox property register */ 70 #define CAN_RFIFOMDATA00(canx) REG32((canx) + 0x1B8U) /*!< CAN receive FIFO0 mailbox data0 register */ 71 #define CAN_RFIFOMDATA10(canx) REG32((canx) + 0x1BCU) /*!< CAN receive FIFO0 mailbox data1 register */ 72 #define CAN_RFIFOMI1(canx) REG32((canx) + 0x1C0U) /*!< CAN receive FIFO1 mailbox identifier register */ 73 #define CAN_RFIFOMP1(canx) REG32((canx) + 0x1C4U) /*!< CAN receive FIFO1 mailbox property register */ 74 #define CAN_RFIFOMDATA01(canx) REG32((canx) + 0x1C8U) /*!< CAN receive FIFO1 mailbox data0 register */ 75 #define CAN_RFIFOMDATA11(canx) REG32((canx) + 0x1CCU) /*!< CAN receive FIFO1 mailbox data1 register */ 76 #define CAN_FCTL(canx) REG32((canx) + 0x200U) /*!< CAN filter control register */ 77 #define CAN_FMCFG(canx) REG32((canx) + 0x204U) /*!< CAN filter mode register */ 78 #define CAN_FSCFG(canx) REG32((canx) + 0x20CU) /*!< CAN filter scale register */ 79 #define CAN_FAFIFO(canx) REG32((canx) + 0x214U) /*!< CAN filter associated FIFO register */ 80 #define CAN_FW(canx) REG32((canx) + 0x21CU) /*!< CAN filter working register */ 81 #define CAN_F0DATA0(canx) REG32((canx) + 0x240U) /*!< CAN filter 0 data 0 register */ 82 #define CAN_F1DATA0(canx) REG32((canx) + 0x248U) /*!< CAN filter 1 data 0 register */ 83 #define CAN_F2DATA0(canx) REG32((canx) + 0x250U) /*!< CAN filter 2 data 0 register */ 84 #define CAN_F3DATA0(canx) REG32((canx) + 0x258U) /*!< CAN filter 3 data 0 register */ 85 #define CAN_F4DATA0(canx) REG32((canx) + 0x260U) /*!< CAN filter 4 data 0 register */ 86 #define CAN_F5DATA0(canx) REG32((canx) + 0x268U) /*!< CAN filter 5 data 0 register */ 87 #define CAN_F6DATA0(canx) REG32((canx) + 0x270U) /*!< CAN filter 6 data 0 register */ 88 #define CAN_F7DATA0(canx) REG32((canx) + 0x278U) /*!< CAN filter 7 data 0 register */ 89 #define CAN_F8DATA0(canx) REG32((canx) + 0x280U) /*!< CAN filter 8 data 0 register */ 90 #define CAN_F9DATA0(canx) REG32((canx) + 0x288U) /*!< CAN filter 9 data 0 register */ 91 #define CAN_F10DATA0(canx) REG32((canx) + 0x290U) /*!< CAN filter 10 data 0 register */ 92 #define CAN_F11DATA0(canx) REG32((canx) + 0x298U) /*!< CAN filter 11 data 0 register */ 93 #define CAN_F12DATA0(canx) REG32((canx) + 0x2A0U) /*!< CAN filter 12 data 0 register */ 94 #define CAN_F13DATA0(canx) REG32((canx) + 0x2A8U) /*!< CAN filter 13 data 0 register */ 95 #define CAN_F14DATA0(canx) REG32((canx) + 0x2B0U) /*!< CAN filter 14 data 0 register */ 96 #define CAN_F15DATA0(canx) REG32((canx) + 0x2B8U) /*!< CAN filter 15 data 0 register */ 97 #define CAN_F16DATA0(canx) REG32((canx) + 0x2C0U) /*!< CAN filter 16 data 0 register */ 98 #define CAN_F17DATA0(canx) REG32((canx) + 0x2C8U) /*!< CAN filter 17 data 0 register */ 99 #define CAN_F18DATA0(canx) REG32((canx) + 0x2D0U) /*!< CAN filter 18 data 0 register */ 100 #define CAN_F19DATA0(canx) REG32((canx) + 0x2D8U) /*!< CAN filter 19 data 0 register */ 101 #define CAN_F20DATA0(canx) REG32((canx) + 0x2E0U) /*!< CAN filter 20 data 0 register */ 102 #define CAN_F21DATA0(canx) REG32((canx) + 0x2E8U) /*!< CAN filter 21 data 0 register */ 103 #define CAN_F22DATA0(canx) REG32((canx) + 0x2F0U) /*!< CAN filter 22 data 0 register */ 104 #define CAN_F23DATA0(canx) REG32((canx) + 0x3F8U) /*!< CAN filter 23 data 0 register */ 105 #define CAN_F24DATA0(canx) REG32((canx) + 0x300U) /*!< CAN filter 24 data 0 register */ 106 #define CAN_F25DATA0(canx) REG32((canx) + 0x308U) /*!< CAN filter 25 data 0 register */ 107 #define CAN_F26DATA0(canx) REG32((canx) + 0x310U) /*!< CAN filter 26 data 0 register */ 108 #define CAN_F27DATA0(canx) REG32((canx) + 0x318U) /*!< CAN filter 27 data 0 register */ 109 #define CAN_F0DATA1(canx) REG32((canx) + 0x244U) /*!< CAN filter 0 data 1 register */ 110 #define CAN_F1DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 1 data 1 register */ 111 #define CAN_F2DATA1(canx) REG32((canx) + 0x254U) /*!< CAN filter 2 data 1 register */ 112 #define CAN_F3DATA1(canx) REG32((canx) + 0x25CU) /*!< CAN filter 3 data 1 register */ 113 #define CAN_F4DATA1(canx) REG32((canx) + 0x264U) /*!< CAN filter 4 data 1 register */ 114 #define CAN_F5DATA1(canx) REG32((canx) + 0x26CU) /*!< CAN filter 5 data 1 register */ 115 #define CAN_F6DATA1(canx) REG32((canx) + 0x274U) /*!< CAN filter 6 data 1 register */ 116 #define CAN_F7DATA1(canx) REG32((canx) + 0x27CU) /*!< CAN filter 7 data 1 register */ 117 #define CAN_F8DATA1(canx) REG32((canx) + 0x284U) /*!< CAN filter 8 data 1 register */ 118 #define CAN_F9DATA1(canx) REG32((canx) + 0x28CU) /*!< CAN filter 9 data 1 register */ 119 #define CAN_F10DATA1(canx) REG32((canx) + 0x294U) /*!< CAN filter 10 data 1 register */ 120 #define CAN_F11DATA1(canx) REG32((canx) + 0x29CU) /*!< CAN filter 11 data 1 register */ 121 #define CAN_F12DATA1(canx) REG32((canx) + 0x2A4U) /*!< CAN filter 12 data 1 register */ 122 #define CAN_F13DATA1(canx) REG32((canx) + 0x2ACU) /*!< CAN filter 13 data 1 register */ 123 #define CAN_F14DATA1(canx) REG32((canx) + 0x2B4U) /*!< CAN filter 14 data 1 register */ 124 #define CAN_F15DATA1(canx) REG32((canx) + 0x2BCU) /*!< CAN filter 15 data 1 register */ 125 #define CAN_F16DATA1(canx) REG32((canx) + 0x2C4U) /*!< CAN filter 16 data 1 register */ 126 #define CAN_F17DATA1(canx) REG32((canx) + 0x24CU) /*!< CAN filter 17 data 1 register */ 127 #define CAN_F18DATA1(canx) REG32((canx) + 0x2D4U) /*!< CAN filter 18 data 1 register */ 128 #define CAN_F19DATA1(canx) REG32((canx) + 0x2DCU) /*!< CAN filter 19 data 1 register */ 129 #define CAN_F20DATA1(canx) REG32((canx) + 0x2E4U) /*!< CAN filter 20 data 1 register */ 130 #define CAN_F21DATA1(canx) REG32((canx) + 0x2ECU) /*!< CAN filter 21 data 1 register */ 131 #define CAN_F22DATA1(canx) REG32((canx) + 0x2F4U) /*!< CAN filter 22 data 1 register */ 132 #define CAN_F23DATA1(canx) REG32((canx) + 0x2FCU) /*!< CAN filter 23 data 1 register */ 133 #define CAN_F24DATA1(canx) REG32((canx) + 0x304U) /*!< CAN filter 24 data 1 register */ 134 #define CAN_F25DATA1(canx) REG32((canx) + 0x30CU) /*!< CAN filter 25 data 1 register */ 135 #define CAN_F26DATA1(canx) REG32((canx) + 0x314U) /*!< CAN filter 26 data 1 register */ 136 #define CAN_F27DATA1(canx) REG32((canx) + 0x31CU) /*!< CAN filter 27 data 1 register */ 137 138 /* CAN transmit mailbox bank */ 139 #define CAN_TMI(canx, bank) REG32((canx) + 0x180U + ((bank) * 0x10U)) /*!< CAN transmit mailbox identifier register */ 140 #define CAN_TMP(canx, bank) REG32((canx) + 0x184U + ((bank) * 0x10U)) /*!< CAN transmit mailbox property register */ 141 #define CAN_TMDATA0(canx, bank) REG32((canx) + 0x188U + ((bank) * 0x10U)) /*!< CAN transmit mailbox data0 register */ 142 #define CAN_TMDATA1(canx, bank) REG32((canx) + 0x18CU + ((bank) * 0x10U)) /*!< CAN transmit mailbox data1 register */ 143 144 /* CAN filter bank */ 145 #define CAN_FDATA0(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x0U) /*!< CAN filter data 0 register */ 146 #define CAN_FDATA1(canx, bank) REG32((canx) + 0x240U + ((bank) * 0x8U) + 0x4U) /*!< CAN filter data 1 register */ 147 148 /* CAN receive fifo mailbox bank */ 149 #define CAN_RFIFOMI(canx, bank) REG32((canx) + 0x1B0U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox identifier register */ 150 #define CAN_RFIFOMP(canx, bank) REG32((canx) + 0x1B4U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox property register */ 151 #define CAN_RFIFOMDATA0(canx, bank) REG32((canx) + 0x1B8U + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data0 register */ 152 #define CAN_RFIFOMDATA1(canx, bank) REG32((canx) + 0x1BCU + ((bank) * 0x10U)) /*!< CAN receive FIFO mailbox data1 register */ 153 154 /* bits definitions */ 155 /* CAN_CTL */ 156 #define CAN_CTL_IWMOD BIT(0) /*!< initial working mode */ 157 #define CAN_CTL_SLPWMOD BIT(1) /*!< sleep working mode */ 158 #define CAN_CTL_TFO BIT(2) /*!< transmit FIFO order */ 159 #define CAN_CTL_RFOD BIT(3) /*!< receive FIFO overwrite disable */ 160 #define CAN_CTL_ARD BIT(4) /*!< automatic retransmission disable */ 161 #define CAN_CTL_AWU BIT(5) /*!< automatic wakeup */ 162 #define CAN_CTL_ABOR BIT(6) /*!< automatic bus-off recovery */ 163 #define CAN_CTL_TTC BIT(7) /*!< time triggered communication */ 164 #define CAN_CTL_SWRST BIT(15) /*!< CAN software reset */ 165 #define CAN_CTL_DFZ BIT(16) /*!< CAN debug freeze */ 166 167 /* CAN_STAT */ 168 #define CAN_STAT_IWS BIT(0) /*!< initial working state */ 169 #define CAN_STAT_SLPWS BIT(1) /*!< sleep working state */ 170 #define CAN_STAT_ERRIF BIT(2) /*!< error interrupt flag*/ 171 #define CAN_STAT_WUIF BIT(3) /*!< status change interrupt flag of wakeup from sleep working mode */ 172 #define CAN_STAT_SLPIF BIT(4) /*!< status change interrupt flag of sleep working mode entering */ 173 #define CAN_STAT_TS BIT(8) /*!< transmitting state */ 174 #define CAN_STAT_RS BIT(9) /*!< receiving state */ 175 #define CAN_STAT_LASTRX BIT(10) /*!< last sample value of rx pin */ 176 #define CAN_STAT_RXL BIT(11) /*!< CAN rx signal */ 177 178 /* CAN_TSTAT */ 179 #define CAN_TSTAT_MTF0 BIT(0) /*!< mailbox0 transmit finished */ 180 #define CAN_TSTAT_MTFNERR0 BIT(1) /*!< mailbox0 transmit finished and no error */ 181 #define CAN_TSTAT_MAL0 BIT(2) /*!< mailbox0 arbitration lost */ 182 #define CAN_TSTAT_MTE0 BIT(3) /*!< mailbox0 transmit error */ 183 #define CAN_TSTAT_MST0 BIT(7) /*!< mailbox0 stop transmitting */ 184 #define CAN_TSTAT_MTF1 BIT(8) /*!< mailbox1 transmit finished */ 185 #define CAN_TSTAT_MTFNERR1 BIT(9) /*!< mailbox1 transmit finished and no error */ 186 #define CAN_TSTAT_MAL1 BIT(10) /*!< mailbox1 arbitration lost */ 187 #define CAN_TSTAT_MTE1 BIT(11) /*!< mailbox1 transmit error */ 188 #define CAN_TSTAT_MST1 BIT(15) /*!< mailbox1 stop transmitting */ 189 #define CAN_TSTAT_MTF2 BIT(16) /*!< mailbox2 transmit finished */ 190 #define CAN_TSTAT_MTFNERR2 BIT(17) /*!< mailbox2 transmit finished and no error */ 191 #define CAN_TSTAT_MAL2 BIT(18) /*!< mailbox2 arbitration lost */ 192 #define CAN_TSTAT_MTE2 BIT(19) /*!< mailbox2 transmit error */ 193 #define CAN_TSTAT_MST2 BIT(23) /*!< mailbox2 stop transmitting */ 194 #define CAN_TSTAT_NUM BITS(24,25) /*!< mailbox number */ 195 #define CAN_TSTAT_TME0 BIT(26) /*!< transmit mailbox0 empty */ 196 #define CAN_TSTAT_TME1 BIT(27) /*!< transmit mailbox1 empty */ 197 #define CAN_TSTAT_TME2 BIT(28) /*!< transmit mailbox2 empty */ 198 #define CAN_TSTAT_TMLS0 BIT(29) /*!< last sending priority flag for mailbox0 */ 199 #define CAN_TSTAT_TMLS1 BIT(30) /*!< last sending priority flag for mailbox1 */ 200 #define CAN_TSTAT_TMLS2 BIT(31) /*!< last sending priority flag for mailbox2 */ 201 202 /* CAN_RFIFO0 */ 203 #define CAN_RFIFO0_RFL0 BITS(0,1) /*!< receive FIFO0 length */ 204 #define CAN_RFIFO0_RFF0 BIT(3) /*!< receive FIFO0 full */ 205 #define CAN_RFIFO0_RFO0 BIT(4) /*!< receive FIFO0 overfull */ 206 #define CAN_RFIFO0_RFD0 BIT(5) /*!< receive FIFO0 dequeue */ 207 208 /* CAN_RFIFO1 */ 209 #define CAN_RFIFO1_RFL1 BITS(0,1) /*!< receive FIFO1 length */ 210 #define CAN_RFIFO1_RFF1 BIT(3) /*!< receive FIFO1 full */ 211 #define CAN_RFIFO1_RFO1 BIT(4) /*!< receive FIFO1 overfull */ 212 #define CAN_RFIFO1_RFD1 BIT(5) /*!< receive FIFO1 dequeue */ 213 214 /* CAN_INTEN */ 215 #define CAN_INTEN_TMEIE BIT(0) /*!< transmit mailbox empty interrupt enable */ 216 #define CAN_INTEN_RFNEIE0 BIT(1) /*!< receive FIFO0 not empty interrupt enable */ 217 #define CAN_INTEN_RFFIE0 BIT(2) /*!< receive FIFO0 full interrupt enable */ 218 #define CAN_INTEN_RFOIE0 BIT(3) /*!< receive FIFO0 overfull interrupt enable */ 219 #define CAN_INTEN_RFNEIE1 BIT(4) /*!< receive FIFO1 not empty interrupt enable */ 220 #define CAN_INTEN_RFFIE1 BIT(5) /*!< receive FIFO1 full interrupt enable */ 221 #define CAN_INTEN_RFOIE1 BIT(6) /*!< receive FIFO1 overfull interrupt enable */ 222 #define CAN_INTEN_WERRIE BIT(8) /*!< warning error interrupt enable */ 223 #define CAN_INTEN_PERRIE BIT(9) /*!< passive error interrupt enable */ 224 #define CAN_INTEN_BOIE BIT(10) /*!< bus-off interrupt enable */ 225 #define CAN_INTEN_ERRNIE BIT(11) /*!< error number interrupt enable */ 226 #define CAN_INTEN_ERRIE BIT(15) /*!< error interrupt enable */ 227 #define CAN_INTEN_WIE BIT(16) /*!< wakeup interrupt enable */ 228 #define CAN_INTEN_SLPWIE BIT(17) /*!< sleep working interrupt enable */ 229 230 /* CAN_ERR */ 231 #define CAN_ERR_WERR BIT(0) /*!< warning error */ 232 #define CAN_ERR_PERR BIT(1) /*!< passive error */ 233 #define CAN_ERR_BOERR BIT(2) /*!< bus-off error */ 234 #define CAN_ERR_ERRN BITS(4,6) /*!< error number */ 235 #define CAN_ERR_TECNT BITS(16,23) /*!< transmit error count */ 236 #define CAN_ERR_RECNT BITS(24,31) /*!< receive error count */ 237 238 /* CAN_BT */ 239 #define CAN_BT_BAUDPSC BITS(0,9) /*!< baudrate prescaler */ 240 #define CAN_BT_BS1 BITS(16,19) /*!< bit segment 1 */ 241 #define CAN_BT_BS2 BITS(20,22) /*!< bit segment 2 */ 242 #define CAN_BT_SJW BITS(24,25) /*!< resynchronization jump width */ 243 #define CAN_BT_LCMOD BIT(30) /*!< loopback communication mode */ 244 #define CAN_BT_SCMOD BIT(31) /*!< silent communication mode */ 245 246 /* CAN_TMIx */ 247 #define CAN_TMI_TEN BIT(0) /*!< transmit enable */ 248 #define CAN_TMI_FT BIT(1) /*!< frame type */ 249 #define CAN_TMI_FF BIT(2) /*!< frame format */ 250 #define CAN_TMI_EFID BITS(3,31) /*!< the frame identifier */ 251 #define CAN_TMI_SFID BITS(21,31) /*!< the frame identifier */ 252 253 /* CAN_TMPx */ 254 #define CAN_TMP_DLENC BITS(0,3) /*!< data length code */ 255 #define CAN_TMP_TSEN BIT(8) /*!< time stamp enable */ 256 #define CAN_TMP_TS BITS(16,31) /*!< time stamp */ 257 258 /* CAN_TMDATA0x */ 259 #define CAN_TMDATA0_DB0 BITS(0,7) /*!< transmit data byte 0 */ 260 #define CAN_TMDATA0_DB1 BITS(8,15) /*!< transmit data byte 1 */ 261 #define CAN_TMDATA0_DB2 BITS(16,23) /*!< transmit data byte 2 */ 262 #define CAN_TMDATA0_DB3 BITS(24,31) /*!< transmit data byte 3 */ 263 264 /* CAN_TMDATA1x */ 265 #define CAN_TMDATA1_DB4 BITS(0,7) /*!< transmit data byte 4 */ 266 #define CAN_TMDATA1_DB5 BITS(8,15) /*!< transmit data byte 5 */ 267 #define CAN_TMDATA1_DB6 BITS(16,23) /*!< transmit data byte 6 */ 268 #define CAN_TMDATA1_DB7 BITS(24,31) /*!< transmit data byte 7 */ 269 270 /* CAN_RFIFOMIx */ 271 #define CAN_RFIFOMI_FT BIT(1) /*!< frame type */ 272 #define CAN_RFIFOMI_FF BIT(2) /*!< frame format */ 273 #define CAN_RFIFOMI_EFID BITS(3,31) /*!< the frame identifier */ 274 #define CAN_RFIFOMI_SFID BITS(21,31) /*!< the frame identifier */ 275 276 /* CAN_RFIFOMPx */ 277 #define CAN_RFIFOMP_DLENC BITS(0,3) /*!< receive data length code */ 278 #define CAN_RFIFOMP_FI BITS(8,15) /*!< filter index */ 279 #define CAN_RFIFOMP_TS BITS(16,31) /*!< time stamp */ 280 281 /* CAN_RFIFOMDATA0x */ 282 #define CAN_RFIFOMDATA0_DB0 BITS(0,7) /*!< receive data byte 0 */ 283 #define CAN_RFIFOMDATA0_DB1 BITS(8,15) /*!< receive data byte 1 */ 284 #define CAN_RFIFOMDATA0_DB2 BITS(16,23) /*!< receive data byte 2 */ 285 #define CAN_RFIFOMDATA0_DB3 BITS(24,31) /*!< receive data byte 3 */ 286 287 /* CAN_RFIFOMDATA1x */ 288 #define CAN_RFIFOMDATA1_DB4 BITS(0,7) /*!< receive data byte 4 */ 289 #define CAN_RFIFOMDATA1_DB5 BITS(8,15) /*!< receive data byte 5 */ 290 #define CAN_RFIFOMDATA1_DB6 BITS(16,23) /*!< receive data byte 6 */ 291 #define CAN_RFIFOMDATA1_DB7 BITS(24,31) /*!< receive data byte 7 */ 292 293 /* CAN_FCTL */ 294 #define CAN_FCTL_FLD BIT(0) /*!< filter lock disable */ 295 #define CAN_FCTL_HBC1F BITS(8,13) /*!< header bank of CAN1 filter */ 296 297 /* CAN_FMCFG */ 298 #define CAN_FMCFG_FMOD(regval) BIT(regval) /*!< filter mode, list or mask*/ 299 300 /* CAN_FSCFG */ 301 #define CAN_FSCFG_FS(regval) BIT(regval) /*!< filter scale, 32 bits or 16 bits*/ 302 303 /* CAN_FAFIFO */ 304 #define CAN_FAFIFOR_FAF(regval) BIT(regval) /*!< filter associated with FIFO */ 305 306 /* CAN_FW */ 307 #define CAN_FW_FW(regval) BIT(regval) /*!< filter working */ 308 309 /* CAN_FxDATAy */ 310 #define CAN_FDATA_FD(regval) BIT(regval) /*!< filter data */ 311 312 /* consts definitions */ 313 /* define the CAN bit position and its register index offset */ 314 #define CAN_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 315 #define CAN_REG_VAL(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 6))) 316 #define CAN_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 317 318 #define CAN_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1)) 319 #define CAN_REG_VALS(canx, offset) (REG32((canx) + ((uint32_t)(offset) >> 12))) 320 #define CAN_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU) 321 #define CAN_BIT_POS1(val) ((uint32_t)(val) & 0x1FU) 322 323 /* register offset */ 324 #define STAT_REG_OFFSET ((uint8_t)0x04U) /*!< STAT register offset */ 325 #define TSTAT_REG_OFFSET ((uint8_t)0x08U) /*!< TSTAT register offset */ 326 #define RFIFO0_REG_OFFSET ((uint8_t)0x0CU) /*!< RFIFO0 register offset */ 327 #define RFIFO1_REG_OFFSET ((uint8_t)0x10U) /*!< RFIFO1 register offset */ 328 #define ERR_REG_OFFSET ((uint8_t)0x18U) /*!< ERR register offset */ 329 330 /* CAN flags */ 331 typedef enum 332 { 333 /* flags in STAT register */ 334 CAN_FLAG_RXL = CAN_REGIDX_BIT(STAT_REG_OFFSET, 11U), /*!< RX level */ 335 CAN_FLAG_LASTRX = CAN_REGIDX_BIT(STAT_REG_OFFSET, 10U), /*!< last sample value of RX pin */ 336 CAN_FLAG_RS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 9U), /*!< receiving state */ 337 CAN_FLAG_TS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 8U), /*!< transmitting state */ 338 CAN_FLAG_SLPIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 4U), /*!< status change flag of entering sleep working mode */ 339 CAN_FLAG_WUIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 3U), /*!< status change flag of wakeup from sleep working mode */ 340 CAN_FLAG_ERRIF = CAN_REGIDX_BIT(STAT_REG_OFFSET, 2U), /*!< error flag */ 341 CAN_FLAG_SLPWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 1U), /*!< sleep working state */ 342 CAN_FLAG_IWS = CAN_REGIDX_BIT(STAT_REG_OFFSET, 0U), /*!< initial working state */ 343 /* flags in TSTAT register */ 344 CAN_FLAG_TMLS2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 31U), /*!< transmit mailbox 2 last sending in Tx FIFO */ 345 CAN_FLAG_TMLS1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 30U), /*!< transmit mailbox 1 last sending in Tx FIFO */ 346 CAN_FLAG_TMLS0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 29U), /*!< transmit mailbox 0 last sending in Tx FIFO */ 347 CAN_FLAG_TME2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 28U), /*!< transmit mailbox 2 empty */ 348 CAN_FLAG_TME1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 27U), /*!< transmit mailbox 1 empty */ 349 CAN_FLAG_TME0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 26U), /*!< transmit mailbox 0 empty */ 350 CAN_FLAG_MTE2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 19U), /*!< mailbox 2 transmit error */ 351 CAN_FLAG_MTE1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 11U), /*!< mailbox 1 transmit error */ 352 CAN_FLAG_MTE0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 3U), /*!< mailbox 0 transmit error */ 353 CAN_FLAG_MAL2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 18U), /*!< mailbox 2 arbitration lost */ 354 CAN_FLAG_MAL1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 10U), /*!< mailbox 1 arbitration lost */ 355 CAN_FLAG_MAL0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 2U), /*!< mailbox 0 arbitration lost */ 356 CAN_FLAG_MTFNERR2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 17U), /*!< mailbox 2 transmit finished with no error */ 357 CAN_FLAG_MTFNERR1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 9U), /*!< mailbox 1 transmit finished with no error */ 358 CAN_FLAG_MTFNERR0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 1U), /*!< mailbox 0 transmit finished with no error */ 359 CAN_FLAG_MTF2 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 16U), /*!< mailbox 2 transmit finished */ 360 CAN_FLAG_MTF1 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 8U), /*!< mailbox 1 transmit finished */ 361 CAN_FLAG_MTF0 = CAN_REGIDX_BIT(TSTAT_REG_OFFSET, 0U), /*!< mailbox 0 transmit finished */ 362 /* flags in RFIFO0 register */ 363 CAN_FLAG_RFO0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 4U), /*!< receive FIFO0 overfull */ 364 CAN_FLAG_RFF0 = CAN_REGIDX_BIT(RFIFO0_REG_OFFSET, 3U), /*!< receive FIFO0 full */ 365 /* flags in RFIFO1 register */ 366 CAN_FLAG_RFO1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 4U), /*!< receive FIFO1 overfull */ 367 CAN_FLAG_RFF1 = CAN_REGIDX_BIT(RFIFO1_REG_OFFSET, 3U), /*!< receive FIFO1 full */ 368 /* flags in ERR register */ 369 CAN_FLAG_BOERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 2U), /*!< bus-off error */ 370 CAN_FLAG_PERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 1U), /*!< passive error */ 371 CAN_FLAG_WERR = CAN_REGIDX_BIT(ERR_REG_OFFSET, 0U), /*!< warning error */ 372 }can_flag_enum; 373 374 /* CAN interrupt flags */ 375 typedef enum 376 { 377 /* interrupt flags in STAT register */ 378 CAN_INT_FLAG_SLPIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 4U, 17U), /*!< status change interrupt flag of sleep working mode entering */ 379 CAN_INT_FLAG_WUIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 3U, 16), /*!< status change interrupt flag of wakeup from sleep working mode */ 380 CAN_INT_FLAG_ERRIF = CAN_REGIDX_BITS(STAT_REG_OFFSET, 2U, 15), /*!< error interrupt flag */ 381 /* interrupt flags in TSTAT register */ 382 CAN_INT_FLAG_MTF2 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 16U, 0U), /*!< mailbox 2 transmit finished interrupt flag */ 383 CAN_INT_FLAG_MTF1 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 8U, 0U), /*!< mailbox 1 transmit finished interrupt flag */ 384 CAN_INT_FLAG_MTF0 = CAN_REGIDX_BITS(TSTAT_REG_OFFSET, 0U, 0U), /*!< mailbox 0 transmit finished interrupt flag */ 385 /* interrupt flags in RFIFO0 register */ 386 CAN_INT_FLAG_RFO0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 4U, 3U), /*!< receive FIFO0 overfull interrupt flag */ 387 CAN_INT_FLAG_RFF0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 3U, 2U), /*!< receive FIFO0 full interrupt flag */ 388 CAN_INT_FLAG_RFL0 = CAN_REGIDX_BITS(RFIFO0_REG_OFFSET, 2U, 1U), /*!< receive FIFO0 not empty interrupt flag */ 389 /* interrupt flags in RFIFO0 register */ 390 CAN_INT_FLAG_RFO1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 4U, 6U), /*!< receive FIFO1 overfull interrupt flag */ 391 CAN_INT_FLAG_RFF1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 3U, 5U), /*!< receive FIFO1 full interrupt flag */ 392 CAN_INT_FLAG_RFL1 = CAN_REGIDX_BITS(RFIFO1_REG_OFFSET, 2U, 4U), /*!< receive FIFO1 not empty interrupt flag */ 393 /* interrupt flags in ERR register */ 394 CAN_INT_FLAG_ERRN = CAN_REGIDX_BITS(ERR_REG_OFFSET, 3U, 11U), /*!< error number interrupt flag */ 395 CAN_INT_FLAG_BOERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 2U, 10U), /*!< bus-off error interrupt flag */ 396 CAN_INT_FLAG_PERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 1U, 9U), /*!< passive error interrupt flag */ 397 CAN_INT_FLAG_WERR = CAN_REGIDX_BITS(ERR_REG_OFFSET, 0U, 8U), /*!< warning error interrupt flag */ 398 }can_interrupt_flag_enum; 399 400 /* CAN initiliaze parameters struct */ 401 typedef struct 402 { 403 uint8_t working_mode; /*!< CAN working mode */ 404 uint8_t resync_jump_width; /*!< CAN resynchronization jump width */ 405 uint8_t time_segment_1; /*!< time segment 1 */ 406 uint8_t time_segment_2; /*!< time segment 2 */ 407 ControlStatus time_triggered; /*!< time triggered communication mode */ 408 ControlStatus auto_bus_off_recovery; /*!< automatic bus-off recovery */ 409 ControlStatus auto_wake_up; /*!< automatic wake-up mode */ 410 ControlStatus no_auto_retrans; /*!< automatic retransmission mode disable */ 411 ControlStatus rec_fifo_overwrite; /*!< receive FIFO overwrite mode */ 412 ControlStatus trans_fifo_order; /*!< transmit FIFO order */ 413 uint16_t prescaler; /*!< baudrate prescaler */ 414 }can_parameter_struct; 415 416 /* CAN transmit message struct */ 417 typedef struct 418 { 419 uint32_t tx_sfid; /*!< standard format frame identifier */ 420 uint32_t tx_efid; /*!< extended format frame identifier */ 421 uint8_t tx_ff; /*!< format of frame, standard or extended format */ 422 uint8_t tx_ft; /*!< type of frame, data or remote */ 423 uint8_t tx_dlen; /*!< data length */ 424 uint8_t tx_data[8]; /*!< transmit data */ 425 }can_trasnmit_message_struct; 426 427 /* CAN receive message struct */ 428 typedef struct 429 { 430 uint32_t rx_sfid; /*!< standard format frame identifier */ 431 uint32_t rx_efid; /*!< extended format frame identifier */ 432 uint8_t rx_ff; /*!< format of frame, standard or extended format */ 433 uint8_t rx_ft; /*!< type of frame, data or remote */ 434 uint8_t rx_dlen; /*!< data length */ 435 uint8_t rx_data[8]; /*!< receive data */ 436 uint8_t rx_fi; /*!< filtering index */ 437 } can_receive_message_struct; 438 439 /* CAN filter parameters struct */ 440 typedef struct 441 { 442 uint16_t filter_list_high; /*!< filter list number high bits*/ 443 uint16_t filter_list_low; /*!< filter list number low bits */ 444 uint16_t filter_mask_high; /*!< filter mask number high bits */ 445 uint16_t filter_mask_low; /*!< filter mask number low bits */ 446 uint16_t filter_fifo_number; /*!< receive FIFO associated with the filter */ 447 uint16_t filter_number; /*!< filter number */ 448 uint16_t filter_mode; /*!< filter mode, list or mask */ 449 uint16_t filter_bits; /*!< filter scale */ 450 ControlStatus filter_enable; /*!< filter work or not */ 451 }can_filter_parameter_struct; 452 453 /* CAN errors */ 454 typedef enum 455 { 456 CAN_ERROR_NONE = 0, /*!< no error */ 457 CAN_ERROR_FILL, /*!< fill error */ 458 CAN_ERROR_FORMATE, /*!< format error */ 459 CAN_ERROR_ACK, /*!< ACK error */ 460 CAN_ERROR_BITRECESSIVE, /*!< bit recessive error */ 461 CAN_ERROR_BITDOMINANTER, /*!< bit dominant error */ 462 CAN_ERROR_CRC, /*!< CRC error */ 463 CAN_ERROR_SOFTWARECFG, /*!< software configure */ 464 }can_error_enum; 465 466 /* transmit states */ 467 typedef enum 468 { 469 CAN_TRANSMIT_FAILED = 0U, /*!< CAN transmitted failure */ 470 CAN_TRANSMIT_OK = 1U, /*!< CAN transmitted success */ 471 CAN_TRANSMIT_PENDING = 2U, /*!< CAN transmitted pending */ 472 CAN_TRANSMIT_NOMAILBOX = 4U, /*!< no empty mailbox to be used for CAN */ 473 }can_transmit_state_enum; 474 475 typedef enum 476 { 477 CAN_INIT_STRUCT = 0, /* CAN initiliaze parameters struct */ 478 CAN_FILTER_STRUCT, /* CAN filter parameters struct */ 479 CAN_TX_MESSAGE_STRUCT, /* CAN transmit message struct */ 480 CAN_RX_MESSAGE_STRUCT, /* CAN receive message struct */ 481 }can_struct_type_enum; 482 483 /* CAN baudrate prescaler*/ 484 #define BT_BAUDPSC(regval) (BITS(0,9) & ((uint32_t)(regval) << 0)) 485 486 /* CAN bit segment 1*/ 487 #define BT_BS1(regval) (BITS(16,19) & ((uint32_t)(regval) << 16)) 488 489 /* CAN bit segment 2*/ 490 #define BT_BS2(regval) (BITS(20,22) & ((uint32_t)(regval) << 20)) 491 492 /* CAN resynchronization jump width*/ 493 #define BT_SJW(regval) (BITS(24,25) & ((uint32_t)(regval) << 24)) 494 495 /* CAN communication mode*/ 496 #define BT_MODE(regval) (BITS(30,31) & ((uint32_t)(regval) << 30)) 497 498 /* CAN FDATA high 16 bits */ 499 #define FDATA_MASK_HIGH(regval) (BITS(16,31) & ((uint32_t)(regval) << 16)) 500 501 /* CAN FDATA low 16 bits */ 502 #define FDATA_MASK_LOW(regval) (BITS(0,15) & ((uint32_t)(regval) << 0)) 503 504 /* CAN1 filter start bank_number*/ 505 #define FCTL_HBC1F(regval) (BITS(8,13) & ((uint32_t)(regval) << 8)) 506 507 /* CAN transmit mailbox extended identifier*/ 508 #define TMI_EFID(regval) (BITS(3,31) & ((uint32_t)(regval) << 3)) 509 510 /* CAN transmit mailbox standard identifier*/ 511 #define TMI_SFID(regval) (BITS(21,31) & ((uint32_t)(regval) << 21)) 512 513 /* transmit data byte 0 */ 514 #define TMDATA0_DB0(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 515 516 /* transmit data byte 1 */ 517 #define TMDATA0_DB1(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 518 519 /* transmit data byte 2 */ 520 #define TMDATA0_DB2(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 521 522 /* transmit data byte 3 */ 523 #define TMDATA0_DB3(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 524 525 /* transmit data byte 4 */ 526 #define TMDATA1_DB4(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 527 528 /* transmit data byte 5 */ 529 #define TMDATA1_DB5(regval) (BITS(8,15) & ((uint32_t)(regval) << 8)) 530 531 /* transmit data byte 6 */ 532 #define TMDATA1_DB6(regval) (BITS(16,23) & ((uint32_t)(regval) << 16)) 533 534 /* transmit data byte 7 */ 535 #define TMDATA1_DB7(regval) (BITS(24,31) & ((uint32_t)(regval) << 24)) 536 537 /* receive mailbox extended identifier*/ 538 #define GET_RFIFOMI_EFID(regval) GET_BITS((uint32_t)(regval), 3U, 31U) 539 540 /* receive mailbox standrad identifier*/ 541 #define GET_RFIFOMI_SFID(regval) GET_BITS((uint32_t)(regval), 21U, 31U) 542 543 /* receive data length */ 544 #define GET_RFIFOMP_DLENC(regval) GET_BITS((uint32_t)(regval), 0U, 3U) 545 546 /* the index of the filter by which the frame is passed */ 547 #define GET_RFIFOMP_FI(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 548 549 /* receive data byte 0 */ 550 #define GET_RFIFOMDATA0_DB0(regval) GET_BITS((uint32_t)(regval), 0U, 7U) 551 552 /* receive data byte 1 */ 553 #define GET_RFIFOMDATA0_DB1(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 554 555 /* receive data byte 2 */ 556 #define GET_RFIFOMDATA0_DB2(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 557 558 /* receive data byte 3 */ 559 #define GET_RFIFOMDATA0_DB3(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 560 561 /* receive data byte 4 */ 562 #define GET_RFIFOMDATA1_DB4(regval) GET_BITS((uint32_t)(regval), 0U, 7U) 563 564 /* receive data byte 5 */ 565 #define GET_RFIFOMDATA1_DB5(regval) GET_BITS((uint32_t)(regval), 8U, 15U) 566 567 /* receive data byte 6 */ 568 #define GET_RFIFOMDATA1_DB6(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 569 570 /* receive data byte 7 */ 571 #define GET_RFIFOMDATA1_DB7(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 572 573 /* error number */ 574 #define GET_ERR_ERRN(regval) GET_BITS((uint32_t)(regval), 4U, 6U) 575 576 /* transmit error count */ 577 #define GET_ERR_TECNT(regval) GET_BITS((uint32_t)(regval), 16U, 23U) 578 579 /* receive error count */ 580 #define GET_ERR_RECNT(regval) GET_BITS((uint32_t)(regval), 24U, 31U) 581 582 /* CAN errors */ 583 #define ERR_ERRN(regval) (BITS(4,6) & ((uint32_t)(regval) << 4)) 584 #define CAN_ERRN_0 ERR_ERRN(0U) /* no error */ 585 #define CAN_ERRN_1 ERR_ERRN(1U) /*!< fill error */ 586 #define CAN_ERRN_2 ERR_ERRN(2U) /*!< format error */ 587 #define CAN_ERRN_3 ERR_ERRN(3U) /*!< ACK error */ 588 #define CAN_ERRN_4 ERR_ERRN(4U) /*!< bit recessive error */ 589 #define CAN_ERRN_5 ERR_ERRN(5U) /*!< bit dominant error */ 590 #define CAN_ERRN_6 ERR_ERRN(6U) /*!< CRC error */ 591 #define CAN_ERRN_7 ERR_ERRN(7U) /*!< software error */ 592 593 #define CAN_STATE_PENDING ((uint32_t)0x00000000U) /*!< CAN pending */ 594 595 /* CAN communication mode */ 596 #define GD32_CAN_NORMAL_MODE ((uint8_t)0x00U) /*!< normal communication mode */ 597 #define GD32_CAN_LOOPBACK_MODE ((uint8_t)0x01U) /*!< loopback communication mode */ 598 #define GD32_CAN_SILENT_MODE ((uint8_t)0x02U) /*!< silent communication mode */ 599 #define GD32_CAN_SILENT_LOOPBACK_MODE ((uint8_t)0x03U) /*!< loopback and silent communication mode */ 600 601 /* CAN resynchronisation jump width */ 602 #define CAN_BT_SJW_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 603 #define CAN_BT_SJW_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 604 #define CAN_BT_SJW_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 605 #define CAN_BT_SJW_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 606 607 /* CAN time segment 1 */ 608 #define CAN_BT_BS1_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 609 #define CAN_BT_BS1_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 610 #define CAN_BT_BS1_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 611 #define CAN_BT_BS1_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 612 #define CAN_BT_BS1_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 613 #define CAN_BT_BS1_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 614 #define CAN_BT_BS1_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 615 #define CAN_BT_BS1_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 616 #define CAN_BT_BS1_9TQ ((uint8_t)0x08U) /*!< 9 time quanta */ 617 #define CAN_BT_BS1_10TQ ((uint8_t)0x09U) /*!< 10 time quanta */ 618 #define CAN_BT_BS1_11TQ ((uint8_t)0x0AU) /*!< 11 time quanta */ 619 #define CAN_BT_BS1_12TQ ((uint8_t)0x0BU) /*!< 12 time quanta */ 620 #define CAN_BT_BS1_13TQ ((uint8_t)0x0CU) /*!< 13 time quanta */ 621 #define CAN_BT_BS1_14TQ ((uint8_t)0x0DU) /*!< 14 time quanta */ 622 #define CAN_BT_BS1_15TQ ((uint8_t)0x0EU) /*!< 15 time quanta */ 623 #define CAN_BT_BS1_16TQ ((uint8_t)0x0FU) /*!< 16 time quanta */ 624 625 /* CAN time segment 2 */ 626 #define CAN_BT_BS2_1TQ ((uint8_t)0x00U) /*!< 1 time quanta */ 627 #define CAN_BT_BS2_2TQ ((uint8_t)0x01U) /*!< 2 time quanta */ 628 #define CAN_BT_BS2_3TQ ((uint8_t)0x02U) /*!< 3 time quanta */ 629 #define CAN_BT_BS2_4TQ ((uint8_t)0x03U) /*!< 4 time quanta */ 630 #define CAN_BT_BS2_5TQ ((uint8_t)0x04U) /*!< 5 time quanta */ 631 #define CAN_BT_BS2_6TQ ((uint8_t)0x05U) /*!< 6 time quanta */ 632 #define CAN_BT_BS2_7TQ ((uint8_t)0x06U) /*!< 7 time quanta */ 633 #define CAN_BT_BS2_8TQ ((uint8_t)0x07U) /*!< 8 time quanta */ 634 635 /* CAN mailbox number */ 636 #define CAN_MAILBOX0 ((uint8_t)0x00U) /*!< mailbox0 */ 637 #define CAN_MAILBOX1 ((uint8_t)0x01U) /*!< mailbox1 */ 638 #define CAN_MAILBOX2 ((uint8_t)0x02U) /*!< mailbox2 */ 639 #define CAN_NOMAILBOX ((uint8_t)0x03U) /*!< no mailbox empty */ 640 641 /* CAN frame format */ 642 #define CAN_FF_STANDARD ((uint32_t)0x00000000U) /*!< standard frame */ 643 #define CAN_FF_EXTENDED ((uint32_t)0x00000004U) /*!< extended frame */ 644 645 /* CAN receive fifo */ 646 #define CAN_FIFO0 ((uint8_t)0x00U) /*!< receive FIFO0 */ 647 #define CAN_FIFO1 ((uint8_t)0x01U) /*!< receive FIFO1 */ 648 649 /* frame number of receive fifo */ 650 #define CAN_RFIF_RFL_MASK ((uint32_t)0x00000003U) /*!< mask for frame number in receive FIFOx */ 651 652 #define CAN_SFID_MASK ((uint32_t)0x000007FFU) /*!< mask of standard identifier */ 653 #define CAN_EFID_MASK ((uint32_t)0x1FFFFFFFU) /*!< mask of extended identifier */ 654 655 /* CAN working mode */ 656 #define CAN_MODE_INITIALIZE ((uint8_t)0x01U) /*!< CAN initialize mode */ 657 #define CAN_MODE_NORMAL ((uint8_t)0x02U) /*!< CAN normal mode */ 658 #define CAN_MODE_SLEEP ((uint8_t)0x04U) /*!< CAN sleep mode */ 659 660 /* filter bits */ 661 #define CAN_FILTERBITS_16BIT ((uint8_t)0x00U) /*!< CAN filter 16 bits */ 662 #define CAN_FILTERBITS_32BIT ((uint8_t)0x01U) /*!< CAN filter 32 bits */ 663 664 /* filter mode */ 665 #define CAN_FILTERMODE_MASK ((uint8_t)0x00U) /*!< mask mode */ 666 #define CAN_FILTERMODE_LIST ((uint8_t)0x01U) /*!< list mode */ 667 668 /* filter 16 bits mask */ 669 #define CAN_FILTER_MASK_16BITS ((uint32_t)0x0000FFFFU) /*!< can filter 16 bits mask */ 670 671 /* frame type */ 672 #define CAN_FT_DATA ((uint32_t)0x00000000U) /*!< data frame */ 673 #define CAN_FT_REMOTE ((uint32_t)0x00000002U) /*!< remote frame */ 674 675 /* CAN timeout */ 676 #define GD32_CAN_TIMEOUT ((uint32_t)0x0000FFFFU) /*!< timeout value */ 677 678 /* interrupt enable bits */ 679 #define CAN_INT_TME CAN_INTEN_TMEIE /*!< transmit mailbox empty interrupt enable */ 680 #define CAN_INT_RFNE0 CAN_INTEN_RFNEIE0 /*!< receive FIFO0 not empty interrupt enable */ 681 #define CAN_INT_RFF0 CAN_INTEN_RFFIE0 /*!< receive FIFO0 full interrupt enable */ 682 #define CAN_INT_RFO0 CAN_INTEN_RFOIE0 /*!< receive FIFO0 overfull interrupt enable */ 683 #define CAN_INT_RFNE1 CAN_INTEN_RFNEIE1 /*!< receive FIFO1 not empty interrupt enable */ 684 #define CAN_INT_RFF1 CAN_INTEN_RFFIE1 /*!< receive FIFO1 full interrupt enable */ 685 #define CAN_INT_RFO1 CAN_INTEN_RFOIE1 /*!< receive FIFO1 overfull interrupt enable */ 686 #define CAN_INT_WERR CAN_INTEN_WERRIE /*!< warning error interrupt enable */ 687 #define CAN_INT_PERR CAN_INTEN_PERRIE /*!< passive error interrupt enable */ 688 #define CAN_INT_BO CAN_INTEN_BOIE /*!< bus-off interrupt enable */ 689 #define CAN_INT_ERRN CAN_INTEN_ERRNIE /*!< error number interrupt enable */ 690 #define CAN_INT_ERR CAN_INTEN_ERRIE /*!< error interrupt enable */ 691 #define CAN_INT_WAKEUP CAN_INTEN_WIE /*!< wakeup interrupt enable */ 692 #define CAN_INT_SLPW CAN_INTEN_SLPWIE /*!< sleep working interrupt enable */ 693 694 /* function declarations */ 695 /* deinitialize CAN */ 696 void can_deinit(uint32_t can_periph); 697 /* initialize CAN struct */ 698 void can_struct_para_init(can_struct_type_enum type, void* p_struct); 699 /* initialize CAN */ 700 ErrStatus can_init(uint32_t can_periph, can_parameter_struct* can_parameter_init); 701 /* CAN filter init */ 702 void can_filter_init(can_filter_parameter_struct* can_filter_parameter_init); 703 /* set can1 fliter start bank number */ 704 void can1_filter_start_bank(uint8_t start_bank); 705 /* enable functions */ 706 /* CAN debug freeze enable */ 707 void can_debug_freeze_enable(uint32_t can_periph); 708 /* CAN debug freeze disable */ 709 void can_debug_freeze_disable(uint32_t can_periph); 710 /* CAN time trigger mode enable */ 711 void can_time_trigger_mode_enable(uint32_t can_periph); 712 /* CAN time trigger mode disable */ 713 void can_time_trigger_mode_disable(uint32_t can_periph); 714 715 /* transmit functions */ 716 /* transmit CAN message */ 717 uint8_t can_message_transmit(uint32_t can_periph, can_trasnmit_message_struct* transmit_message); 718 /* get CAN transmit state */ 719 can_transmit_state_enum can_transmit_states(uint32_t can_periph, uint8_t mailbox_number); 720 /* stop CAN transmission */ 721 void can_transmission_stop(uint32_t can_periph, uint8_t mailbox_number); 722 /* CAN receive message */ 723 void can_message_receive(uint32_t can_periph, uint8_t fifo_number, can_receive_message_struct* receive_message); 724 /* CAN release fifo */ 725 void can_fifo_release(uint32_t can_periph, uint8_t fifo_number); 726 /* CAN receive message length */ 727 uint8_t can_receive_message_length_get(uint32_t can_periph, uint8_t fifo_number); 728 /* CAN working mode */ 729 ErrStatus can_working_mode_set(uint32_t can_periph, uint8_t working_mode); 730 /* CAN wakeup from sleep mode */ 731 ErrStatus can_wakeup(uint32_t can_periph); 732 733 /* CAN get error */ 734 can_error_enum can_error_get(uint32_t can_periph); 735 /* get CAN receive error number */ 736 uint8_t can_receive_error_number_get(uint32_t can_periph); 737 /* get CAN transmit error number */ 738 uint8_t can_transmit_error_number_get(uint32_t can_periph); 739 740 /* CAN interrupt enable */ 741 void can_interrupt_enable(uint32_t can_periph, uint32_t interrupt); 742 /* CAN interrupt disable */ 743 void can_interrupt_disable(uint32_t can_periph, uint32_t interrupt); 744 /* CAN get flag state */ 745 FlagStatus can_flag_get(uint32_t can_periph, can_flag_enum flag); 746 /* CAN clear flag state */ 747 void can_flag_clear(uint32_t can_periph, can_flag_enum flag); 748 /* CAN get interrupt flag state */ 749 FlagStatus can_interrupt_flag_get(uint32_t can_periph, can_interrupt_flag_enum flag); 750 /* CAN clear interrupt flag state */ 751 void can_interrupt_flag_clear(uint32_t can_periph, can_interrupt_flag_enum flag); 752 753 #endif /* GD32F403_CAN_H */ 754
