1 /*! 2 \file gd32f3x0_rcu.h 3 \brief definitions for the RCU 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_RCU_H 38 #define GD32F3X0_RCU_H 39 40 #include "gd32f3x0.h" 41 42 /* RCU definitions */ 43 #define RCU RCU_BASE 44 45 /* registers definitions */ 46 #define RCU_CTL0 REG32(RCU + 0x00000000U) /*!< control register 0 */ 47 #define RCU_CFG0 REG32(RCU + 0x00000004U) /*!< configuration register 0 */ 48 #define RCU_INT REG32(RCU + 0x00000008U) /*!< interrupt register */ 49 #define RCU_APB2RST REG32(RCU + 0x0000000CU) /*!< APB2 reset register */ 50 #define RCU_APB1RST REG32(RCU + 0x00000010U) /*!< APB1 reset register */ 51 #define RCU_AHBEN REG32(RCU + 0x00000014U) /*!< AHB enable register */ 52 #define RCU_APB2EN REG32(RCU + 0x00000018U) /*!< APB2 enable register */ 53 #define RCU_APB1EN REG32(RCU + 0x0000001CU) /*!< APB1 enable register */ 54 #define RCU_BDCTL REG32(RCU + 0x00000020U) /*!< backup domain control register */ 55 #define RCU_RSTSCK REG32(RCU + 0x00000024U) /*!< reset source /clock register */ 56 #define RCU_AHBRST REG32(RCU + 0x00000028U) /*!< AHB reset register */ 57 #define RCU_CFG1 REG32(RCU + 0x0000002CU) /*!< configuration register 1 */ 58 #define RCU_CFG2 REG32(RCU + 0x00000030U) /*!< configuration register 2 */ 59 #define RCU_CTL1 REG32(RCU + 0x00000034U) /*!< control register 1 */ 60 #define RCU_ADDCTL REG32(RCU + 0x000000C0U) /*!< additional clock control register */ 61 #define RCU_ADDINT REG32(RCU + 0x000000CCU) /*!< additional clock interrupt register */ 62 #define RCU_ADDAPB1EN REG32(RCU + 0x000000F8U) /*!< APB1 additional enable register */ 63 #define RCU_ADDAPB1RST REG32(RCU + 0x000000FCU) /*!< APB1 additional reset register */ 64 #define RCU_VKEY REG32(RCU + 0x00000100U) /*!< voltage key register */ 65 #define RCU_DSV REG32(RCU + 0x00000134U) /*!< deep-sleep mode voltage register */ 66 67 /* bits definitions */ 68 /* RCU_CTL0 */ 69 #define RCU_CTL0_IRC8MEN BIT(0) /*!< internal high speed oscillator enable */ 70 #define RCU_CTL0_IRC8MSTB BIT(1) /*!< IRC8M high speed internal oscillator stabilization flag */ 71 #define RCU_CTL0_IRC8MADJ BITS(3,7) /*!< high speed internal oscillator clock trim adjust value */ 72 #define RCU_CTL0_IRC8MCALIB BITS(8,15) /*!< high speed internal oscillator calibration value register */ 73 #define RCU_CTL0_HXTALEN BIT(16) /*!< external high speed oscillator enable */ 74 #define RCU_CTL0_HXTALSTB BIT(17) /*!< external crystal oscillator clock stabilization flag */ 75 #define RCU_CTL0_HXTALBPS BIT(18) /*!< external crystal oscillator clock bypass mode enable */ 76 #define RCU_CTL0_CKMEN BIT(19) /*!< HXTAL clock monitor enable */ 77 #define RCU_CTL0_PLLEN BIT(24) /*!< PLL enable */ 78 #define RCU_CTL0_PLLSTB BIT(25) /*!< PLL clock stabilization flag */ 79 80 /* RCU_CFG0 */ 81 #define RCU_CFG0_SCS BITS(0,1) /*!< system clock switch */ 82 #define RCU_CFG0_SCSS BITS(2,3) /*!< system clock switch status */ 83 #define RCU_CFG0_AHBPSC BITS(4,7) /*!< AHB prescaler selection */ 84 #define RCU_CFG0_APB1PSC BITS(8,10) /*!< APB1 prescaler selection */ 85 #define RCU_CFG0_APB2PSC BITS(11,13) /*!< APB2 prescaler selection */ 86 #define RCU_CFG0_ADCPSC BITS(14,15) /*!< ADC clock prescaler selection */ 87 #define RCU_CFG0_PLLSEL BIT(16) /*!< PLL clock source selection */ 88 #define RCU_CFG0_PLLPREDV BIT(17) /*!< divider for PLL source clock selection */ 89 #define RCU_CFG0_PLLMF (BIT(27) | BITS(18,21)) /*!< PLL multiply factor */ 90 #define RCU_CFG0_USBFSPSC BITS(22,23) /*!< USBFS clock prescaler selection */ 91 #define RCU_CFG0_CKOUTSEL BITS(24,26) /*!< CK_OUT clock source selection */ 92 #define RCU_CFG0_PLLMF4 BIT(27) /*!< bit 4 of PLLMF */ 93 #define RCU_CFG0_CKOUTDIV BITS(28,30) /*!< CK_OUT divider which the CK_OUT frequency can be reduced */ 94 #define RCU_CFG0_PLLDV BIT(31) /*!< CK_PLL divide by 1 or 2 */ 95 96 /* RCU_INT */ 97 #define RCU_INT_IRC40KSTBIF BIT(0) /*!< IRC40K stabilization interrupt flag */ 98 #define RCU_INT_LXTALSTBIF BIT(1) /*!< LXTAL stabilization interrupt flag */ 99 #define RCU_INT_IRC8MSTBIF BIT(2) /*!< IRC8M stabilization interrupt flag */ 100 #define RCU_INT_HXTALSTBIF BIT(3) /*!< HXTAL stabilization interrupt flag */ 101 #define RCU_INT_PLLSTBIF BIT(4) /*!< PLL stabilization interrupt flag */ 102 #define RCU_INT_IRC28MSTBIF BIT(5) /*!< IRC28M stabilization interrupt flag */ 103 #define RCU_INT_CKMIF BIT(7) /*!< HXTAL clock stuck interrupt flag */ 104 #define RCU_INT_IRC40KSTBIE BIT(8) /*!< IRC40K stabilization interrupt enable */ 105 #define RCU_INT_LXTALSTBIE BIT(9) /*!< LXTAL stabilization interrupt enable */ 106 #define RCU_INT_IRC8MSTBIE BIT(10) /*!< IRC8M stabilization interrupt enable */ 107 #define RCU_INT_HXTALSTBIE BIT(11) /*!< HXTAL stabilization interrupt enable */ 108 #define RCU_INT_PLLSTBIE BIT(12) /*!< PLL stabilization interrupt enable */ 109 #define RCU_INT_IRC28MSTBIE BIT(13) /*!< IRC28M stabilization interrupt enable */ 110 #define RCU_INT_IRC40KSTBIC BIT(16) /*!< IRC40K stabilization interrupt clear */ 111 #define RCU_INT_LXTALSTBIC BIT(17) /*!< LXTAL stabilization interrupt clear */ 112 #define RCU_INT_IRC8MSTBIC BIT(18) /*!< IRC8M stabilization interrupt clear */ 113 #define RCU_INT_HXTALSTBIC BIT(19) /*!< HXTAL stabilization interrupt clear */ 114 #define RCU_INT_PLLSTBIC BIT(20) /*!< PLL stabilization interrupt clear */ 115 #define RCU_INT_IRC28MSTBIC BIT(21) /*!< IRC28M stabilization interrupt clear */ 116 #define RCU_INT_CKMIC BIT(23) /*!< HXTAL clock stuck interrupt clear */ 117 118 /* RCU_APB2RST */ 119 #define RCU_APB2RST_CFGRST BIT(0) /*!< system configuration reset */ 120 #define RCU_APB2RST_ADCRST BIT(9) /*!< ADC reset */ 121 #define RCU_APB2RST_TIMER0RST BIT(11) /*!< TIMER0 reset */ 122 #define RCU_APB2RST_SPI0RST BIT(12) /*!< SPI0 reset */ 123 #define RCU_APB2RST_USART0RST BIT(14) /*!< USART0 reset */ 124 #define RCU_APB2RST_TIMER14RST BIT(16) /*!< TIMER14 reset */ 125 #define RCU_APB2RST_TIMER15RST BIT(17) /*!< TIMER15 reset */ 126 #define RCU_APB2RST_TIMER16RST BIT(18) /*!< TIMER16 reset */ 127 128 /* RCU_APB1RST */ 129 #define RCU_APB1RST_TIMER1RST BIT(0) /*!< TIMER1 timer reset */ 130 #define RCU_APB1RST_TIMER2RST BIT(1) /*!< TIMER2 timer reset */ 131 #define RCU_APB1RST_TIMER5RST BIT(4) /*!< TIMER5 timer reset */ 132 #define RCU_APB1RST_TIMER13RST BIT(8) /*!< TIMER13 timer reset */ 133 #define RCU_APB1RST_WWDGTRST BIT(11) /*!< window watchdog timer reset */ 134 #define RCU_APB1RST_SPI1RST BIT(14) /*!< SPI1 reset */ 135 #define RCU_APB1RST_USART1RST BIT(17) /*!< USART1 reset */ 136 #define RCU_APB1RST_I2C0RST BIT(21) /*!< I2C0 reset */ 137 #define RCU_APB1RST_I2C1RST BIT(22) /*!< I2C1 reset */ 138 #define RCU_APB1RST_PMURST BIT(28) /*!< power control reset */ 139 #define RCU_APB1RST_DACRST BIT(29) /*!< DAC reset */ 140 #define RCU_APB1RST_CECRST BIT(30) /*!< HDMI CEC reset */ 141 142 /* RCU_AHBEN */ 143 #define RCU_AHBEN_DMAEN BIT(0) /*!< DMA clock enable */ 144 #define RCU_AHBEN_SRAMSPEN BIT(2) /*!< SRAM interface clock enable */ 145 #define RCU_AHBEN_FMCSPEN BIT(4) /*!< FMC clock enable */ 146 #define RCU_AHBEN_CRCEN BIT(6) /*!< CRC clock enable */ 147 #define RCU_AHBEN_USBFS BIT(12) /*!< USBFS clock enable */ 148 #define RCU_AHBEN_PAEN BIT(17) /*!< GPIO port A clock enable */ 149 #define RCU_AHBEN_PBEN BIT(18) /*!< GPIO port B clock enable */ 150 #define RCU_AHBEN_PCEN BIT(19) /*!< GPIO port C clock enable */ 151 #define RCU_AHBEN_PDEN BIT(20) /*!< GPIO port D clock enable */ 152 #define RCU_AHBEN_PFEN BIT(22) /*!< GPIO port F clock enable */ 153 #define RCU_AHBEN_TSIEN BIT(24) /*!< TSI clock enable */ 154 155 /* RCU_APB2EN */ 156 #define RCU_APB2EN_CFGCMPEN BIT(0) /*!< system configuration and comparator clock enable */ 157 #define RCU_APB2EN_ADCEN BIT(9) /*!< ADC interface clock enable */ 158 #define RCU_APB2EN_TIMER0EN BIT(11) /*!< TIMER0 timer clock enable */ 159 #define RCU_APB2EN_SPI0EN BIT(12) /*!< SPI0 clock enable */ 160 #define RCU_APB2EN_USART0EN BIT(14) /*!< USART0 clock enable */ 161 #define RCU_APB2EN_TIMER14EN BIT(16) /*!< TIMER14 timer clock enable */ 162 #define RCU_APB2EN_TIMER15EN BIT(17) /*!< TIMER15 timer clock enable */ 163 #define RCU_APB2EN_TIMER16EN BIT(18) /*!< TIMER16 timer clock enable */ 164 165 /* RCU_APB1EN */ 166 #define RCU_APB1EN_TIMER1EN BIT(0) /*!< TIMER1 timer clock enable */ 167 #define RCU_APB1EN_TIMER2EN BIT(1) /*!< TIMER2 timer clock enable */ 168 #define RCU_APB1EN_TIMER5EN BIT(4) /*!< TIMER5 timer clock enable */ 169 #define RCU_APB1EN_TIMER13EN BIT(8) /*!< TIMER13 timer clock enable */ 170 #define RCU_APB1EN_WWDGTEN BIT(11) /*!< window watchdog timer clock enable */ 171 #define RCU_APB1EN_SPI1EN BIT(14) /*!< SPI1 clock enable */ 172 #define RCU_APB1EN_USART1EN BIT(17) /*!< USART1 clock enable */ 173 #define RCU_APB1EN_I2C0EN BIT(21) /*!< I2C0 clock enable */ 174 #define RCU_APB1EN_I2C1EN BIT(22) /*!< I2C1 clock enable */ 175 #define RCU_APB1EN_PMUEN BIT(28) /*!< power interface clock enable */ 176 #define RCU_APB1EN_DACEN BIT(29) /*!< DAC interface clock enable */ 177 #define RCU_APB1EN_CECEN BIT(30) /*!< HDMI CEC interface clock enable */ 178 179 /* RCU_BDCTL */ 180 #define RCU_BDCTL_LXTALEN BIT(0) /*!< LXTAL enable */ 181 #define RCU_BDCTL_LXTALSTB BIT(1) /*!< external low-speed oscillator stabilization */ 182 #define RCU_BDCTL_LXTALBPS BIT(2) /*!< LXTAL bypass mode enable */ 183 #define RCU_BDCTL_LXTALDRI BITS(3,4) /*!< LXTAL drive capability */ 184 #define RCU_BDCTL_RTCSRC BITS(8,9) /*!< RTC clock entry selection */ 185 #define RCU_BDCTL_RTCEN BIT(15) /*!< RTC clock enable */ 186 #define RCU_BDCTL_BKPRST BIT(16) /*!< backup domain reset */ 187 188 /* RCU_RSTSCK */ 189 #define RCU_RSTSCK_IRC40KEN BIT(0) /*!< IRC40K enable */ 190 #define RCU_RSTSCK_IRC40KSTB BIT(1) /*!< IRC40K stabilization */ 191 #define RCU_RSTSCK_V12RSTF BIT(23) /*!< V12 domain power reset flag */ 192 #define RCU_RSTSCK_RSTFC BIT(24) /*!< reset flag clear */ 193 #define RCU_RSTSCK_OBLRSTF BIT(25) /*!< option byte loader reset flag */ 194 #define RCU_RSTSCK_EPRSTF BIT(26) /*!< external pin reset flag */ 195 #define RCU_RSTSCK_PORRSTF BIT(27) /*!< power reset flag */ 196 #define RCU_RSTSCK_SWRSTF BIT(28) /*!< software reset flag */ 197 #define RCU_RSTSCK_FWDGTRSTF BIT(29) /*!< free watchdog timer reset flag */ 198 #define RCU_RSTSCK_WWDGTRSTF BIT(30) /*!< window watchdog timer reset flag */ 199 #define RCU_RSTSCK_LPRSTF BIT(31) /*!< low-power reset flag */ 200 201 /* RCU_AHBRST */ 202 #define RCU_AHBRST_USBFSRST BIT(12) /*!< USBFS reset */ 203 #define RCU_AHBRST_PARST BIT(17) /*!< GPIO port A reset */ 204 #define RCU_AHBRST_PBRST BIT(18) /*!< GPIO port B reset */ 205 #define RCU_AHBRST_PCRST BIT(19) /*!< GPIO port C reset */ 206 #define RCU_AHBRST_PDRST BIT(20) /*!< GPIO port D reset */ 207 #define RCU_AHBRST_PFRST BIT(22) /*!< GPIO port F reset */ 208 #define RCU_AHBRST_TSIRST BIT(24) /*!< TSI unit reset */ 209 210 /* RCU_CFG1 */ 211 #define RCU_CFG1_PREDV BITS(0,3) /*!< CK_HXTAL divider previous PLL */ 212 #define RCU_CFG1_PLLPRESEL BIT(30) /*!< PLL clock source preselection */ 213 #define RCU_CFG1_PLLMF5 BIT(31) /*!< bit 5 of PLLMF */ 214 215 /* RCU_CFG2 */ 216 #define RCU_CFG2_USART0SEL BITS(0,1) /*!< CK_USART0 clock source selection */ 217 #define RCU_CFG2_CECSEL BIT(6) /*!< CK_CEC clock source selection */ 218 #define RCU_CFG2_ADCSEL BIT(8) /*!< CK_ADC clock source selection */ 219 #define RCU_CFG2_IRC28MDIV BIT(16) /*!< CK_IRC28M divider 2 or not */ 220 #define RCU_CFG2_USBFSPSC2 BIT(30) /*!< bit 2 of USBFSPSC */ 221 #define RCU_CFG2_ADCPSC2 BIT(31) /*!< bit 2 of ADCPSC */ 222 223 /* RCU_CTL1 */ 224 #define RCU_CTL1_IRC28MEN BIT(0) /*!< IRC28M internal 28M RC oscillator enable */ 225 #define RCU_CTL1_IRC28MSTB BIT(1) /*!< IRC28M internal 28M RC oscillator stabilization flag */ 226 #define RCU_CTL1_IRC28MADJ BITS(3,7) /*!< internal 28M RC oscillator clock trim adjust value */ 227 #define RCU_CTL1_IRC28MCALIB BITS(8,15) /*!< internal 28M RC oscillator calibration value register */ 228 229 /* RCU_ADDCTL */ 230 #define RCU_ADDCTL_CK48MSEL BIT(0) /*!< 48M clock selection */ 231 #define RCU_ADDCTL_IRC48MEN BIT(16) /*!< IRC48M internal 48M RC oscillator enable */ 232 #define RCU_ADDCTL_IRC48MSTB BIT(17) /*!< internal 48M RC oscillator stabilization flag */ 233 #define RCU_ADDCTL_IRC48MCALIB BITS(24,31) /*!< internal 48M RC oscillator calibration value register */ 234 235 /* RCU_ADDINT */ 236 #define RCU_ADDINT_IRC48MSTBIF BIT(6) /*!< IRC48M stabilization interrupt flag */ 237 #define RCU_ADDINT_IRC48MSTBIE BIT(14) /*!< IRC48M stabilization interrupt enable */ 238 #define RCU_ADDINT_IRC48MSTBIC BIT(22) /*!< IRC48M stabilization interrupt clear */ 239 240 /* RCU_ADDAPB1EN */ 241 #define RCU_ADDAPB1EN_CTCEN BIT(27) /*!< CTC unit clock enable */ 242 243 /* RCU_ADDAPB1RST */ 244 #define RCU_ADDAPB1RST_CTCRST BIT(27) /*!< CTC unit reset */ 245 246 /* RCU_VKEY */ 247 #define RCU_VKEY_KEY BITS(0,31) /*!< key of RCU_DSV register */ 248 249 /* RCU_DSV */ 250 #define RCU_DSV_DSLPVS BITS(0,1) /*!< deep-sleep mode voltage select */ 251 252 /* constants definitions */ 253 /* define the peripheral clock enable bit position and its register index offset */ 254 #define RCU_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx)<<6) | (uint32_t)(bitpos)) 255 #define RCU_REG_VAL(periph) (REG32(RCU + ((uint32_t)(periph)>>6))) 256 #define RCU_BIT_POS(val) ((uint32_t)(val) & (uint32_t)0x0000001FU) 257 /* define the voltage key unlock value */ 258 #define RCU_VKEY_UNLOCK ((uint32_t)0x1A2B3C4DU) 259 260 /* register index */ 261 typedef enum 262 { 263 /* peripherals enable */ 264 IDX_AHBEN = ((uint32_t)0x00000014U), 265 IDX_APB2EN = ((uint32_t)0x00000018U), 266 IDX_APB1EN = ((uint32_t)0x0000001CU), 267 IDX_ADDAPB1EN = ((uint32_t)0x000000F8U), 268 /* peripherals reset */ 269 IDX_AHBRST = ((uint32_t)0x00000028U), 270 IDX_APB2RST = ((uint32_t)0x0000000CU), 271 IDX_APB1RST = ((uint32_t)0x00000010U), 272 IDX_ADDAPB1RST = ((uint32_t)0x000000FCU), 273 /* clock stabilization */ 274 IDX_CTL0 = ((uint32_t)0x00000000U), 275 IDX_BDCTL = ((uint32_t)0x00000020U), 276 IDX_CTL1 = ((uint32_t)0x00000034U), 277 IDX_ADDCTL = ((uint32_t)0x000000C0U), 278 /* peripheral reset */ 279 IDX_RSTSCK = ((uint32_t)0x00000024U), 280 /* clock stabilization and stuck interrupt */ 281 IDX_INT = ((uint32_t)0x00000008U), 282 IDX_ADDINT = ((uint32_t)0x000000CCU), 283 /* configuration register */ 284 IDX_CFG0 = ((uint32_t)0x00000004U), 285 IDX_CFG2 = ((uint32_t)0x00000030U) 286 }reg_idx; 287 288 /* peripheral clock enable */ 289 typedef enum 290 { 291 /* AHB peripherals */ 292 RCU_DMA = RCU_REGIDX_BIT(IDX_AHBEN, 0U), /*!< DMA clock */ 293 RCU_CRC = RCU_REGIDX_BIT(IDX_AHBEN, 6U), /*!< CRC clock */ 294 RCU_GPIOA = RCU_REGIDX_BIT(IDX_AHBEN, 17U), /*!< GPIOA clock */ 295 RCU_GPIOB = RCU_REGIDX_BIT(IDX_AHBEN, 18U), /*!< GPIOB clock */ 296 RCU_GPIOC = RCU_REGIDX_BIT(IDX_AHBEN, 19U), /*!< GPIOC clock */ 297 RCU_GPIOD = RCU_REGIDX_BIT(IDX_AHBEN, 20U), /*!< GPIOD clock */ 298 RCU_GPIOF = RCU_REGIDX_BIT(IDX_AHBEN, 22U), /*!< GPIOF clock */ 299 RCU_TSI = RCU_REGIDX_BIT(IDX_AHBEN, 24U), /*!< TSI clock */ 300 301 /* APB2 peripherals */ 302 RCU_CFGCMP = RCU_REGIDX_BIT(IDX_APB2EN, 0U), /*!< CFGCMP clock */ 303 RCU_ADC = RCU_REGIDX_BIT(IDX_APB2EN, 9U), /*!< ADC clock */ 304 RCU_TIMER0 = RCU_REGIDX_BIT(IDX_APB2EN, 11U), /*!< TIMER0 clock */ 305 RCU_SPI0 = RCU_REGIDX_BIT(IDX_APB2EN, 12U), /*!< SPI0 clock */ 306 RCU_USART0 = RCU_REGIDX_BIT(IDX_APB2EN, 14U), /*!< USART0 clock */ 307 RCU_TIMER14 = RCU_REGIDX_BIT(IDX_APB2EN, 16U), /*!< TIMER14 clock */ 308 RCU_TIMER15 = RCU_REGIDX_BIT(IDX_APB2EN, 17U), /*!< TIMER15 clock */ 309 RCU_TIMER16 = RCU_REGIDX_BIT(IDX_APB2EN, 18U), /*!< TIMER16 clock */ 310 311 /* APB1 peripherals */ 312 RCU_TIMER1 = RCU_REGIDX_BIT(IDX_APB1EN, 0U), /*!< TIMER1 clock */ 313 RCU_TIMER2 = RCU_REGIDX_BIT(IDX_APB1EN, 1U), /*!< TIMER2 clock */ 314 RCU_TIMER13 = RCU_REGIDX_BIT(IDX_APB1EN, 8U), /*!< TIMER13 clock */ 315 RCU_WWDGT = RCU_REGIDX_BIT(IDX_APB1EN, 11U), /*!< WWDGT clock */ 316 RCU_SPI1 = RCU_REGIDX_BIT(IDX_APB1EN, 14U), /*!< SPI1 clock */ 317 RCU_USART1 = RCU_REGIDX_BIT(IDX_APB1EN, 17U), /*!< USART1 clock */ 318 RCU_I2C0 = RCU_REGIDX_BIT(IDX_APB1EN, 21U), /*!< I2C0 clock */ 319 RCU_I2C1 = RCU_REGIDX_BIT(IDX_APB1EN, 22U), /*!< I2C1 clock */ 320 RCU_PMU = RCU_REGIDX_BIT(IDX_APB1EN, 28U), /*!< PMU clock */ 321 #if defined(GD32F350) 322 RCU_DAC = RCU_REGIDX_BIT(IDX_APB1EN, 29U), /*!< DAC clock */ 323 RCU_CEC = RCU_REGIDX_BIT(IDX_APB1EN, 30U), /*!< CEC clock */ 324 RCU_TIMER5 = RCU_REGIDX_BIT(IDX_APB1EN, 4U), /*!< TIMER5 clock */ 325 RCU_USBFS = RCU_REGIDX_BIT(IDX_AHBEN, 12U), /*!< USBFS clock */ 326 #endif /* GD32F350 */ 327 RCU_RTC = RCU_REGIDX_BIT(IDX_BDCTL, 15U), /*!< RTC clock */ 328 329 /* RCU_ADDAPB1EN */ 330 RCU_CTC = RCU_REGIDX_BIT(IDX_ADDAPB1EN, 27U) /*!< CTC clock */ 331 }rcu_periph_enum; 332 333 /* peripheral clock enable when sleep mode*/ 334 typedef enum 335 { 336 /* AHB peripherals */ 337 RCU_SRAM_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 2U), /*!< SRAM clock */ 338 RCU_FMC_SLP = RCU_REGIDX_BIT(IDX_AHBEN, 4U), /*!< FMC clock */ 339 }rcu_periph_sleep_enum; 340 341 /* peripherals reset */ 342 typedef enum 343 { 344 /* AHB peripherals reset */ 345 RCU_GPIOARST = RCU_REGIDX_BIT(IDX_AHBRST, 17U), /*!< GPIOA reset */ 346 RCU_GPIOBRST = RCU_REGIDX_BIT(IDX_AHBRST, 18U), /*!< GPIOB reset */ 347 RCU_GPIOCRST = RCU_REGIDX_BIT(IDX_AHBRST, 19U), /*!< GPIOC reset */ 348 RCU_GPIODRST = RCU_REGIDX_BIT(IDX_AHBRST, 20U), /*!< GPIOD reset */ 349 RCU_GPIOFRST = RCU_REGIDX_BIT(IDX_AHBRST, 22U), /*!< GPIOF reset */ 350 RCU_TSIRST = RCU_REGIDX_BIT(IDX_AHBRST, 24U), /*!< TSI reset */ 351 352 /* APB2 peripherals reset */ 353 RCU_CFGCMPRST = RCU_REGIDX_BIT(IDX_APB2RST, 0U), /*!< CFGCMP reset */ 354 RCU_ADCRST = RCU_REGIDX_BIT(IDX_APB2RST, 9U), /*!< ADC reset */ 355 RCU_TIMER0RST = RCU_REGIDX_BIT(IDX_APB2RST, 11U), /*!< TIMER0 reset */ 356 RCU_SPI0RST = RCU_REGIDX_BIT(IDX_APB2RST, 12U), /*!< SPI0 reset */ 357 RCU_USART0RST = RCU_REGIDX_BIT(IDX_APB2RST, 14U), /*!< USART0 reset */ 358 RCU_TIMER14RST = RCU_REGIDX_BIT(IDX_APB2RST, 16U), /*!< TIMER14 reset */ 359 RCU_TIMER15RST = RCU_REGIDX_BIT(IDX_APB2RST, 17U), /*!< TIMER15 reset */ 360 RCU_TIMER16RST = RCU_REGIDX_BIT(IDX_APB2RST, 18U), /*!< TIMER16 reset */ 361 362 /* APB1 peripherals reset */ 363 RCU_TIMER1RST = RCU_REGIDX_BIT(IDX_APB1RST, 0U), /*!< TIMER1 reset */ 364 RCU_TIMER2RST = RCU_REGIDX_BIT(IDX_APB1RST, 1U), /*!< TIMER2 reset */ 365 RCU_TIMER13RST = RCU_REGIDX_BIT(IDX_APB1RST, 8U), /*!< TIMER13 reset */ 366 RCU_WWDGTRST = RCU_REGIDX_BIT(IDX_APB1RST, 11U), /*!< WWDGT reset */ 367 RCU_SPI1RST = RCU_REGIDX_BIT(IDX_APB1RST, 14U), /*!< SPI1 reset */ 368 RCU_USART1RST = RCU_REGIDX_BIT(IDX_APB1RST, 17U), /*!< USART1 reset */ 369 RCU_I2C0RST = RCU_REGIDX_BIT(IDX_APB1RST, 21U), /*!< I2C0 reset */ 370 RCU_I2C1RST = RCU_REGIDX_BIT(IDX_APB1RST, 22U), /*!< I2C1 reset */ 371 RCU_PMURST = RCU_REGIDX_BIT(IDX_APB1RST, 28U), /*!< PMU reset */ 372 #if defined(GD32F350) 373 RCU_DACRST = RCU_REGIDX_BIT(IDX_APB1RST, 29U), /*!< DAC reset */ 374 RCU_CECRST = RCU_REGIDX_BIT(IDX_APB1RST, 30U), /*!< CEC reset */ 375 RCU_TIMER5RST = RCU_REGIDX_BIT(IDX_APB1RST, 4U), /*!< TIMER5 reset */ 376 RCU_USBFSRST = RCU_REGIDX_BIT(IDX_AHBRST, 12U), /*!< USBFS reset */ 377 #endif /* GD32F350 */ 378 /* RCU_ADDAPB1RST */ 379 RCU_CTCRST = RCU_REGIDX_BIT(IDX_ADDAPB1RST, 27U), /*!< CTC reset */ 380 }rcu_periph_reset_enum; 381 382 /* clock stabilization and peripheral reset flags */ 383 typedef enum 384 { 385 RCU_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_RSTSCK, 1U), /*!< IRC40K stabilization flags */ 386 RCU_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_BDCTL, 1U), /*!< LXTAL stabilization flags */ 387 RCU_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_CTL0, 1U), /*!< IRC8M stabilization flags */ 388 RCU_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_CTL0, 17U), /*!< HXTAL stabilization flags */ 389 RCU_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_CTL0, 25U), /*!< PLL stabilization flags */ 390 RCU_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_CTL1, 1U), /*!< IRC28M stabilization flags */ 391 RCU_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDCTL, 17U), /*!< IRC48M stabilization flags */ 392 393 RCU_FLAG_V12RST = RCU_REGIDX_BIT(IDX_RSTSCK, 23U), /*!< V12 reset flags */ 394 RCU_FLAG_OBLRST = RCU_REGIDX_BIT(IDX_RSTSCK, 25U), /*!< OBL reset flags */ 395 RCU_FLAG_EPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 26U), /*!< EPR reset flags */ 396 RCU_FLAG_PORRST = RCU_REGIDX_BIT(IDX_RSTSCK, 27U), /*!< power reset flags */ 397 RCU_FLAG_SWRST = RCU_REGIDX_BIT(IDX_RSTSCK, 28U), /*!< SW reset flags */ 398 RCU_FLAG_FWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 29U), /*!< FWDGT reset flags */ 399 RCU_FLAG_WWDGTRST = RCU_REGIDX_BIT(IDX_RSTSCK, 30U), /*!< WWDGT reset flags */ 400 RCU_FLAG_LPRST = RCU_REGIDX_BIT(IDX_RSTSCK, 31U) /*!< LP reset flags */ 401 }rcu_flag_enum; 402 403 /* clock stabilization and ckm interrupt flags */ 404 typedef enum 405 { 406 RCU_INT_FLAG_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 0U), /*!< IRC40K stabilization interrupt flag */ 407 RCU_INT_FLAG_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 1U), /*!< LXTAL stabilization interrupt flag */ 408 RCU_INT_FLAG_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 2U), /*!< IRC8M stabilization interrupt flag */ 409 RCU_INT_FLAG_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 3U), /*!< HXTAL stabilization interrupt flag */ 410 RCU_INT_FLAG_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 4U), /*!< PLL stabilization interrupt flag */ 411 RCU_INT_FLAG_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 5U), /*!< IRC28M stabilization interrupt flag */ 412 RCU_INT_FLAG_CKM = RCU_REGIDX_BIT(IDX_INT, 7U), /*!< CKM interrupt flag */ 413 RCU_INT_FLAG_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 6U) /*!< IRC48M stabilization interrupt flag */ 414 }rcu_int_flag_enum; 415 416 /* clock stabilization and stuck interrupt flags clear */ 417 typedef enum 418 { 419 RCU_INT_FLAG_IRC40KSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 16U), /*!< IRC40K stabilization interrupt flags clear */ 420 RCU_INT_FLAG_LXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 17U), /*!< LXTAL stabilization interrupt flags clear */ 421 RCU_INT_FLAG_IRC8MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 18U), /*!< IRC8M stabilization interrupt flags clear */ 422 RCU_INT_FLAG_HXTALSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 19U), /*!< HXTAL stabilization interrupt flags clear */ 423 RCU_INT_FLAG_PLLSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 20U), /*!< PLL stabilization interrupt flags clear */ 424 RCU_INT_FLAG_IRC28MSTB_CLR = RCU_REGIDX_BIT(IDX_INT, 21U), /*!< IRC28M stabilization interrupt flags clear */ 425 RCU_INT_FLAG_CKM_CLR = RCU_REGIDX_BIT(IDX_INT, 23U), /*!< CKM interrupt flags clear */ 426 RCU_INT_FLAG_IRC48MSTB_CLR = RCU_REGIDX_BIT(IDX_ADDINT, 22U) /*!< IRC48M stabilization interrupt flag clear */ 427 }rcu_int_flag_clear_enum; 428 429 /* clock stabilization interrupt enable or disable */ 430 typedef enum 431 { 432 RCU_INT_IRC40KSTB = RCU_REGIDX_BIT(IDX_INT, 8U), /*!< IRC40K stabilization interrupt */ 433 RCU_INT_LXTALSTB = RCU_REGIDX_BIT(IDX_INT, 9U), /*!< LXTAL stabilization interrupt */ 434 RCU_INT_IRC8MSTB = RCU_REGIDX_BIT(IDX_INT, 10U), /*!< IRC8M stabilization interrupt */ 435 RCU_INT_HXTALSTB = RCU_REGIDX_BIT(IDX_INT, 11U), /*!< HXTAL stabilization interrupt */ 436 RCU_INT_PLLSTB = RCU_REGIDX_BIT(IDX_INT, 12U), /*!< PLL stabilization interrupt */ 437 RCU_INT_IRC28MSTB = RCU_REGIDX_BIT(IDX_INT, 13U), /*!< IRC28M stabilization interrupt */ 438 RCU_INT_IRC48MSTB = RCU_REGIDX_BIT(IDX_ADDINT, 14U) /*!< IRC48M stabilization interrupt */ 439 }rcu_int_enum; 440 441 /* ADC clock source */ 442 typedef enum 443 { 444 RCU_ADCCK_IRC28M_DIV2 = 0U, /*!< ADC clock source select IRC28M/2 */ 445 RCU_ADCCK_IRC28M, /*!< ADC clock source select IRC28M */ 446 RCU_ADCCK_APB2_DIV2, /*!< ADC clock source select APB2/2 */ 447 RCU_ADCCK_AHB_DIV3, /*!< ADC clock source select AHB/3 */ 448 RCU_ADCCK_APB2_DIV4, /*!< ADC clock source select APB2/4 */ 449 RCU_ADCCK_AHB_DIV5, /*!< ADC clock source select AHB/5 */ 450 RCU_ADCCK_APB2_DIV6, /*!< ADC clock source select APB2/6 */ 451 RCU_ADCCK_AHB_DIV7, /*!< ADC clock source select AHB/7 */ 452 RCU_ADCCK_APB2_DIV8, /*!< ADC clock source select APB2/8 */ 453 RCU_ADCCK_AHB_DIV9 /*!< ADC clock source select AHB/9 */ 454 }rcu_adc_clock_enum; 455 456 /* oscillator types */ 457 typedef enum 458 { 459 RCU_HXTAL = RCU_REGIDX_BIT(IDX_CTL0, 16U), /*!< HXTAL */ 460 RCU_LXTAL = RCU_REGIDX_BIT(IDX_BDCTL, 0U), /*!< LXTAL */ 461 RCU_IRC8M = RCU_REGIDX_BIT(IDX_CTL0, 0U), /*!< IRC8M */ 462 RCU_IRC28M = RCU_REGIDX_BIT(IDX_CTL1, 0U), /*!< IRC28M */ 463 RCU_IRC48M = RCU_REGIDX_BIT(IDX_ADDCTL, 16U), /*!< IRC48M */ 464 RCU_IRC40K = RCU_REGIDX_BIT(IDX_RSTSCK, 0U), /*!< IRC40K */ 465 RCU_PLL_CK = RCU_REGIDX_BIT(IDX_CTL0, 24U) /*!< PLL */ 466 }rcu_osci_type_enum; 467 468 /* rcu clock frequency */ 469 typedef enum 470 { 471 CK_SYS = 0U, /*!< system clock */ 472 CK_AHB, /*!< AHB clock */ 473 CK_APB1, /*!< APB1 clock */ 474 CK_APB2, /*!< APB2 clock */ 475 CK_ADC, /*!< ADC clock */ 476 CK_CEC, /*!< CEC clock */ 477 CK_USART /*!< USART clock */ 478 }rcu_clock_freq_enum; 479 480 /* system clock source select */ 481 #define CFG0_SCS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 482 #define RCU_CKSYSSRC_IRC8M CFG0_SCS(0) /*!< system clock source select IRC8M */ 483 #define RCU_CKSYSSRC_HXTAL CFG0_SCS(1) /*!< system clock source select HXTAL */ 484 #define RCU_CKSYSSRC_PLL CFG0_SCS(2) /*!< system clock source select PLL */ 485 486 /* system clock source select status */ 487 #define CFG0_SCSS(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 488 #define RCU_SCSS_IRC8M CFG0_SCSS(0) /*!< system clock source select IRC8M */ 489 #define RCU_SCSS_HXTAL CFG0_SCSS(1) /*!< system clock source select HXTAL */ 490 #define RCU_SCSS_PLL CFG0_SCSS(2) /*!< system clock source select PLL */ 491 492 /* AHB prescaler selection */ 493 #define CFG0_AHBPSC(regval) (BITS(4,7) & ((uint32_t)(regval) << 4)) 494 #define RCU_AHB_CKSYS_DIV1 CFG0_AHBPSC(0) /*!< AHB prescaler select CK_SYS */ 495 #define RCU_AHB_CKSYS_DIV2 CFG0_AHBPSC(8) /*!< AHB prescaler select CK_SYS/2 */ 496 #define RCU_AHB_CKSYS_DIV4 CFG0_AHBPSC(9) /*!< AHB prescaler select CK_SYS/4 */ 497 #define RCU_AHB_CKSYS_DIV8 CFG0_AHBPSC(10) /*!< AHB prescaler select CK_SYS/8 */ 498 #define RCU_AHB_CKSYS_DIV16 CFG0_AHBPSC(11) /*!< AHB prescaler select CK_SYS/16 */ 499 #define RCU_AHB_CKSYS_DIV64 CFG0_AHBPSC(12) /*!< AHB prescaler select CK_SYS/64 */ 500 #define RCU_AHB_CKSYS_DIV128 CFG0_AHBPSC(13) /*!< AHB prescaler select CK_SYS/128 */ 501 #define RCU_AHB_CKSYS_DIV256 CFG0_AHBPSC(14) /*!< AHB prescaler select CK_SYS/256 */ 502 #define RCU_AHB_CKSYS_DIV512 CFG0_AHBPSC(15) /*!< AHB prescaler select CK_SYS/512 */ 503 504 /* APB1 prescaler selection */ 505 #define CFG0_APB1PSC(regval) (BITS(8,10) & ((uint32_t)(regval) << 8)) 506 #define RCU_APB1_CKAHB_DIV1 CFG0_APB1PSC(0) /*!< APB1 prescaler select CK_AHB */ 507 #define RCU_APB1_CKAHB_DIV2 CFG0_APB1PSC(4) /*!< APB1 prescaler select CK_AHB/2 */ 508 #define RCU_APB1_CKAHB_DIV4 CFG0_APB1PSC(5) /*!< APB1 prescaler select CK_AHB/4 */ 509 #define RCU_APB1_CKAHB_DIV8 CFG0_APB1PSC(6) /*!< APB1 prescaler select CK_AHB/8 */ 510 #define RCU_APB1_CKAHB_DIV16 CFG0_APB1PSC(7) /*!< APB1 prescaler select CK_AHB/16 */ 511 512 /* APB2 prescaler selection */ 513 #define CFG0_APB2PSC(regval) (BITS(11,13) & ((uint32_t)(regval) << 11)) 514 #define RCU_APB2_CKAHB_DIV1 CFG0_APB2PSC(0) /*!< APB2 prescaler select CK_AHB */ 515 #define RCU_APB2_CKAHB_DIV2 CFG0_APB2PSC(4) /*!< APB2 prescaler select CK_AHB/2 */ 516 #define RCU_APB2_CKAHB_DIV4 CFG0_APB2PSC(5) /*!< APB2 prescaler select CK_AHB/4 */ 517 #define RCU_APB2_CKAHB_DIV8 CFG0_APB2PSC(6) /*!< APB2 prescaler select CK_AHB/8 */ 518 #define RCU_APB2_CKAHB_DIV16 CFG0_APB2PSC(7) /*!< APB2 prescaler select CK_AHB/16 */ 519 520 /* ADC clock prescaler selection */ 521 #define CFG0_ADCPSC(regval) (BITS(14,15) & ((uint32_t)(regval) << 14)) 522 #define RCU_ADC_CKAPB2_DIV2 CFG0_ADCPSC(0) /*!< ADC clock prescaler select CK_APB2/2 */ 523 #define RCU_ADC_CKAPB2_DIV4 CFG0_ADCPSC(1) /*!< ADC clock prescaler select CK_APB2/4 */ 524 #define RCU_ADC_CKAPB2_DIV6 CFG0_ADCPSC(2) /*!< ADC clock prescaler select CK_APB2/6 */ 525 #define RCU_ADC_CKAPB2_DIV8 CFG0_ADCPSC(3) /*!< ADC clock prescaler select CK_APB2/8 */ 526 527 /* PLL clock source selection */ 528 #define RCU_PLLSRC_IRC8M_DIV2 ((uint32_t)0x00000000U) /*!< PLL clock source select IRC8M/2 */ 529 #define RCU_PLLSRC_HXTAL_IRC48M RCU_CFG0_PLLSEL /*!< PLL clock source select HXTAL or IRC48M*/ 530 531 /* PLL clock source preselection */ 532 #define RCU_PLLPRESEL_HXTAL ((uint32_t)0x00000000U) /*!< PLL clock source preselection HXTAL */ 533 #define RCU_PLLPRESEL_IRC48M RCU_CFG1_PLLPRESEL /*!< PLL clock source preselection IRC48M */ 534 535 /* HXTAL or IRC48M divider for PLL source clock selection */ 536 #define RCU_PLLPREDV ((uint32_t)0x00000000U) /*!< HXTAL or IRC48M clock selected */ 537 #define RCU_PLLPREDV_DIV2 RCU_CFG0_PLLPREDV /*!< (HXTAL or IRC48M) /2 clock selected */ 538 539 /* PLL multiply factor */ 540 #define CFG0_PLLMF(regval) (BITS(18,21) & ((uint32_t)(regval) << 18)) 541 #define RCU_PLL_MUL2 CFG0_PLLMF(0) /*!< PLL source clock multiply by 2 */ 542 #define RCU_PLL_MUL3 CFG0_PLLMF(1) /*!< PLL source clock multiply by 3 */ 543 #define RCU_PLL_MUL4 CFG0_PLLMF(2) /*!< PLL source clock multiply by 4 */ 544 #define RCU_PLL_MUL5 CFG0_PLLMF(3) /*!< PLL source clock multiply by 5 */ 545 #define RCU_PLL_MUL6 CFG0_PLLMF(4) /*!< PLL source clock multiply by 6 */ 546 #define RCU_PLL_MUL7 CFG0_PLLMF(5) /*!< PLL source clock multiply by 7 */ 547 #define RCU_PLL_MUL8 CFG0_PLLMF(6) /*!< PLL source clock multiply by 8 */ 548 #define RCU_PLL_MUL9 CFG0_PLLMF(7) /*!< PLL source clock multiply by 9 */ 549 #define RCU_PLL_MUL10 CFG0_PLLMF(8) /*!< PLL source clock multiply by 10 */ 550 #define RCU_PLL_MUL11 CFG0_PLLMF(9) /*!< PLL source clock multiply by 11 */ 551 #define RCU_PLL_MUL12 CFG0_PLLMF(10) /*!< PLL source clock multiply by 12 */ 552 #define RCU_PLL_MUL13 CFG0_PLLMF(11) /*!< PLL source clock multiply by 13 */ 553 #define RCU_PLL_MUL14 CFG0_PLLMF(12) /*!< PLL source clock multiply by 14 */ 554 #define RCU_PLL_MUL15 CFG0_PLLMF(13) /*!< PLL source clock multiply by 15 */ 555 #define RCU_PLL_MUL16 CFG0_PLLMF(14) /*!< PLL source clock multiply by 16 */ 556 #define RCU_PLL_MUL17 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(0)) /*!< PLL source clock multiply by 17 */ 557 #define RCU_PLL_MUL18 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(1)) /*!< PLL source clock multiply by 18 */ 558 #define RCU_PLL_MUL19 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(2)) /*!< PLL source clock multiply by 19 */ 559 #define RCU_PLL_MUL20 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(3)) /*!< PLL source clock multiply by 20 */ 560 #define RCU_PLL_MUL21 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(4)) /*!< PLL source clock multiply by 21 */ 561 #define RCU_PLL_MUL22 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(5)) /*!< PLL source clock multiply by 22 */ 562 #define RCU_PLL_MUL23 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(6)) /*!< PLL source clock multiply by 23 */ 563 #define RCU_PLL_MUL24 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(7)) /*!< PLL source clock multiply by 24 */ 564 #define RCU_PLL_MUL25 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(8)) /*!< PLL source clock multiply by 25 */ 565 #define RCU_PLL_MUL26 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(9)) /*!< PLL source clock multiply by 26 */ 566 #define RCU_PLL_MUL27 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(10)) /*!< PLL source clock multiply by 27 */ 567 #define RCU_PLL_MUL28 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(11)) /*!< PLL source clock multiply by 28 */ 568 #define RCU_PLL_MUL29 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(12)) /*!< PLL source clock multiply by 29 */ 569 #define RCU_PLL_MUL30 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(13)) /*!< PLL source clock multiply by 30 */ 570 #define RCU_PLL_MUL31 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(14)) /*!< PLL source clock multiply by 31 */ 571 #define RCU_PLL_MUL32 (RCU_CFG0_PLLMF4 | CFG0_PLLMF(15)) /*!< PLL source clock multiply by 32 */ 572 #define RCU_PLL_MUL33 (CFG0_PLLMF(0) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 33 */ 573 #define RCU_PLL_MUL34 (CFG0_PLLMF(1) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 34 */ 574 #define RCU_PLL_MUL35 (CFG0_PLLMF(2) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 35 */ 575 #define RCU_PLL_MUL36 (CFG0_PLLMF(3) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 36 */ 576 #define RCU_PLL_MUL37 (CFG0_PLLMF(4) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 37 */ 577 #define RCU_PLL_MUL38 (CFG0_PLLMF(5) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 38 */ 578 #define RCU_PLL_MUL39 (CFG0_PLLMF(6) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 39 */ 579 #define RCU_PLL_MUL40 (CFG0_PLLMF(7) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 40 */ 580 #define RCU_PLL_MUL41 (CFG0_PLLMF(8) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 41 */ 581 #define RCU_PLL_MUL42 (CFG0_PLLMF(9) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 42 */ 582 #define RCU_PLL_MUL43 (CFG0_PLLMF(10) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 43 */ 583 #define RCU_PLL_MUL44 (CFG0_PLLMF(11) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 44 */ 584 #define RCU_PLL_MUL45 (CFG0_PLLMF(12) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 45 */ 585 #define RCU_PLL_MUL46 (CFG0_PLLMF(13) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 46 */ 586 #define RCU_PLL_MUL47 (CFG0_PLLMF(14) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 47 */ 587 #define RCU_PLL_MUL48 (CFG0_PLLMF(15) | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 48 */ 588 #define RCU_PLL_MUL49 (RCU_CFG0_PLLMF4 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 49 */ 589 #define RCU_PLL_MUL50 (RCU_PLL_MUL18 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 50 */ 590 #define RCU_PLL_MUL51 (RCU_PLL_MUL19 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 51 */ 591 #define RCU_PLL_MUL52 (RCU_PLL_MUL20 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 52 */ 592 #define RCU_PLL_MUL53 (RCU_PLL_MUL21 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 53 */ 593 #define RCU_PLL_MUL54 (RCU_PLL_MUL22 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 54 */ 594 #define RCU_PLL_MUL55 (RCU_PLL_MUL23 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 55 */ 595 #define RCU_PLL_MUL56 (RCU_PLL_MUL24 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 56 */ 596 #define RCU_PLL_MUL57 (RCU_PLL_MUL25 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 57 */ 597 #define RCU_PLL_MUL58 (RCU_PLL_MUL26 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 58 */ 598 #define RCU_PLL_MUL59 (RCU_PLL_MUL27 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 59 */ 599 #define RCU_PLL_MUL60 (RCU_PLL_MUL28 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 60 */ 600 #define RCU_PLL_MUL61 (RCU_PLL_MUL29 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 61 */ 601 #define RCU_PLL_MUL62 (RCU_PLL_MUL30 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 62 */ 602 #define RCU_PLL_MUL63 (RCU_PLL_MUL31 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 63 */ 603 #define RCU_PLL_MUL64 (RCU_PLL_MUL32 | RCU_CFG1_PLLMF5) /*!< PLL source clock multiply by 64 */ 604 605 /* USBFS clock prescaler selection */ 606 #define CFG0_USBFSPSC(regval) (BITS(22,23) & ((uint32_t)(regval) << 22)) 607 #define RCU_USBFS_CKPLL_DIV1_5 CFG0_USBFSPSC(0) /*!< USBFS clock prescaler select CK_PLL/1.5 */ 608 #define RCU_USBFS_CKPLL_DIV1 CFG0_USBFSPSC(1) /*!< USBFS clock prescaler select CK_PLL */ 609 #define RCU_USBFS_CKPLL_DIV2_5 CFG0_USBFSPSC(2) /*!< USBFS clock prescaler select CK_PLL/2.5 */ 610 #define RCU_USBFS_CKPLL_DIV2 CFG0_USBFSPSC(3) /*!< USBFS clock prescaler select CK_PLL/2 */ 611 #define RCU_USBFS_CKPLL_DIV3 RCU_CFG2_USBFSPSC2 /*!< USBFS clock prescaler select CK_PLL/3 */ 612 #define RCU_USBFS_CKPLL_DIV3_5 (CFG0_USBFSPSC(1)|RCU_CFG2_USBFSPSC2) /*!< USBFS clock prescaler select CK_PLL/3.5 */ 613 614 /* CK_OUT clock source selection */ 615 #define CFG0_CKOUTSEL(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) 616 #define RCU_CKOUTSRC_NONE CFG0_CKOUTSEL(0) /*!< no clock selected */ 617 #define RCU_CKOUTSRC_IRC28M CFG0_CKOUTSEL(1) /*!< CK_OUT clock source select IRC28M */ 618 #define RCU_CKOUTSRC_IRC40K CFG0_CKOUTSEL(2) /*!< CK_OUT clock source select IRC40K */ 619 #define RCU_CKOUTSRC_LXTAL CFG0_CKOUTSEL(3) /*!< CK_OUT clock source select LXTAL */ 620 #define RCU_CKOUTSRC_CKSYS CFG0_CKOUTSEL(4) /*!< CK_OUT clock source select CKSYS */ 621 #define RCU_CKOUTSRC_IRC8M CFG0_CKOUTSEL(5) /*!< CK_OUT clock source select IRC8M */ 622 #define RCU_CKOUTSRC_HXTAL CFG0_CKOUTSEL(6) /*!< CK_OUT clock source select HXTAL */ 623 #define RCU_CKOUTSRC_CKPLL_DIV1 (RCU_CFG0_PLLDV | CFG0_CKOUTSEL(7)) /*!< CK_OUT clock source select CK_PLL */ 624 #define RCU_CKOUTSRC_CKPLL_DIV2 CFG0_CKOUTSEL(7) /*!< CK_OUT clock source select CK_PLL/2 */ 625 626 /* CK_OUT divider */ 627 #define CFG0_CKOUTDIV(regval) (BITS(28,30) & ((uint32_t)(regval) << 28)) 628 #define RCU_CKOUT_DIV1 CFG0_CKOUTDIV(0) /*!< CK_OUT is divided by 1 */ 629 #define RCU_CKOUT_DIV2 CFG0_CKOUTDIV(1) /*!< CK_OUT is divided by 2 */ 630 #define RCU_CKOUT_DIV4 CFG0_CKOUTDIV(2) /*!< CK_OUT is divided by 4 */ 631 #define RCU_CKOUT_DIV8 CFG0_CKOUTDIV(3) /*!< CK_OUT is divided by 8 */ 632 #define RCU_CKOUT_DIV16 CFG0_CKOUTDIV(4) /*!< CK_OUT is divided by 16 */ 633 #define RCU_CKOUT_DIV32 CFG0_CKOUTDIV(5) /*!< CK_OUT is divided by 32 */ 634 #define RCU_CKOUT_DIV64 CFG0_CKOUTDIV(6) /*!< CK_OUT is divided by 64 */ 635 #define RCU_CKOUT_DIV128 CFG0_CKOUTDIV(7) /*!< CK_OUT is divided by 128 */ 636 637 /* CK_PLL divide by 1 or 2 for CK_OUT */ 638 #define RCU_PLLDV_CKPLL_DIV2 ((uint32_t)0x00000000U) /*!< CK_PLL divide by 2 for CK_OUT */ 639 #define RCU_PLLDV_CKPLL RCU_CFG0_PLLDV /*!< CK_PLL divide by 1 for CK_OUT */ 640 641 /* LXTAL drive capability */ 642 #define BDCTL_LXTALDRI(regval) (BITS(3,4) & ((uint32_t)(regval) << 3)) 643 #define RCU_LXTAL_LOWDRI BDCTL_LXTALDRI(0) /*!< lower driving capability */ 644 #define RCU_LXTAL_MED_LOWDRI BDCTL_LXTALDRI(1) /*!< medium low driving capability */ 645 #define RCU_LXTAL_MED_HIGHDRI BDCTL_LXTALDRI(2) /*!< medium high driving capability */ 646 #define RCU_LXTAL_HIGHDRI BDCTL_LXTALDRI(3) /*!< higher driving capability */ 647 648 /* RTC clock entry selection */ 649 #define BDCTL_RTCSRC(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 650 #define RCU_RTCSRC_NONE BDCTL_RTCSRC(0) /*!< no clock selected */ 651 #define RCU_RTCSRC_LXTAL BDCTL_RTCSRC(1) /*!< LXTAL selected as RTC source clock */ 652 #define RCU_RTCSRC_IRC40K BDCTL_RTCSRC(2) /*!< IRC40K selected as RTC source clock */ 653 #define RCU_RTCSRC_HXTAL_DIV32 BDCTL_RTCSRC(3) /*!< HXTAL/32 selected as RTC source clock */ 654 655 /* CK_HXTAL divider previous PLL */ 656 #define CFG1_PREDV(regval) (BITS(0,3) & ((uint32_t)(regval) << 0)) 657 #define RCU_PLL_PREDV1 CFG1_PREDV(0) /*!< PLL not divided */ 658 #define RCU_PLL_PREDV2 CFG1_PREDV(1) /*!< PLL divided by 2 */ 659 #define RCU_PLL_PREDV3 CFG1_PREDV(2) /*!< PLL divided by 3 */ 660 #define RCU_PLL_PREDV4 CFG1_PREDV(3) /*!< PLL divided by 4 */ 661 #define RCU_PLL_PREDV5 CFG1_PREDV(4) /*!< PLL divided by 5 */ 662 #define RCU_PLL_PREDV6 CFG1_PREDV(5) /*!< PLL divided by 6 */ 663 #define RCU_PLL_PREDV7 CFG1_PREDV(6) /*!< PLL divided by 7 */ 664 #define RCU_PLL_PREDV8 CFG1_PREDV(7) /*!< PLL divided by 8 */ 665 #define RCU_PLL_PREDV9 CFG1_PREDV(8) /*!< PLL divided by 9 */ 666 #define RCU_PLL_PREDV10 CFG1_PREDV(9) /*!< PLL divided by 10 */ 667 #define RCU_PLL_PREDV11 CFG1_PREDV(10) /*!< PLL divided by 11 */ 668 #define RCU_PLL_PREDV12 CFG1_PREDV(11) /*!< PLL divided by 12 */ 669 #define RCU_PLL_PREDV13 CFG1_PREDV(12) /*!< PLL divided by 13 */ 670 #define RCU_PLL_PREDV14 CFG1_PREDV(13) /*!< PLL divided by 14 */ 671 #define RCU_PLL_PREDV15 CFG1_PREDV(14) /*!< PLL divided by 15 */ 672 #define RCU_PLL_PREDV16 CFG1_PREDV(15) /*!< PLL divided by 16 */ 673 674 /* USART0 clock source selection */ 675 #define CFG2_USART0SEL(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 676 #define RCU_USART0SRC_CKAPB2 CFG2_USART0SEL(0) /*!< CK_USART0 select CK_APB2 */ 677 #define RCU_USART0SRC_CKSYS CFG2_USART0SEL(1) /*!< CK_USART0 select CK_SYS */ 678 #define RCU_USART0SRC_LXTAL CFG2_USART0SEL(2) /*!< CK_USART0 select LXTAL */ 679 #define RCU_USART0SRC_IRC8M CFG2_USART0SEL(3) /*!< CK_USART0 select IRC8M */ 680 681 /* CEC clock source selection */ 682 #define RCU_CECSRC_IRC8M_DIV244 ((uint32_t)0x00000000U) /*!< CK_CEC clock source select IRC8M/244 */ 683 #define RCU_CECSRC_LXTAL RCU_CFG2_CECSEL /*!< CK_CEC clock source select LXTAL */ 684 685 /* ADC clock source selection */ 686 #define RCU_ADCSRC_IRC28M ((uint32_t)0x00000000U) /*!< ADC clock source select */ 687 #define RCU_ADCSRC_AHB_APB2DIV RCU_CFG2_ADCSEL /*!< ADC clock source select */ 688 689 /* IRC28M clock divider for ADC */ 690 #define RCU_ADC_IRC28M_DIV2 ((uint32_t)0x00000000U) /*!< IRC28M/2 select to ADC clock */ 691 #define RCU_ADC_IRC28M_DIV1 RCU_CFG2_IRC28MDIV /*!< IRC28M select to ADC clock */ 692 693 /* CK48M clock source selection */ 694 #define RCU_CK48MSRC_PLL48M ((uint32_t)0x00000000U) /*!< CK48M source clock select PLL48M */ 695 #define RCU_CK48MSRC_IRC48M RCU_ADDCTL_CK48MSEL /*!< CK48M source clock select IRC48M */ 696 697 /* Deep-sleep mode voltage */ 698 #define DSV_DSLPVS(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 699 #define RCU_DEEPSLEEP_V_1_0 DSV_DSLPVS(0) /*!< core voltage is 1.0V in deep-sleep mode */ 700 #define RCU_DEEPSLEEP_V_0_9 DSV_DSLPVS(1) /*!< core voltage is 0.9V in deep-sleep mode */ 701 #define RCU_DEEPSLEEP_V_0_8 DSV_DSLPVS(2) /*!< core voltage is 0.8V in deep-sleep mode */ 702 #define RCU_DEEPSLEEP_V_0_7 DSV_DSLPVS(3) /*!< core voltage is 0.7V in deep-sleep mode */ 703 704 /* function declarations */ 705 /* deinitialize the RCU */ 706 void rcu_deinit(void); 707 /* enable the peripherals clock */ 708 void rcu_periph_clock_enable(rcu_periph_enum periph); 709 /* disable the peripherals clock */ 710 void rcu_periph_clock_disable(rcu_periph_enum periph); 711 /* enable the peripherals clock when sleep mode */ 712 void rcu_periph_clock_sleep_enable(rcu_periph_sleep_enum periph); 713 /* disable the peripherals clock when sleep mode */ 714 void rcu_periph_clock_sleep_disable(rcu_periph_sleep_enum periph); 715 /* reset the peripherals */ 716 void rcu_periph_reset_enable(rcu_periph_reset_enum periph_reset); 717 /* disable reset the peripheral */ 718 void rcu_periph_reset_disable(rcu_periph_reset_enum periph_reset); 719 /* reset the BKP */ 720 void rcu_bkp_reset_enable(void); 721 /* disable the BKP reset */ 722 void rcu_bkp_reset_disable(void); 723 724 /* configure the system clock source */ 725 void rcu_system_clock_source_config(uint32_t ck_sys); 726 /* get the system clock source */ 727 uint32_t rcu_system_clock_source_get(void); 728 /* configure the AHB prescaler selection */ 729 void rcu_ahb_clock_config(uint32_t ck_ahb); 730 /* configure the APB1 prescaler selection */ 731 void rcu_apb1_clock_config(uint32_t ck_apb1); 732 /* configure the APB2 prescaler selection */ 733 void rcu_apb2_clock_config(uint32_t ck_apb2); 734 /* configure the ADC clock source and prescaler selection */ 735 void rcu_adc_clock_config(rcu_adc_clock_enum ck_adc); 736 /* configure the USBFS prescaler selection */ 737 void rcu_usbfs_clock_config(uint32_t ck_usbfs); 738 /* configure the CK_OUT clock source and divider */ 739 void rcu_ckout_config(uint32_t ckout_src, uint32_t ckout_div); 740 741 /* configure the PLL clock source preselection */ 742 void rcu_pll_preselection_config(uint32_t pll_presel); 743 /* configure the PLL clock source selection and PLL multiply factor */ 744 void rcu_pll_config(uint32_t pll_src, uint32_t pll_mul); 745 /* configure the USART clock source selection */ 746 void rcu_usart_clock_config(uint32_t ck_usart); 747 /* configure the CEC clock source selection */ 748 void rcu_cec_clock_config(uint32_t ck_cec); 749 /* configure the RTC clock source selection */ 750 void rcu_rtc_clock_config(uint32_t rtc_clock_source); 751 /* configure the CK48M clock selection */ 752 void rcu_ck48m_clock_config(uint32_t ck48m_clock_source); 753 /* configure the HXTAL divider used as input of PLL */ 754 void rcu_hxtal_prediv_config(uint32_t hxtal_prediv); 755 /* configure the LXTAL drive capability */ 756 void rcu_lxtal_drive_capability_config(uint32_t lxtal_dricap); 757 758 /* get the clock stabilization and periphral reset flags */ 759 FlagStatus rcu_flag_get(rcu_flag_enum flag); 760 /* clear the reset flag */ 761 void rcu_all_reset_flag_clear(void); 762 /* get the clock stabilization interrupt and ckm flags */ 763 FlagStatus rcu_interrupt_flag_get(rcu_int_flag_enum int_flag); 764 /* clear the interrupt flags */ 765 void rcu_interrupt_flag_clear(rcu_int_flag_clear_enum int_flag_clear); 766 /* enable the stabilization interrupt */ 767 void rcu_interrupt_enable(rcu_int_enum stab_int); 768 /* disable the stabilization interrupt */ 769 void rcu_interrupt_disable(rcu_int_enum stab_int); 770 771 /* wait until oscillator stabilization flags is SET */ 772 ErrStatus rcu_osci_stab_wait(rcu_osci_type_enum osci); 773 /* turn on the oscillator */ 774 void rcu_osci_on(rcu_osci_type_enum osci); 775 /* turn off the oscillator */ 776 void rcu_osci_off(rcu_osci_type_enum osci); 777 /* enable the oscillator bypass mode */ 778 void rcu_osci_bypass_mode_enable(rcu_osci_type_enum osci); 779 /* disable the oscillator bypass mode */ 780 void rcu_osci_bypass_mode_disable(rcu_osci_type_enum osci); 781 /* enable the HXTAL clock monitor */ 782 void rcu_hxtal_clock_monitor_enable(void); 783 /* disable the HXTAL clock monitor */ 784 void rcu_hxtal_clock_monitor_disable(void); 785 786 /* set the IRC8M adjust value */ 787 void rcu_irc8m_adjust_value_set(uint8_t irc8m_adjval); 788 /* set the IRC28M adjust value */ 789 void rcu_irc28m_adjust_value_set(uint8_t irc28m_adjval); 790 /* unlock the voltage key */ 791 void rcu_voltage_key_unlock(void); 792 /* set the deep sleep mode voltage */ 793 void rcu_deepsleep_voltage_set(uint32_t dsvol); 794 795 /* get the system clock, bus and peripheral clock frequency */ 796 uint32_t rcu_clock_freq_get(rcu_clock_freq_enum clock); 797 798 #endif /* GD32F3X0_RCU_H */ 799
