1 /*! 2 \file gd32f3x0_pmu.h 3 \brief definitions for the PMU 4 5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0 6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0 7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F3X0_PMU_H 38 #define GD32F3X0_PMU_H 39 40 #include "gd32f3x0.h" 41 42 /* PMU definitions */ 43 #define PMU PMU_BASE /*!< PMU base address */ 44 45 /* registers definitions */ 46 #define PMU_CTL REG32(PMU + 0x00000000U) /*!< PMU control register */ 47 #define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register */ 48 49 /* bits definitions */ 50 /* PMU_CTL */ 51 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 52 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 53 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 54 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 55 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 56 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 57 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 58 #define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ 59 #define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ 60 #define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ 61 #define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ 62 #define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ 63 #define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ 64 65 /* PMU_CS */ 66 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 67 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 68 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 69 #define PMU_CS_WUPEN0 BIT(8) /*!< wakeup pin enable */ 70 #define PMU_CS_WUPEN1 BIT(9) /*!< wakeup pin enable */ 71 #define PMU_CS_WUPEN4 BIT(12) /*!< wakeup pin enable */ 72 #define PMU_CS_WUPEN5 BIT(13) /*!< wakeup pin enable */ 73 #define PMU_CS_WUPEN6 BIT(14) /*!< wakeup pin enable */ 74 #define PMU_CS_LDOVSRF BIT(15) /*!< LDO voltage select ready flag */ 75 #define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ 76 #define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ 77 #define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ 78 79 /* constants definitions */ 80 /* PMU low voltage detector threshold definitions */ 81 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 82 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ 83 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ 84 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ 85 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ 86 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ 87 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ 88 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ 89 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ 90 91 /* PMU LDO output voltage select definitions */ 92 #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) 93 #define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ 94 #define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ 95 #define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ 96 97 /* PMU low-driver mode enable in deep-sleep mode */ 98 #define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 99 #define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ 100 #define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ 101 102 /* PMU high-driver mode switch */ 103 #define PMU_HIGHDR_SWITCH_NONE ((uint32_t)0x00000000U) /*!< no high-driver mode switch */ 104 #define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /*!< high-driver mode switch */ 105 106 /* PMU low-driver mode when use normal power LDO */ 107 #define PMU_NORMALDR_NORMALPWR ((uint32_t)0x00000000U) /*!< normal-driver when use normal power LDO */ 108 #define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ 109 110 /* PMU low-driver mode when use low power LDO */ 111 #define PMU_NORMALDR_LOWPWR ((uint32_t)0x00000000U) /*!< normal-driver when use low power LDO */ 112 #define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ 113 114 /* PMU ldo definitions */ 115 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO operates normally when PMU enter deepsleep mode */ 116 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 117 118 /* PMU low power mode ready flag definitions */ 119 #define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 120 #define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal-driver in deep-sleep mode */ 121 #define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ 122 123 /* PMU flag definitions */ 124 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 125 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 126 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< LVD flag status */ 127 #define PMU_FLAG_LDOVSR PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ 128 #define PMU_FLAG_HDR PMU_CS_HDRF /*!< high-driver ready flag */ 129 #define PMU_FLAG_HDSR PMU_CS_HDSRF /*!< high-driver switch ready flag */ 130 #define PMU_FLAG_LDR PMU_CS_LDRF /*!< low-driver mode ready flag */ 131 132 /* PMU WKUP pin definitions */ 133 #define PMU_WAKEUP_PIN0 PMU_CS_WUPEN0 /*!< WKUP Pin 0 (PA0) enable */ 134 #define PMU_WAKEUP_PIN1 PMU_CS_WUPEN1 /*!< WKUP Pin 1 (PC13) enable */ 135 #define PMU_WAKEUP_PIN4 PMU_CS_WUPEN4 /*!< WKUP Pin 4 (PC5) enable */ 136 #define PMU_WAKEUP_PIN5 PMU_CS_WUPEN5 /*!< WKUP Pin 5 (PB5) enable */ 137 #define PMU_WAKEUP_PIN6 PMU_CS_WUPEN6 /*!< WKUP Pin 6 (PB15) enable */ 138 139 /* PMU flag reset definitions */ 140 #define PMU_FLAG_RESET_WAKEUP PMU_CTL_WURST /*!< wakeup flag reset */ 141 #define PMU_FLAG_RESET_STANDBY PMU_CTL_STBRST /*!< standby flag reset */ 142 143 /* PMU command constants definitions */ 144 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 145 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 146 147 /* function declarations */ 148 /* function configuration */ 149 /* reset PMU registers */ 150 void pmu_deinit(void); 151 /* select low voltage detector threshold */ 152 void pmu_lvd_select(uint32_t lvdt_n); 153 /* select LDO output voltage */ 154 void pmu_ldo_output_select(uint32_t ldo_output); 155 /* disable PMU lvd */ 156 void pmu_lvd_disable(void); 157 158 /* functions of low-driver mode and high-driver mode in deep-sleep mode */ 159 /* enable low-driver mode in deep-sleep mode */ 160 void pmu_lowdriver_mode_enable(void); 161 /* disable low-driver mode in deep-sleep mode */ 162 void pmu_lowdriver_mode_disable(void); 163 /* enable high-driver mode */ 164 void pmu_highdriver_mode_enable(void); 165 /* disable high-driver mode */ 166 void pmu_highdriver_mode_disable(void); 167 /* switch high-driver mode */ 168 void pmu_highdriver_switch_select(uint32_t highdr_switch); 169 /* in deep-sleep mode, low-driver mode when use low power LDO */ 170 void pmu_lowpower_driver_config(uint32_t mode); 171 /* in deep-sleep mode, low-driver mode when use normal power LDO */ 172 void pmu_normalpower_driver_config(uint32_t mode); 173 174 /* set PMU mode */ 175 /* PMU work in sleep mode */ 176 void pmu_to_sleepmode(uint8_t sleepmodecmd); 177 /* PMU work in deepsleep mode */ 178 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); 179 /* PMU work in standby mode */ 180 void pmu_to_standbymode(uint8_t standbymodecmd); 181 /* enable PMU wakeup pin */ 182 void pmu_wakeup_pin_enable(uint32_t wakeup_pin); 183 /* disable PMU wakeup pin */ 184 void pmu_wakeup_pin_disable(uint32_t wakeup_pin); 185 186 /* backup related functions */ 187 /* enable backup domain write */ 188 void pmu_backup_write_enable(void); 189 /* disable backup domain write */ 190 void pmu_backup_write_disable(void); 191 192 /* flag functions */ 193 /* clear flag bit */ 194 void pmu_flag_clear(uint32_t flag_clear); 195 /* get flag state */ 196 FlagStatus pmu_flag_get(uint32_t flag); 197 198 #endif /* GD32F3X0_PMU_H */ 199
