1 /*!
2 \file gd32e50x_misc.c
3 \brief MISC driver
4
5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2020-08-26, V1.1.0, firmware for GD32E50x
7 \version 2021-03-23, V1.2.0, firmware for GD32E50x
8 \version 2021-12-09, V1.2.1, firmware for GD32E50x
9 */
10
11 /*
12 Copyright (c) 2021, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32e50x_misc.h"
39
40 /*!
41 \brief set the priority group
42 \param[in] nvic_prigroup: the NVIC priority group
43 \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
44 \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
45 \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
46 \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
47 \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
48 \param[out] none
49 \retval none
50 */
nvic_priority_group_set(uint32_t nvic_prigroup)51 void nvic_priority_group_set(uint32_t nvic_prigroup)
52 {
53 /* set the priority group value */
54 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
55 }
56
57 /*!
58 \brief enable NVIC request
59 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
60 \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
61 \param[in] nvic_irq_sub_priority: the subpriority needed to set
62 \param[out] none
63 \retval none
64 */
nvic_irq_enable(uint8_t nvic_irq,uint8_t nvic_irq_pre_priority,uint8_t nvic_irq_sub_priority)65 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
66 uint8_t nvic_irq_sub_priority)
67 {
68 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
69 /* use the priority group value to get the temp_pre and the temp_sub */
70 if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
71 temp_pre=0U;
72 temp_sub=0x4U;
73 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
74 temp_pre=1U;
75 temp_sub=0x3U;
76 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
77 temp_pre=2U;
78 temp_sub=0x2U;
79 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
80 temp_pre=3U;
81 temp_sub=0x1U;
82 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
83 temp_pre=4U;
84 temp_sub=0x0U;
85 }else{
86 nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
87 temp_pre=2U;
88 temp_sub=0x2U;
89 }
90 /* get the temp_priority to fill the NVIC->IP register */
91 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
92 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
93 temp_priority = temp_priority << 0x04U;
94 NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
95 /* enable the selected IRQ */
96 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
97 }
98
99 /*!
100 \brief disable NVIC request
101 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
102 \param[out] none
103 \retval none
104 */
nvic_irq_disable(uint8_t nvic_irq)105 void nvic_irq_disable(uint8_t nvic_irq)
106 {
107 /* disable the selected IRQ.*/
108 NVIC_DisableIRQ((IRQn_Type)nvic_irq);
109 }
110
111 /*!
112 \brief initiates a system reset request to reset the MCU
113 \param[in] none
114 \param[out] none
115 \retval none
116 */
nvic_system_reset(void)117 void nvic_system_reset(void)
118 {
119 NVIC_SystemReset();
120 }
121
122 /*!
123 \brief set the NVIC vector table base address
124 \param[in] nvic_vict_tab: the RAM or FLASH base address
125 \arg NVIC_VECTTAB_RAM: RAM base address
126 \are NVIC_VECTTAB_FLASH: Flash base address
127 \param[in] offset: Vector Table offset
128 \param[out] none
129 \retval none
130 */
nvic_vector_table_set(uint32_t nvic_vict_tab,uint32_t offset)131 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
132 {
133 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
134 __DSB();
135 }
136
137 /*!
138 \brief set the state of the low power mode
139 \param[in] lowpower_mode: the low power mode state
140 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
141 mode by exiting from ISR
142 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
143 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
144 by all the enable and disable interrupts
145 \param[out] none
146 \retval none
147 */
system_lowpower_set(uint8_t lowpower_mode)148 void system_lowpower_set(uint8_t lowpower_mode)
149 {
150 SCB->SCR |= (uint32_t)lowpower_mode;
151 }
152
153 /*!
154 \brief reset the state of the low power mode
155 \param[in] lowpower_mode: the low power mode state
156 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
157 mode by exiting from ISR
158 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
159 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
160 woke up by the enable interrupts
161 \param[out] none
162 \retval none
163 */
system_lowpower_reset(uint8_t lowpower_mode)164 void system_lowpower_reset(uint8_t lowpower_mode)
165 {
166 SCB->SCR &= (~(uint32_t)lowpower_mode);
167 }
168
169 /*!
170 \brief set the systick clock source
171 \param[in] systick_clksource: the systick clock source needed to choose
172 \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
173 \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
174 \param[out] none
175 \retval none
176 */
177
systick_clksource_set(uint32_t systick_clksource)178 void systick_clksource_set(uint32_t systick_clksource)
179 {
180 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
181 /* set the systick clock source from HCLK */
182 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
183 }else{
184 /* set the systick clock source from HCLK/8 */
185 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
186 }
187 }
188
