1 /*! 2 \file gd32e50x_i2c.h 3 \brief definitions for the I2C 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_I2C_H 38 #define GD32E50X_I2C_H 39 40 #include "gd32e50x.h" 41 42 /* I2Cx(x=0,1,2) definitions */ 43 #define I2C0 I2C_BASE /*!< I2C0 base address */ 44 #define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ 45 #define I2C2 (I2C_BASE + 0x00006C00U) /*!< I2C2 base address */ 46 47 /* registers definitions */ 48 /* registers of I2Cx(x=0,1) */ 49 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ 50 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ 51 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ 52 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register */ 53 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ 54 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ 55 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ 56 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ 57 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ 58 #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ 59 #define I2C_CTL2(i2cx) REG32((i2cx) + 0x00000090U) /*!< control register 2 */ 60 #define I2C_CS(i2cx) REG32((i2cx) + 0x00000094U) /*!< control and status register */ 61 #define I2C_STATC(i2cx) REG32((i2cx) + 0x00000098U) /*!< status clear register */ 62 63 /* registers of I2Cx(x=2) */ 64 #define I2C2_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ 65 #define I2C2_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ 66 #define I2C2_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ 67 #define I2C2_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1*/ 68 #define I2C2_TIMING(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C timing register */ 69 #define I2C2_TIMEOUT(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C timeout register */ 70 #define I2C2_STAT(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C status register */ 71 #define I2C2_STATC(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C status clear register */ 72 #define I2C2_PEC(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C PEC register */ 73 #define I2C2_RDATA(i2cx) REG32((i2cx) + 0x00000024U) /*!< I2C receive data register */ 74 #define I2C2_TDATA(i2cx) REG32((i2cx) + 0x00000028U) /*!< I2C transmit data register */ 75 76 /* bits definitions */ 77 /* bits definitions of I2Cx(x=0,1) */ 78 /* I2Cx_CTL0 */ 79 #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ 80 #define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ 81 #define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ 82 #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ 83 #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ 84 #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ 85 #define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ 86 #define I2C_CTL0_START BIT(8) /*!< start generation */ 87 #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ 88 #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ 89 #define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ 90 #define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ 91 #define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ 92 #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ 93 94 /* I2Cx_CTL1 */ 95 #define I2C_CTL1_I2CCLK BITS(0,6) /*!< I2CCLK[6:0] bits (peripheral clock frequency) */ 96 #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ 97 #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ 98 #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ 99 #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ 100 #define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ 101 102 /* I2Cx_SADDR0 */ 103 #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ 104 #define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ 105 #define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ 106 #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ 107 108 /* I2Cx_SADDR1 */ 109 #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ 110 #define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ 111 112 /* I2Cx_DATA */ 113 #define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ 114 115 /* I2Cx_STAT0 */ 116 #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ 117 #define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ 118 #define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ 119 #define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ 120 #define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ 121 #define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ 122 #define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ 123 #define I2C_STAT0_BERR BIT(8) /*!< bus error */ 124 #define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ 125 #define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ 126 #define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ 127 #define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ 128 #define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ 129 #define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ 130 131 /* I2Cx_STAT1 */ 132 #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ 133 #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ 134 #define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ 135 #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ 136 #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ 137 #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ 138 #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ 139 #define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ 140 141 /* I2Cx_CKCFG */ 142 #define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ 143 #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ 144 #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ 145 146 /* I2Cx_RT */ 147 #define I2C_RT_RISETIME BITS(0,6) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ 148 149 /* I2Cx_SAMCS */ 150 #define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ 151 #define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ 152 #define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ 153 #define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ 154 #define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ 155 #define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ 156 #define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ 157 #define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ 158 #define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag */ 159 #define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag */ 160 #define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag */ 161 #define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag */ 162 163 /* I2Cx_CTL2 */ 164 #define I2C_CTL2_FMPEN BIT(0) /*!< fast mode plus enable */ 165 #define I2C_CTL2_SETM BIT(1) /*!< start early termination mode */ 166 #define I2C_CTL2_TOEN BIT(4) /*!< timeout calculation disable */ 167 #define I2C_CTL2_RADD BIT(8) /*!< record received slave address to the transfer buffer register */ 168 #define I2C_CTL2_ADDM BITS(9,15) /*!< address bit compare select */ 169 170 /* I2Cx_CS */ 171 #define I2C_CS_STLO BIT(0) /*!< start lost occurred */ 172 #define I2C_CS_STPSEND BIT(1) /*!< stop condition sent */ 173 #define I2C_CS_STLOIE BIT(8) /*!< start lost interrupt enable */ 174 #define I2C_CS_STPSENDIE BIT(9) /*!< stop condition sent interrupt enable */ 175 176 /* I2Cx_STATC */ 177 #define I2C_STATC_SBSENDC BIT(0) /*!< clear SBSEND bit */ 178 #define I2C_STATC_ADDSENDC BIT(1) /*!< clear ADDSEND bit */ 179 #define I2C_STATC_BTCC BIT(2) /*!< clear BTC bit */ 180 #define I2C_STATC_ADD10SENDC BIT(3) /*!< clear ADD10SEND bit */ 181 #define I2C_STATC_STOPFC BIT(4) /*!< clear STPDET bit */ 182 #define I2C_STATC_SRCEN BIT(15) /*!< Status register clear enable */ 183 184 /* bits definitions of I2Cx(x=2) */ 185 /* I2Cx_CTL0 */ 186 #define I2C2_CTL0_I2CEN BIT(0) /*!< I2C peripheral enable */ 187 #define I2C2_CTL0_TIE BIT(1) /*!< transmit interrupt enable */ 188 #define I2C2_CTL0_RBNEIE BIT(2) /*!< receive interrupt enable */ 189 #define I2C2_CTL0_ADDMIE BIT(3) /*!< address match interrupt enable in slave mode */ 190 #define I2C2_CTL0_NACKIE BIT(4) /*!< not acknowledge received interrupt enable */ 191 #define I2C2_CTL0_STPDETIE BIT(5) /*!< stop detection interrupt enable */ 192 #define I2C2_CTL0_TCIE BIT(6) /*!< transfer complete interrupt enable */ 193 #define I2C2_CTL0_ERRIE BIT(7) /*!< error interrupt enable */ 194 #define I2C2_CTL0_DNF BITS(8,11) /*!< digital noise filter */ 195 #define I2C2_CTL0_ANOFF BIT(12) /*!< analog noise filter */ 196 #define I2C2_CTL0_DENT BIT(14) /*!< DMA enable for transmission */ 197 #define I2C2_CTL0_DENR BIT(15) /*!< DMA enable for reception */ 198 #define I2C2_CTL0_SBCTL BIT(16) /*!< slave byte control */ 199 #define I2C2_CTL0_SS BIT(17) /*!< whether to stretch SCL low when data is not ready in slave mode */ 200 #define I2C2_CTL0_WUEN BIT(18) /*!< wakeup from Deep-sleep mode enable */ 201 #define I2C2_CTL0_GCEN BIT(19) /*!< whether or not to response to a General Call (0x00) */ 202 #define I2C2_CTL0_SMBHAEN BIT(20) /*!< SMBus host address enable */ 203 #define I2C2_CTL0_SMBDAEN BIT(21) /*!< SMBus device default address enable */ 204 #define I2C2_CTL0_SMBALTEN BIT(22) /*!< SMBus alert enable */ 205 #define I2C2_CTL0_PECEN BIT(23) /*!< PEC calculation switch */ 206 207 /* I2Cx_CTL1 */ 208 #define I2C2_CTL1_SADDRESS BITS(0,9) /*!< received slave address */ 209 #define I2C2_CTL1_TRDIR BIT(10) /*!< transfer direction in master mode */ 210 #define I2C2_CTL1_ADD10EN BIT(11) /*!< 10-bit addressing mode enable in master mode */ 211 #define I2C2_CTL1_HEAD10R BIT(12) /*!< 10-bit address header executes read direction only in master receive mode */ 212 #define I2C2_CTL1_START BIT(13) /*!< generate a START condition on I2C bus */ 213 #define I2C2_CTL1_STOP BIT(14) /*!< generate a STOP condition on I2C bus */ 214 #define I2C2_CTL1_NACKEN BIT(15) /*!< generate NACK in slave mode */ 215 #define I2C2_CTL1_BYTENUM BITS(16,23) /*!< number of bytes to be transferred */ 216 #define I2C2_CTL1_RELOAD BIT(24) /*!< reload mode enable */ 217 #define I2C2_CTL1_AUTOEND BIT(25) /*!< automatic end mode in master mode */ 218 #define I2C2_CTL1_PECTRANS BIT(26) /*!< PEC transfer */ 219 220 /* I2Cx_SADDR0 */ 221 #define I2C2_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ 222 #define I2C2_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ 223 #define I2C2_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ 224 #define I2C2_SADDR0_ADDFORMAT BIT(10) /*!< address mode for the I2C slave */ 225 #define I2C2_SADDR0_ADDRESSEN BIT(15) /*!< I2C address enable */ 226 227 /* I2Cx_SADDR1 */ 228 #define I2C2_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave */ 229 #define I2C2_SADDR1_ADDMSK2 BITS(8,10) /*!< ADDRESS2[7:1] mask */ 230 #define I2C2_SADDR1_ADDRESS2EN BIT(15) /*!< second I2C address enable */ 231 232 /* I2Cx_TIMING */ 233 #define I2C2_TIMING_SCLL BITS(0,7) /*!< SCL low period */ 234 #define I2C2_TIMING_SCLH BITS(8,15) /*!< SCL high period */ 235 #define I2C2_TIMING_SDADELY BITS(16,19) /*!< data hold time */ 236 #define I2C2_TIMING_SCLDELY BITS(20,23) /*!< data setup time */ 237 #define I2C2_TIMING_PSC BITS(28,31) /*!< timing prescaler */ 238 239 /* I2Cx_TIMEOUT */ 240 #define I2C2_TIMEOUT_BUSTOA BITS(0,11) /*!< bus timeout A */ 241 #define I2C2_TIMEOUT_TOIDLE BIT(12) /*!< idle clock timeout detection */ 242 #define I2C2_TIMEOUT_TOEN BIT(15) /*!< clock timeout detection enable */ 243 #define I2C2_TIMEOUT_BUSTOB BITS(16,27) /*!< bus timeout B */ 244 #define I2C2_TIMEOUT_EXTOEN BIT(31) /*!< extended clock timeout detection enable */ 245 246 /* I2Cx_STAT */ 247 #define I2C2_STAT_TBE BIT(0) /*!< I2C_TDATA is empty during transmitting */ 248 #define I2C2_STAT_TI BIT(1) /*!< transmit interrupt */ 249 #define I2C2_STAT_RBNE BIT(2) /*!< I2C_RDATA is not empty during receiving */ 250 #define I2C2_STAT_ADDSEND BIT(3) /*!< address received matches in slave mode */ 251 #define I2C2_STAT_NACK BIT(4) /*!< not acknowledge flag */ 252 #define I2C2_STAT_STPDET BIT(5) /*!< STOP condition detected in slave mode */ 253 #define I2C2_STAT_TC BIT(6) /*!< transfer complete in master mode */ 254 #define I2C2_STAT_TCR BIT(7) /*!< transfer complete reload */ 255 #define I2C2_STAT_BERR BIT(8) /*!< bus error */ 256 #define I2C2_STAT_LOSTARB BIT(9) /*!< arbitration lost */ 257 #define I2C2_STAT_OUERR BIT(10) /*!< overrun/underrun error in slave mode */ 258 #define I2C2_STAT_PECERR BIT(11) /*!< PEC error */ 259 #define I2C2_STAT_TIMEOUT BIT(12) /*!< timeout flag */ 260 #define I2C2_STAT_SMBALT BIT(13) /*!< SMBus Alert */ 261 #define I2C2_STAT_I2CBSY BIT(15) /*!< busy flag */ 262 #define I2C2_STAT_TR BIT(16) /*!< whether the I2C is a transmitter or a receiver in slave mode */ 263 #define I2C2_STAT_READDR BITS(17,23) /*!< received match address in slave mode */ 264 265 /* I2Cx_STATC */ 266 #define I2C2_STATC_ADDSENDC BIT(3) /*!< ADDSEND flag clear */ 267 #define I2C2_STATC_NACKC BIT(4) /*!< not acknowledge flag clear */ 268 #define I2C2_STATC_STPDETC BIT(5) /*!< STPDET flag clear */ 269 #define I2C2_STATC_BERRC BIT(8) /*!< bus error flag clear */ 270 #define I2C2_STATC_LOSTARBC BIT(9) /*!< arbitration Lost flag clear */ 271 #define I2C2_STATC_OUERRC BIT(10) /*!< overrun/underrun flag clear */ 272 #define I2C2_STATC_PECERRC BIT(11) /*!< PEC error flag clear */ 273 #define I2C2_STATC_TIMEOUTC BIT(12) /*!< TIMEOUT flag clear */ 274 #define I2C2_STATC_SMBALTC BIT(13) /*!< SMBus Alert flag clear */ 275 276 /* I2Cx_PEC */ 277 #define I2C2_PEC_PECV BITS(0,7) /*!< Packet Error Checking Value that calculated by hardware when PEC is enabled */ 278 279 /* I2Cx_RDATA */ 280 #define I2C2_RDATA_RDATA BITS(0,7) /*!< receive data value */ 281 282 /* I2Cx_TDATA */ 283 #define I2C2_TDATA_TDATA BITS(0,7) /*!< transmit data value */ 284 285 /* constants definitions */ 286 /* define the I2C bit position and its register index offset */ 287 #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 288 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 289 #define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 290 #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 291 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 292 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) 293 #define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 294 295 /* register offset */ 296 /* register offset of I2Cx(x=0,1) */ 297 #define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ 298 #define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ 299 #define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ 300 #define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ 301 #define I2C_CTL2_REG_OFFSET ((uint32_t)0x00000090U) /*!< CTL2 register offset */ 302 #define I2C_CS_REG_OFFSET ((uint32_t)0x00000094U) /*!< control and status register offset */ 303 #define I2C_STATC_REG_OFFSET ((uint32_t)0x00000098U) /*!< status clear register offset */ 304 /* register offset of I2Cx(x=2) */ 305 #define I2C2_CTL0_REG_OFFSET ((uint32_t)0x00000000U) /*!< CTL0 register offset */ 306 #define I2C2_STAT_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT register offset */ 307 308 /* I2C flag definitions */ 309 /* I2C flag definitions of I2Cx(x=0,1) */ 310 typedef enum 311 { 312 /* flags in STAT0 register */ 313 I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ 314 I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ 315 I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ 316 I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ 317 I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ 318 I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ 319 I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ 320 I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ 321 I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ 322 I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ 323 I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ 324 I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ 325 I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ 326 I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ 327 /* flags in STAT1 register */ 328 I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ 329 I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ 330 I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ 331 I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ 332 I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ 333 I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ 334 I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ 335 /* flags in SAMCS register */ 336 I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ 337 I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ 338 I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ 339 I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U), /*!< rxframe rise flag */ 340 /* flags in control and status register */ 341 I2C_FLAG_STLO = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 0U), /*!< start lost flag */ 342 I2C_FLAG_STPSEND = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 1U) /*!< stop condition sent flag */ 343 }i2c_flag_enum; 344 345 /* I2C flag definitions of I2Cx(x=2) */ 346 #define I2C2_FLAG_TBE I2C2_STAT_TBE /*!< I2C_TDATA is empty during transmitting */ 347 #define I2C2_FLAG_TI I2C2_STAT_TI /*!< transmit interrupt */ 348 #define I2C2_FLAG_RBNE I2C2_STAT_RBNE /*!< I2C_RDATA is not empty during receiving */ 349 #define I2C2_FLAG_ADDSEND I2C2_STAT_ADDSEND /*!< address received matches in slave mode */ 350 #define I2C2_FLAG_NACK I2C2_STAT_NACK /*!< not acknowledge flag */ 351 #define I2C2_FLAG_STPDET I2C2_STAT_STPDET /*!< STOP condition detected in slave mode */ 352 #define I2C2_FLAG_TC I2C2_STAT_TC /*!< transfer complete in master mode */ 353 #define I2C2_FLAG_TCR I2C2_STAT_TCR /*!< transfer complete reload */ 354 #define I2C2_FLAG_BERR I2C2_STAT_BERR /*!< bus error */ 355 #define I2C2_FLAG_LOSTARB I2C2_STAT_LOSTARB /*!< arbitration lost */ 356 #define I2C2_FLAG_OUERR I2C2_STAT_OUERR /*!< overrun/underrun error in slave mode */ 357 #define I2C2_FLAG_PECERR I2C2_STAT_PECERR /*!< PEC error */ 358 #define I2C2_FLAG_TIMEOUT I2C2_STAT_TIMEOUT /*!< timeout flag */ 359 #define I2C2_FLAG_SMBALT I2C2_STAT_SMBALT /*!< SMBus Alert */ 360 #define I2C2_FLAG_I2CBSY I2C2_STAT_I2CBSY /*!< busy flag */ 361 #define I2C2_FLAG_TR I2C2_STAT_TR /*!< whether the I2C is a transmitter or a receiver in slave mode */ 362 363 /* I2C interrupt flags */ 364 /* I2C interrupt flags of I2Cx(x=0,1) */ 365 typedef enum 366 { 367 /* interrupt flags in CTL1 register */ 368 I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ 369 I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ 370 I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ 371 I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ 372 I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ 373 I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ 374 I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ 375 I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ 376 I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ 377 I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ 378 I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ 379 I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ 380 I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ 381 I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ 382 /* interrupt flags in SAMCS register */ 383 I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ 384 I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ 385 I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ 386 I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U), /*!< rxframe rise interrupt flag */ 387 /* interrupt flags in control and status register */ 388 I2C_INT_FLAG_STLO = I2C_REGIDX_BIT2(I2C_CS_REG_OFFSET, 8U, I2C_CS_REG_OFFSET, 0U), /*!< start lost interrupt flag */ 389 I2C_INT_FLAG_STPSEND = I2C_REGIDX_BIT2(I2C_CS_REG_OFFSET, 9U, I2C_CS_REG_OFFSET, 1U) /*!< stop condition sent interrupt flag */ 390 }i2c_interrupt_flag_enum; 391 392 /* I2C interrupt flags of I2Cx(x=2) */ 393 typedef enum 394 { 395 I2C2_INT_FLAG_TI = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 1U, I2C2_STAT_REG_OFFSET, 1U), /*!< transmit interrupt flag */ 396 I2C2_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 2U, I2C2_STAT_REG_OFFSET, 2U), /*!< I2C_RDATA is not empty during receiving interrupt flag */ 397 I2C2_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 3U, I2C2_STAT_REG_OFFSET, 3U), /*!< address received matches in slave mode interrupt flag */ 398 I2C2_INT_FLAG_NACK = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 4U, I2C2_STAT_REG_OFFSET, 4U), /*!< not acknowledge interrupt flag */ 399 I2C2_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 5U, I2C2_STAT_REG_OFFSET, 5U), /*!< stop condition detected in slave mode interrupt flag */ 400 I2C2_INT_FLAG_TC = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 6U, I2C2_STAT_REG_OFFSET, 6U), /*!< transfer complete in master mode interrupt flag */ 401 I2C2_INT_FLAG_TCR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 6U, I2C2_STAT_REG_OFFSET, 7U), /*!< transfer complete reload interrupt flag */ 402 I2C2_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 8U), /*!< bus error interrupt flag */ 403 I2C2_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 9U), /*!< arbitration lost interrupt flag */ 404 I2C2_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 10U), /*!< overrun/underrun error in slave mode interrupt flag */ 405 I2C2_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 11U), /*!< PEC error interrupt flag */ 406 I2C2_INT_FLAG_TIMEOUT = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 12U), /*!< timeout interrupt flag */ 407 I2C2_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C2_CTL0_REG_OFFSET, 7U, I2C2_STAT_REG_OFFSET, 13U), /*!< SMBus Alert interrupt flag */ 408 }i2c2_interrupt_flag_enum; 409 410 /* I2C interrupt enable or disable */ 411 /* I2C interrupt enable or disable of I2Cx(x=0,1) */ 412 typedef enum 413 { 414 /* interrupt in CTL1 register */ 415 I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ 416 I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ 417 I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ 418 /* interrupt in SAMCS register */ 419 I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt enable */ 420 I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt enable */ 421 I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt enable */ 422 I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U), /*!< rxframe rise interrupt enable */ 423 /* interrupt in control and status register */ 424 I2C_INT_STLO = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 8U), /*!< start lost interrupt enable */ 425 I2C_INT_STPSEND = I2C_REGIDX_BIT(I2C_CS_REG_OFFSET, 9U) /*!< stop condition sent interrupt enable */ 426 }i2c_interrupt_enum; 427 428 /* I2C interrupt enable or disable of I2Cx(x=2) */ 429 #define I2C2_INT_ERR I2C2_CTL0_ERRIE /*!< error interrupt enable */ 430 #define I2C2_INT_TC I2C2_CTL0_TCIE /*!< transfer complete interrupt enable */ 431 #define I2C2_INT_STPDET I2C2_CTL0_STPDETIE /*!< stop detection interrupt enable */ 432 #define I2C2_INT_NACK I2C2_CTL0_NACKIE /*!< not acknowledge received interrupt enable */ 433 #define I2C2_INT_ADDM I2C2_CTL0_ADDMIE /*!< address match interrupt enable */ 434 #define I2C2_INT_RBNE I2C2_CTL0_RBNEIE /*!< receive interrupt enable */ 435 #define I2C2_INT_TI I2C2_CTL0_TIE /*!< transmit interrupt enable */ 436 437 /* I2C status register bit clear */ 438 #define CLEAR_STPDET I2C_STATC_STOPFC /*!< clear STPDET bit in I2C_STAT0 */ 439 #define CLEAR_ADD10SEND I2C_STATC_ADD10SENDC /*!< clear ADD10SEND bit in I2C_STAT0 */ 440 #define CLEAR_BTC I2C_STATC_BTCC /*!< clear BTC bit in I2C_STAT0 */ 441 #define CLEAR_ADDSEND I2C_STATC_ADDSENDC /*!< clear ADDSEND bit in I2C_STAT0 */ 442 #define CLEAR_SBSEND I2C_STATC_SBSENDC /*!< clear SBSEND bit in I2C_STAT0 */ 443 444 /* I2C start early termination mode */ 445 #define STANDARD_I2C_PROTOCOL_MODE ((uint32_t)0x00000000U) /*!< do as the standard i2c protocol */ 446 #define ARBITRATION_LOST_MODE I2C_CTL2_SETM /*!< do the same thing as arbitration lost */ 447 448 /* SMBus/I2C mode switch and SMBus type selection */ 449 #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ 450 #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ 451 452 /* SMBus/I2C mode switch and SMBus type selection */ 453 #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ 454 #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ 455 456 /* I2C transfer direction */ 457 #define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ 458 #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ 459 460 /* whether or not to send an ACK */ 461 #define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ 462 #define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ 463 464 /* I2C POAP position*/ 465 #define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ 466 #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ 467 468 /* software reset I2C */ 469 #define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ 470 #define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ 471 472 /* I2C DMA mode configure */ 473 /* DMA mode switch */ 474 #define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ 475 #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ 476 477 /* flag indicating DMA last transfer */ 478 #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ 479 #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ 480 481 /* I2C PEC configure */ 482 /* PEC enable */ 483 #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ 484 #define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ 485 486 /* PEC transfer */ 487 #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ 488 #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ 489 490 /* I2C SMBus configure */ 491 /* issue or not alert through SMBA pin */ 492 #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ 493 #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ 494 495 /* ARP protocol in SMBus switch */ 496 #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ 497 #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ 498 499 /* fast mode plus enable */ 500 #define I2C_FAST_MODE_PLUS_ENABLE I2C_CTL2_FMPEN /*!< fast mode plus enable */ 501 #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ 502 503 /* I2C duty cycle in fast mode or fast mode plus */ 504 #define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 2 */ 505 #define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< in I2C fast mode or fast mode plus Tlow/Thigh = 16/9 */ 506 507 /* address mode for the I2C slave */ 508 #define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ 509 #define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ 510 511 /* I2C DMA constants definitions */ 512 #define I2C2_DMA_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C transmit data use DMA */ 513 #define I2C2_DMA_RECEIVE ((uint32_t)0x00000001U) /*!< I2C receive data use DMA */ 514 515 /* I2C transfer direction in master mode */ 516 #define I2C2_MASTER_TRANSMIT ((uint32_t)0x00000000U) /*!< I2C master transmit */ 517 #define I2C2_MASTER_RECEIVE I2C2_CTL1_TRDIR /*!< I2C master receive */ 518 519 /* address mode for the I2C slave */ 520 #define I2C2_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ 521 #define I2C2_ADDFORMAT_10BITS I2C2_SADDR0_ADDFORMAT /*!< address:10 bits */ 522 523 /* defines which bits of register ADDRESS[7:1] are compared with an incoming address byte */ 524 #define ADDRESS_BIT1_COMPARE ((uint32_t)0x00000200U) /*!< address bit1 needs compare */ 525 #define ADDRESS_BIT2_COMPARE ((uint32_t)0x00000400U) /*!< address bit2 needs compare */ 526 #define ADDRESS_BIT3_COMPARE ((uint32_t)0x00000800U) /*!< address bit3 needs compare */ 527 #define ADDRESS_BIT4_COMPARE ((uint32_t)0x00001000U) /*!< address bit4 needs compare */ 528 #define ADDRESS_BIT5_COMPARE ((uint32_t)0x00002000U) /*!< address bit5 needs compare */ 529 #define ADDRESS_BIT6_COMPARE ((uint32_t)0x00004000U) /*!< address bit6 needs compare */ 530 #define ADDRESS_BIT7_COMPARE ((uint32_t)0x00008000U) /*!< address bit7 needs compare */ 531 532 /* the length of filter spikes */ 533 #define FILTER_DISABLE ((uint32_t)0x00000000U) /*!< digital filter is disabled */ 534 #define FILTER_LENGTH_1 ((uint32_t)0x00000001U) /*!< digital filter is enabled and filter spikes with a length of up to 1 tI2CCLK */ 535 #define FILTER_LENGTH_2 ((uint32_t)0x00000002U) /*!< digital filter is enabled and filter spikes with a length of up to 2 tI2CCLK */ 536 #define FILTER_LENGTH_3 ((uint32_t)0x00000003U) /*!< digital filter is enabled and filter spikes with a length of up to 3 tI2CCLK */ 537 #define FILTER_LENGTH_4 ((uint32_t)0x00000004U) /*!< digital filter is enabled and filter spikes with a length of up to 4 tI2CCLK */ 538 #define FILTER_LENGTH_5 ((uint32_t)0x00000005U) /*!< digital filter is enabled and filter spikes with a length of up to 5 tI2CCLK */ 539 #define FILTER_LENGTH_6 ((uint32_t)0x00000006U) /*!< digital filter is enabled and filter spikes with a length of up to 6 tI2CCLK */ 540 #define FILTER_LENGTH_7 ((uint32_t)0x00000007U) /*!< digital filter is enabled and filter spikes with a length of up to 7 tI2CCLK */ 541 #define FILTER_LENGTH_8 ((uint32_t)0x00000008U) /*!< digital filter is enabled and filter spikes with a length of up to 8 tI2CCLK */ 542 #define FILTER_LENGTH_9 ((uint32_t)0x00000009U) /*!< digital filter is enabled and filter spikes with a length of up to 9 tI2CCLK */ 543 #define FILTER_LENGTH_10 ((uint32_t)0x0000000AU) /*!< digital filter is enabled and filter spikes with a length of up to 10 tI2CCLK */ 544 #define FILTER_LENGTH_11 ((uint32_t)0x0000000BU) /*!< digital filter is enabled and filter spikes with a length of up to 11 tI2CCLK */ 545 #define FILTER_LENGTH_12 ((uint32_t)0x0000000CU) /*!< digital filter is enabled and filter spikes with a length of up to 12 tI2CCLK */ 546 #define FILTER_LENGTH_13 ((uint32_t)0x0000000DU) /*!< digital filter is enabled and filter spikes with a length of up to 13 tI2CCLK */ 547 #define FILTER_LENGTH_14 ((uint32_t)0x0000000EU) /*!< digital filter is enabled and filter spikes with a length of up to 14 tI2CCLK */ 548 #define FILTER_LENGTH_15 ((uint32_t)0x0000000FU) /*!< digital filter is enabled and filter spikes with a length of up to 15 tI2CCLK */ 549 550 /* defines which bits of ADDRESS2[7:1] are compared with an incoming address byte, and which bits are masked (don��t care) */ 551 #define ADDRESS2_NO_MASK ((uint32_t)0x00000000U) /*!< no mask, all the bits must be compared */ 552 #define ADDRESS2_MASK_BIT1 ((uint32_t)0x00000001U) /*!< ADDRESS2[1] is masked, only ADDRESS2[7:2] are compared */ 553 #define ADDRESS2_MASK_BIT1_2 ((uint32_t)0x00000002U) /*!< ADDRESS2[2:1] is masked, only ADDRESS2[7:3] are compared */ 554 #define ADDRESS2_MASK_BIT1_3 ((uint32_t)0x00000003U) /*!< ADDRESS2[3:1] is masked, only ADDRESS2[7:4] are compared */ 555 #define ADDRESS2_MASK_BIT1_4 ((uint32_t)0x00000004U) /*!< ADDRESS2[4:1] is masked, only ADDRESS2[7:5] are compared */ 556 #define ADDRESS2_MASK_BIT1_5 ((uint32_t)0x00000005U) /*!< ADDRESS2[5:1] is masked, only ADDRESS2[7:6] are compared */ 557 #define ADDRESS2_MASK_BIT1_6 ((uint32_t)0x00000006U) /*!< ADDRESS2[6:1] is masked, only ADDRESS2[7] are compared */ 558 #define ADDRESS2_MASK_ALL ((uint32_t)0x00000007U) /*!< all the ADDRESS2[7:1] bits are masked */ 559 560 /* idle clock timeout detection */ 561 #define BUSTOA_DETECT_SCL_LOW ((uint32_t)0x00000000U) /*!< BUSTOA is used to detect SCL low timeout */ 562 #define BUSTOA_DETECT_IDLE I2C2_TIMEOUT_TOIDLE /*!< BUSTOA is used to detect both SCL and SDA high timeout when the bus is idle */ 563 564 /* I2C clock frequency, MHz */ 565 #define I2CCLK_MAX ((uint32_t)0x0000007FU) /*!< i2cclk maximum value */ 566 #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value */ 567 #define I2CCLK_FM_MIN ((uint32_t)0x00000008U) /*!< i2cclk minimum value for fast mode */ 568 #define I2CCLK_FM_PLUS_MIN ((uint32_t)0x00000018U) /*!< i2cclk minimum value for fast mode plus */ 569 570 /* function declarations */ 571 /* functions of I2C0~2 */ 572 /* reset I2C */ 573 void i2c_deinit(uint32_t i2c_periph); 574 /* enable I2C */ 575 void i2c_enable(uint32_t i2c_periph); 576 /* disable I2C */ 577 void i2c_disable(uint32_t i2c_periph); 578 /* generate a START condition on I2C bus */ 579 void i2c_start_on_bus(uint32_t i2c_periph); 580 /* generate a STOP condition on I2C bus */ 581 void i2c_stop_on_bus(uint32_t i2c_periph); 582 /* enable the response to a general call */ 583 void i2c_slave_response_to_gcall_enable(uint32_t i2c_periph); 584 /* disable the response to a general call */ 585 void i2c_slave_response_to_gcall_disable(uint32_t i2c_periph); 586 /* enable to stretch SCL low when data is not ready in slave mode */ 587 void i2c_stretch_scl_low_enable(uint32_t i2c_periph); 588 /* disable to stretch SCL low when data is not ready in slave mode */ 589 void i2c_stretch_scl_low_disable(uint32_t i2c_periph); 590 /* I2C transmit data function */ 591 void i2c_data_transmit(uint32_t i2c_periph, uint32_t data); 592 /* I2C receive data function */ 593 uint32_t i2c_data_receive(uint32_t i2c_periph); 594 /* I2C transfers PEC value */ 595 void i2c_pec_transfer(uint32_t i2c_periph); 596 /* enable I2C PEC calculation */ 597 void i2c_pec_enable(uint32_t i2c_periph); 598 /* disable I2C PEC calculation */ 599 void i2c_pec_disable(uint32_t i2c_periph); 600 /* get packet error checking value */ 601 uint32_t i2c_pec_value_get(uint32_t i2c_periph); 602 603 /* functions of I2C0, I2C1 */ 604 /* configure I2C clock */ 605 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); 606 /* configure I2C address */ 607 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); 608 /* SMBus type selection */ 609 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); 610 /* whether or not to send an ACK */ 611 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); 612 /* configure I2C POAP position */ 613 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); 614 /* master sends slave address */ 615 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); 616 /* enable dual-address mode */ 617 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); 618 /* disable dual-address mode */ 619 void i2c_dualaddr_disable(uint32_t i2c_periph); 620 621 /* enable I2C DMA mode */ 622 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); 623 /* configure whether next DMA EOT is DMA last transfer or not */ 624 void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); 625 /* software reset I2C */ 626 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); 627 /* I2C issue alert through SMBA pin */ 628 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); 629 /* I2C ARP protocol in SMBus switch */ 630 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); 631 /* enable SAM_V interface */ 632 void i2c_sam_enable(uint32_t i2c_periph); 633 /* disable SAM_V interface */ 634 void i2c_sam_disable(uint32_t i2c_periph); 635 /* enable SAM_V interface timeout detect */ 636 void i2c_sam_timeout_enable(uint32_t i2c_periph); 637 /* disable SAM_V interface timeout detect */ 638 void i2c_sam_timeout_disable(uint32_t i2c_periph); 639 640 /* configure I2C start early termination mode */ 641 void i2c_start_early_termination_mode_config(uint32_t i2c_periph, uint32_t mode); 642 /* enable i2c timeout calculation */ 643 void i2c_timeout_calculation_enable(uint32_t i2c_periph); 644 /* disable i2c timeout calculation */ 645 void i2c_timeout_calculation_disable(uint32_t i2c_periph); 646 /* enable i2c record the received slave address to the transfer buffer register */ 647 void i2c_record_received_slave_address_enable(uint32_t i2c_periph); 648 /* disable i2c record the received slave address to the transfer buffer register */ 649 void i2c_record_received_slave_address_disable(uint32_t i2c_periph); 650 /* define which bits of ADDRESS[7:1] need to compare with the incoming address byte */ 651 void i2c_address_bit_compare_config(uint32_t i2c_periph, uint16_t compare_bits); 652 /* enable i2c status register clear */ 653 void i2c_status_clear_enable(uint32_t i2c_periph); 654 /* disable i2c status register clear */ 655 void i2c_status_clear_disable(uint32_t i2c_periph); 656 /* clear I2C status in I2C_STAT0 register */ 657 void i2c_status_bit_clear(uint32_t i2c_periph, uint32_t clear_bit); 658 659 /* check I2C flag is set or not */ 660 FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); 661 /* clear I2C flag */ 662 void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); 663 /* enable I2C interrupt */ 664 void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 665 /* disable I2C interrupt */ 666 void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 667 /* check I2C interrupt flag */ 668 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 669 /* clear I2C interrupt flag */ 670 void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 671 672 /* functions of I2C2 */ 673 /* configure the timing parameters */ 674 void i2c_timing_config(uint32_t i2c_periph, uint32_t psc, uint32_t scl_dely, uint32_t sda_dely); 675 /* configure digital noise filter */ 676 void i2c_digital_noise_filter_config(uint32_t i2c_periph, uint32_t filter_length); 677 /* enable analog noise filter */ 678 void i2c_analog_noise_filter_enable(uint32_t i2c_periph); 679 /* disable analog noise filter */ 680 void i2c_analog_noise_filter_disable(uint32_t i2c_periph); 681 /* enable wakeup from Deep-sleep mode */ 682 void i2c_wakeup_from_deepsleep_enable(uint32_t i2c_periph); 683 /* disable wakeup from Deep-sleep mode */ 684 void i2c_wakeup_from_deepsleep_disable(uint32_t i2c_periph); 685 686 /* configure the SCL high and low period of clock in master mode */ 687 void i2c_master_clock_config(uint32_t i2c_periph, uint32_t sclh, uint32_t scll); 688 /* configure i2c slave address and transfer direction in master mode */ 689 void i2c2_master_addressing(uint32_t i2c_periph, uint32_t address, uint32_t trans_direction); 690 /* 10-bit address header executes read direction only in master receive mode */ 691 void i2c_address10_header_enable(uint32_t i2c_periph); 692 /* 10-bit address header executes complete sequence in master receive mode */ 693 void i2c_address10_header_disable(uint32_t i2c_periph); 694 /* enable 10-bit addressing mode in master mode */ 695 void i2c_address10_enable(uint32_t i2c_periph); 696 /* disable 10-bit addressing mode in master mode */ 697 void i2c_address10_disable(uint32_t i2c_periph); 698 /* enable I2C automatic end mode in master mode */ 699 void i2c_automatic_end_enable(uint32_t i2c_periph); 700 /* disable I2C automatic end mode in master mode */ 701 void i2c_automatic_end_disable(uint32_t i2c_periph); 702 703 /* configure i2c slave address */ 704 void i2c_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_format); 705 /* disable i2c address in slave mode */ 706 void i2c_address_disable(uint32_t i2c_periph); 707 /* configure i2c second slave address */ 708 void i2c_second_address_config(uint32_t i2c_periph, uint32_t address, uint32_t addr_mask); 709 /* disable i2c second address in slave mode */ 710 void i2c_second_address_disable(uint32_t i2c_periph); 711 /* get received match address in slave mode */ 712 uint32_t i2c_recevied_address_get(uint32_t i2c_periph); 713 /* enable slave byte control */ 714 void i2c_slave_byte_control_enable(uint32_t i2c_periph); 715 /* disable slave byte control */ 716 void i2c_slave_byte_control_disable(uint32_t i2c_periph); 717 /* generate a NACK in slave mode */ 718 void i2c_nack_enable(uint32_t i2c_periph); 719 /* generate an ACK in slave mode */ 720 void i2c_nack_disable(uint32_t i2c_periph); 721 722 /* enable I2C reload mode */ 723 void i2c_reload_enable(uint32_t i2c_periph); 724 /* disable I2C reload mode */ 725 void i2c_reload_disable(uint32_t i2c_periph); 726 /* configure number of bytes to be transferred */ 727 void i2c_transfer_byte_number_config(uint32_t i2c_periph, uint32_t byte_number); 728 /* enable I2C DMA for transmission or reception */ 729 void i2c2_dma_enable(uint32_t i2c_periph, uint8_t dma); 730 /* disable I2C DMA for transmission or reception */ 731 void i2c2_dma_disable(uint32_t i2c_periph, uint8_t dma); 732 733 /* enable SMBus Alert */ 734 void i2c_smbus_alert_enable(uint32_t i2c_periph); 735 /* disable SMBus Alert */ 736 void i2c_smbus_alert_disable(uint32_t i2c_periph); 737 /* enable SMBus device default address */ 738 void i2c_smbus_default_addr_enable(uint32_t i2c_periph); 739 /* disable SMBus device default address */ 740 void i2c_smbus_default_addr_disable(uint32_t i2c_periph); 741 /* enable SMBus Host address */ 742 void i2c_smbus_host_addr_enable(uint32_t i2c_periph); 743 /* disable SMBus Host address */ 744 void i2c_smbus_host_addr_disable(uint32_t i2c_periph); 745 /* enable extended clock timeout detection */ 746 void i2c_extented_clock_timeout_enable(uint32_t i2c_periph); 747 /* disable extended clock timeout detection */ 748 void i2c_extented_clock_timeout_disable(uint32_t i2c_periph); 749 /* enable clock timeout detection */ 750 void i2c_clock_timeout_enable(uint32_t i2c_periph); 751 /* disable clock timeout detection */ 752 void i2c_clock_timeout_disable(uint32_t i2c_periph); 753 /* configure bus timeout B */ 754 void i2c_bus_timeout_b_config(uint32_t i2c_periph, uint32_t timeout); 755 /* configure bus timeout A */ 756 void i2c_bus_timeout_a_config(uint32_t i2c_periph, uint32_t timeout); 757 /* configure idle clock timeout detection */ 758 void i2c_idle_clock_timeout_config(uint32_t i2c_periph, uint32_t timeout); 759 760 /* get I2C flag status */ 761 FlagStatus i2c2_flag_get(uint32_t i2c_periph, uint32_t flag); 762 /* clear I2C flag status */ 763 void i2c2_flag_clear(uint32_t i2c_periph, uint32_t flag); 764 /* enable I2C interrupt */ 765 void i2c2_interrupt_enable(uint32_t i2c_periph, uint32_t interrupt); 766 /* disable I2C interrupt */ 767 void i2c2_interrupt_disable(uint32_t i2c_periph, uint32_t interrupt); 768 /* get I2C interrupt flag status */ 769 FlagStatus i2c2_interrupt_flag_get(uint32_t i2c_periph, i2c2_interrupt_flag_enum int_flag); 770 /* clear I2C interrupt flag status */ 771 void i2c2_interrupt_flag_clear(uint32_t i2c_periph, i2c2_interrupt_flag_enum int_flag); 772 773 #endif /* GD32E50X_I2C_H */ 774
