1 /*!
2 \file gd32e50x_dac.c
3 \brief DAC driver
4
5 \version 2020-03-10, V1.0.0, firmware for GD32E50x
6 \version 2020-08-26, V1.1.0, firmware for GD32E50x
7 \version 2021-03-23, V1.2.0, firmware for GD32E50x
8 */
9
10 /*
11 Copyright (c) 2021, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32e50x_dac.h"
38
39 /* DAC register bit offset */
40 #define OUT1_REG_OFFSET ((uint32_t)0x00000010U)
41 #define DH_12BIT_OFFSET ((uint32_t)0x00000010U)
42 #define DH_8BIT_OFFSET ((uint32_t)0x00000008U)
43
44 /*!
45 \brief deinitialize DAC
46 \param[in] none
47 \param[out] none
48 \retval none
49 */
dac_deinit(void)50 void dac_deinit(void)
51 {
52 rcu_periph_reset_enable(RCU_DACRST);
53 rcu_periph_reset_disable(RCU_DACRST);
54 }
55
56 /*!
57 \brief enable DAC
58 \param[in] dac_out: DAC_OUT_x(x=0,1)
59 \param[out] none
60 \retval none
61 */
dac_enable(uint8_t dac_out)62 void dac_enable(uint8_t dac_out)
63 {
64 if(DAC_OUT_0 == dac_out){
65 DAC_CTL0 |= DAC_CTL0_DEN0;
66 }else{
67 DAC_CTL0 |= DAC_CTL0_DEN1;
68 }
69 }
70
71 /*!
72 \brief disable DAC
73 \param[in] dac_out: DAC_OUT_x(x=0,1)
74 \param[out] none
75 \retval none
76 */
dac_disable(uint8_t dac_out)77 void dac_disable(uint8_t dac_out)
78 {
79 if(DAC_OUT_0 == dac_out){
80 DAC_CTL0 &= ~DAC_CTL0_DEN0;
81 }else{
82 DAC_CTL0 &= ~DAC_CTL0_DEN1;
83 }
84 }
85
86 /*!
87 \brief enable DAC DMA function
88 \param[in] dac_out: DAC_OUT_x(x=0,1)
89 \param[out] none
90 \retval none
91 */
dac_dma_enable(uint8_t dac_out)92 void dac_dma_enable(uint8_t dac_out)
93 {
94 if(DAC_OUT_0 == dac_out){
95 DAC_CTL0 |= DAC_CTL0_DDMAEN0;
96 }else{
97 DAC_CTL0 |= DAC_CTL0_DDMAEN1;
98 }
99 }
100
101 /*!
102 \brief disable DAC DMA function
103 \param[in] dac_out: DAC_OUT_x(x=0,1)
104 \param[out] none
105 \retval none
106 */
dac_dma_disable(uint8_t dac_out)107 void dac_dma_disable(uint8_t dac_out)
108 {
109 if(DAC_OUT_0 == dac_out){
110 DAC_CTL0 &= ~DAC_CTL0_DDMAEN0;
111 }else{
112 DAC_CTL0 &= ~DAC_CTL0_DDMAEN1;
113 }
114 }
115
116 /*!
117 \brief enable DAC output buffer
118 \param[in] dac_out: DAC_OUT_x(x=0,1)
119 \param[out] none
120 \retval none
121 */
dac_output_buffer_enable(uint8_t dac_out)122 void dac_output_buffer_enable(uint8_t dac_out)
123 {
124 if(DAC_OUT_0 == dac_out){
125 DAC_CTL0 &= ~DAC_CTL0_DBOFF0;
126 }else{
127 DAC_CTL0 &= ~DAC_CTL0_DBOFF1;
128 }
129 }
130
131 /*!
132 \brief disable DAC output buffer
133 \param[in] dac_out: DAC_OUT_x(x=0,1)
134 \param[out] none
135 \retval none
136 */
dac_output_buffer_disable(uint8_t dac_out)137 void dac_output_buffer_disable(uint8_t dac_out)
138 {
139 if(DAC_OUT_0 == dac_out){
140 DAC_CTL0 |= DAC_CTL0_DBOFF0;
141 }else{
142 DAC_CTL0 |= DAC_CTL0_DBOFF1;
143 }
144 }
145
146 /*!
147 \brief get DAC output value
148 \param[in] dac_out: DAC_OUT_x(x=0,1)
149 \param[out] none
150 \retval DAC output data: 0~4095
151 */
dac_output_value_get(uint8_t dac_out)152 uint16_t dac_output_value_get(uint8_t dac_out)
153 {
154 uint16_t data = 0U;
155 if(DAC_OUT_0 == dac_out){
156 /* store the DAC_OUT0 output value */
157 data = (uint16_t)OUT0_DO;
158 }else{
159 /* store the DAC_OUT1 output value */
160 data = (uint16_t)OUT1_DO;
161 }
162 return data;
163 }
164
165 /*!
166 \brief set DAC data holding register value
167 \param[in] dac_out: DAC_OUT_x(x=0,1)
168 \param[in] dac_align: DAC data alignment mode
169 only one parameter can be selected which is shown as below:
170 \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
171 \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
172 \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
173 \param[in] data: data to be loaded, 0~4095
174 \param[out] none
175 \retval none
176 */
dac_data_set(uint8_t dac_out,uint32_t dac_align,uint16_t data)177 void dac_data_set(uint8_t dac_out, uint32_t dac_align, uint16_t data)
178 {
179 /* DAC_OUT0 data alignment */
180 if(DAC_OUT_0 == dac_out){
181 switch(dac_align){
182 /* 12-bit right-aligned data */
183 case DAC_ALIGN_12B_R:
184 OUT0_R12DH = data;
185 break;
186 /* 12-bit left-aligned data */
187 case DAC_ALIGN_12B_L:
188 OUT0_L12DH = data;
189 break;
190 /* 8-bit right-aligned data */
191 case DAC_ALIGN_8B_R:
192 OUT0_R8DH = data;
193 break;
194 default:
195 break;
196 }
197 }else{
198 /* DAC_OUT1 data alignment */
199 switch(dac_align){
200 /* 12-bit right-aligned data */
201 case DAC_ALIGN_12B_R:
202 OUT1_R12DH = data;
203 break;
204 /* 12-bit left-aligned data */
205 case DAC_ALIGN_12B_L:
206 OUT1_L12DH = data;
207 break;
208 /* 8-bit right-aligned data */
209 case DAC_ALIGN_8B_R:
210 OUT1_R8DH = data;
211 break;
212 default:
213 break;
214 }
215 }
216 }
217
218 /*!
219 \brief enable DAC output FIFO
220 \param[in] dac_out: DAC_OUT_x(x=0,1)
221 \param[out] none
222 \retval none
223 */
dac_output_fifo_enable(uint8_t dac_out)224 void dac_output_fifo_enable(uint8_t dac_out)
225 {
226 if(DAC_OUT_0 == dac_out){
227 DAC_CTL1 |= DAC_CTL1_FIFOEN0;
228 }else{
229 DAC_CTL1 |= DAC_CTL1_FIFOEN1;
230 }
231 }
232
233 /*!
234 \brief disable DAC output FIFO
235 \param[in] dac_out: DAC_OUT_x(x=0,1)
236 \param[out] none
237 \retval none
238 */
dac_output_fifo_disable(uint8_t dac_out)239 void dac_output_fifo_disable(uint8_t dac_out)
240 {
241
242 if(DAC_OUT_0 == dac_out){
243 DAC_CTL1 &= ~DAC_CTL1_FIFOEN0;
244 }else{
245 DAC_CTL1 &= ~DAC_CTL1_FIFOEN1;
246 }
247 }
248
249 /*!
250 \brief get DAC output FIFO number
251 \param[in] dac_out: DAC_OUT_x(x=0,1)
252 \param[out] none
253 \retval DAC output FIFO number: 0~4
254 */
dac_output_fifo_number_get(uint8_t dac_out)255 uint16_t dac_output_fifo_number_get(uint8_t dac_out)
256 {
257 uint16_t number = 0U;
258
259 if(DAC_OUT_0 == dac_out){
260 /* get the DAC_OUT0 output FIFO number */
261 number = (uint16_t)((uint16_t)DAC_STAT1 >> 4U);
262 }else{
263 /* get the DAC_OUT1 output FIFO number */
264 number = (uint16_t)(DAC_STAT1 >> 20U);
265 }
266 return number;
267 }
268
269 /*!
270 \brief enable DAC trigger
271 \param[in] dac_out: DAC_OUT_x(x=0,1)
272 \param[out] none
273 \retval none
274 */
dac_trigger_enable(uint8_t dac_out)275 void dac_trigger_enable(uint8_t dac_out)
276 {
277 if(DAC_OUT_0 == dac_out){
278 DAC_CTL0 |= DAC_CTL0_DTEN0;
279 }else{
280 DAC_CTL0 |= DAC_CTL0_DTEN1;
281 }
282 }
283
284 /*!
285 \brief disable DAC trigger
286 \param[in] dac_out: DAC_OUT_x(x=0,1)
287 \param[out] none
288 \retval none
289 */
dac_trigger_disable(uint8_t dac_out)290 void dac_trigger_disable(uint8_t dac_out)
291 {
292 if(DAC_OUT_0 == dac_out){
293 DAC_CTL0 &= ~DAC_CTL0_DTEN0;
294 }else{
295 DAC_CTL0 &= ~DAC_CTL0_DTEN1;
296 }
297 }
298
299 /*!
300 \brief configure DAC trigger source
301 \param[in] dac_out: DAC_OUT_x(x=0,1)
302 \param[in] triggersource: external triggers of DAC
303 only one parameter can be selected which is shown as below:
304 \arg DAC_TRIGGER_T5_TRGO: TIMER5 TRGO
305 \arg DAC_TRIGGER_T7_TRGO: TIMER7 TRGO (for GD32E50X_HD and GD32E50X_XD devices)
306 \arg DAC_TRIGGER_T2_TRGO: TIMER2 TRGO (for GD32E50X_CL devices)
307 \arg DAC_TRIGGER_T6_TRGO: TIMER6 TRGO
308 \arg DAC_TRIGGER_T4_TRGO: TIMER4 TRGO
309 \arg DAC_TRIGGER_T1_TRGO: TIMER1 TRGO
310 \arg DAC_TRIGGER_T3_TRGO: TIMER3 TRGO
311 \arg DAC_TRIGGER_EXTI_9: EXTI interrupt line9 event
312 \arg DAC_TRIGGER_SOFTWARE: software trigger
313 \arg DAC_TRIGGER_SHRTIMER_DACTRIG0: SHRTIMER_DACTRIG0 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
314 \arg DAC_TRIGGER_SHRTIMER_DACTRIG1: SHRTIMER_DACTRIG1 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
315 \arg DAC_TRIGGER_SHRTIMER_DACTRIG2: SHRTIMER_DACTRIG2 trigger(for GD32E50X_HD, GD32E50X_XD and GD32E50X_CL devices)
316 \param[out] none
317 \retval none
318 */
dac_trigger_source_config(uint8_t dac_out,uint32_t triggersource)319 void dac_trigger_source_config(uint8_t dac_out,uint32_t triggersource)
320 {
321 if(DAC_OUT_0 == dac_out){
322 /* configure DAC_OUT0 trigger source */
323 DAC_CTL0 &= (uint32_t)(~(DAC_CTL0_DTSEL0 | DAC_CTL0_DTSEL0_3));
324 DAC_CTL0 |= triggersource;
325 }else{
326 /* configure DAC_OUT1 trigger source */
327 DAC_CTL0 &= (uint32_t)(~(DAC_CTL0_DTSEL1 | DAC_CTL0_DTSEL1_3));
328 DAC_CTL0 |= (triggersource << OUT1_REG_OFFSET);
329 }
330 }
331
332 /*!
333 \brief enable DAC software trigger
334 \param[in] dac_out: DAC_OUT_x(x=0,1)
335 \retval none
336 */
dac_software_trigger_enable(uint8_t dac_out)337 void dac_software_trigger_enable(uint8_t dac_out)
338 {
339 if(DAC_OUT_0 == dac_out){
340 DAC_SWT |= DAC_SWT_SWTR0;
341 }else{
342 DAC_SWT |= DAC_SWT_SWTR1;
343 }
344 }
345
346 /*!
347 \brief disable DAC software trigger
348 \param[in] dac_out: DAC_OUT_x(x=0,1)
349 \param[out] none
350 \retval none
351 */
dac_software_trigger_disable(uint8_t dac_out)352 void dac_software_trigger_disable(uint8_t dac_out)
353 {
354 if(DAC_OUT_0 == dac_out){
355 DAC_SWT &= ~DAC_SWT_SWTR0;
356 }else{
357 DAC_SWT &= ~DAC_SWT_SWTR1;
358 }
359 }
360
361 /*!
362 \brief configure DAC wave mode
363 \param[in] dac_out: DAC_OUT_x(x=0,1)
364 \param[in] wave_mode: DAC wave mode
365 only one parameter can be selected which is shown as below:
366 \arg DAC_WAVE_DISABLE: wave mode disable
367 \arg DAC_WAVE_MODE_LFSR: LFSR noise mode
368 \arg DAC_WAVE_MODE_TRIANGLE: triangle noise mode
369 \param[out] none
370 \retval none
371 */
dac_wave_mode_config(uint8_t dac_out,uint32_t wave_mode)372 void dac_wave_mode_config(uint8_t dac_out, uint32_t wave_mode)
373 {
374 if(DAC_OUT_0 == dac_out){
375 /* configure DAC_OUT0 wave mode */
376 DAC_CTL0 &= ~DAC_CTL0_DWM0;
377 DAC_CTL0 |= wave_mode;
378 }else{
379 /* configure DAC_OUT1 wave mode */
380 DAC_CTL0 &= ~DAC_CTL0_DWM1;
381 DAC_CTL0 |= (wave_mode << OUT1_REG_OFFSET);
382 }
383 }
384
385 /*!
386 \brief configure DAC wave bit width
387 \param[in] dac_out: DAC_OUT_x(x=0,1)
388 \param[in] bit_width: DAC noise wave bit width
389 only one parameter can be selected which is shown as below:
390 \arg DAC_WAVE_BIT_WIDTH_1: bit width of the wave signal is 1
391 \arg DAC_WAVE_BIT_WIDTH_2: bit width of the wave signal is 2
392 \arg DAC_WAVE_BIT_WIDTH_3: bit width of the wave signal is 3
393 \arg DAC_WAVE_BIT_WIDTH_4: bit width of the wave signal is 4
394 \arg DAC_WAVE_BIT_WIDTH_5: bit width of the wave signal is 5
395 \arg DAC_WAVE_BIT_WIDTH_6: bit width of the wave signal is 6
396 \arg DAC_WAVE_BIT_WIDTH_7: bit width of the wave signal is 7
397 \arg DAC_WAVE_BIT_WIDTH_8: bit width of the wave signal is 8
398 \arg DAC_WAVE_BIT_WIDTH_9: bit width of the wave signal is 9
399 \arg DAC_WAVE_BIT_WIDTH_10: bit width of the wave signal is 10
400 \arg DAC_WAVE_BIT_WIDTH_11: bit width of the wave signal is 11
401 \arg DAC_WAVE_BIT_WIDTH_12: bit width of the wave signal is 12
402 \param[out] none
403 \retval none
404 */
dac_wave_bit_width_config(uint8_t dac_out,uint32_t bit_width)405 void dac_wave_bit_width_config(uint8_t dac_out, uint32_t bit_width)
406 {
407 if(DAC_OUT_0 == dac_out){
408 /* configure DAC_OUT0 wave bit width */
409 DAC_CTL0 &= ~DAC_CTL0_DWBW0;
410 DAC_CTL0 |= bit_width;
411 }else{
412 /* configure DAC_OUT1 wave bit width */
413 DAC_CTL0 &= ~DAC_CTL0_DWBW1;
414 DAC_CTL0 |= (bit_width << OUT1_REG_OFFSET);
415 }
416 }
417
418 /*!
419 \brief configure DAC LFSR noise mode
420 \param[in] dac_out: DAC_OUT_x(x=0,1)
421 \param[in] unmask_bits: LFSR noise unmask bits
422 only one parameter can be selected which is shown as below:
423 \arg DAC_LFSR_BIT0: unmask the LFSR bit0
424 \arg DAC_LFSR_BITS1_0: unmask the LFSR bits[1:0]
425 \arg DAC_LFSR_BITS2_0: unmask the LFSR bits[2:0]
426 \arg DAC_LFSR_BITS3_0: unmask the LFSR bits[3:0]
427 \arg DAC_LFSR_BITS4_0: unmask the LFSR bits[4:0]
428 \arg DAC_LFSR_BITS5_0: unmask the LFSR bits[5:0]
429 \arg DAC_LFSR_BITS6_0: unmask the LFSR bits[6:0]
430 \arg DAC_LFSR_BITS7_0: unmask the LFSR bits[7:0]
431 \arg DAC_LFSR_BITS8_0: unmask the LFSR bits[8:0]
432 \arg DAC_LFSR_BITS9_0: unmask the LFSR bits[9:0]
433 \arg DAC_LFSR_BITS10_0: unmask the LFSR bits[10:0]
434 \arg DAC_LFSR_BITS11_0: unmask the LFSR bits[11:0]
435 \param[out] none
436 \retval none
437 */
dac_lfsr_noise_config(uint8_t dac_out,uint32_t unmask_bits)438 void dac_lfsr_noise_config(uint8_t dac_out, uint32_t unmask_bits)
439 {
440 if(DAC_OUT_0 == dac_out){
441 /* configure DAC_OUT0 LFSR noise mode */
442 DAC_CTL0 &= ~DAC_CTL0_DWBW0;
443 DAC_CTL0 |= unmask_bits;
444 }else{
445 /* configure DAC_OUT1 LFSR noise mode */
446 DAC_CTL0 &= ~DAC_CTL0_DWBW1;
447 DAC_CTL0 |= (unmask_bits << OUT1_REG_OFFSET);
448 }
449 }
450
451 /*!
452 \brief configure DAC triangle noise mode
453 \param[in] dac_out: DAC_OUT_x(x=0,1)
454 \param[in] amplitude: the amplitude of the triangle
455 only one parameter can be selected which is shown as below:
456 \arg DAC_TRIANGLE_AMPLITUDE_1: triangle amplitude is 1
457 \arg DAC_TRIANGLE_AMPLITUDE_3: triangle amplitude is 3
458 \arg DAC_TRIANGLE_AMPLITUDE_7: triangle amplitude is 7
459 \arg DAC_TRIANGLE_AMPLITUDE_15: triangle amplitude is 15
460 \arg DAC_TRIANGLE_AMPLITUDE_31: triangle amplitude is 31
461 \arg DAC_TRIANGLE_AMPLITUDE_63: triangle amplitude is 63
462 \arg DAC_TRIANGLE_AMPLITUDE_127: triangle amplitude is 127
463 \arg DAC_TRIANGLE_AMPLITUDE_255: triangle amplitude is 255
464 \arg DAC_TRIANGLE_AMPLITUDE_511: triangle amplitude is 511
465 \arg DAC_TRIANGLE_AMPLITUDE_1023: triangle amplitude is 1023
466 \arg DAC_TRIANGLE_AMPLITUDE_2047: triangle amplitude is 2047
467 \arg DAC_TRIANGLE_AMPLITUDE_4095: triangle amplitude is 4095
468 \param[out] none
469 \retval none
470 */
dac_triangle_noise_config(uint8_t dac_out,uint32_t amplitude)471 void dac_triangle_noise_config(uint8_t dac_out, uint32_t amplitude)
472 {
473 if(DAC_OUT_0 == dac_out){
474 /* configure DAC_OUT0 triangle noise mode */
475 DAC_CTL0 &= ~DAC_CTL0_DWBW0;
476 DAC_CTL0 |= amplitude;
477 }else{
478 /* configure DAC_OUT1 triangle noise mode */
479 DAC_CTL0 &= ~DAC_CTL0_DWBW1;
480 DAC_CTL0 |= (amplitude << OUT1_REG_OFFSET);
481 }
482 }
483
484 /*!
485 \brief enable DAC concurrent mode
486 \param[in] none
487 \param[out] none
488 \retval none
489 */
dac_concurrent_enable(void)490 void dac_concurrent_enable(void)
491 {
492 uint32_t ctl = 0U;
493 ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
494 DAC_CTL0 |= (uint32_t)(ctl);
495 }
496
497 /*!
498 \brief disable DAC concurrent mode
499 \param[in] none
500 \param[out] none
501 \retval none
502 */
dac_concurrent_disable(void)503 void dac_concurrent_disable(void)
504 {
505 uint32_t ctl = 0U;
506 ctl = (uint32_t)(DAC_CTL0_DEN0 | DAC_CTL0_DEN1);
507 DAC_CTL0 &= (uint32_t)(~ctl);
508 }
509
510 /*!
511 \brief enable DAC concurrent software trigger
512 \param[in] none
513 \param[out] none
514 \retval none
515 */
dac_concurrent_software_trigger_enable(void)516 void dac_concurrent_software_trigger_enable(void)
517 {
518 uint32_t swt = 0U;
519 swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
520 DAC_SWT |= (uint32_t)(swt);
521 }
522
523 /*!
524 \brief disable DAC concurrent software trigger
525 \param[in] none
526 \param[out] none
527 \retval none
528 */
dac_concurrent_software_trigger_disable(void)529 void dac_concurrent_software_trigger_disable(void)
530 {
531 uint32_t swt = 0U;
532 swt = (uint32_t)(DAC_SWT_SWTR0 | DAC_SWT_SWTR1);
533 DAC_SWT &= (uint32_t)(~swt);
534 }
535
536 /*!
537 \brief enable DAC concurrent buffer
538 \param[in] none
539 \param[out] none
540 \retval none
541 */
dac_concurrent_output_buffer_enable(void)542 void dac_concurrent_output_buffer_enable(void)
543 {
544 uint32_t ctl = 0U;
545 ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
546 DAC_CTL0 &= (uint32_t)(~ctl);
547 }
548
549 /*!
550 \brief disable DAC concurrent buffer
551 \param[in] none
552 \param[out] none
553 \retval none
554 */
dac_concurrent_output_buffer_disable(void)555 void dac_concurrent_output_buffer_disable(void)
556 {
557 uint32_t ctl = 0U;
558 ctl = (uint32_t)(DAC_CTL0_DBOFF0 | DAC_CTL0_DBOFF1);
559 DAC_CTL0 |= (uint32_t)(ctl);
560 }
561
562 /*!
563 \brief set DAC concurrent mode data holding register value
564 \param[in] dac_align: DAC data alignment mode
565 only one parameter can be selected which is shown as below:
566 \arg DAC_ALIGN_12B_R: 12-bit right-aligned data
567 \arg DAC_ALIGN_12B_L: 12-bit left-aligned data
568 \arg DAC_ALIGN_8B_R: 8-bit right-aligned data
569 \param[in] data0: data to be loaded, 0~4095
570 \param[in] data1: data to be loaded, 0~4095
571 \param[out] none
572 \retval none
573 */
dac_concurrent_data_set(uint32_t dac_align,uint16_t data0,uint16_t data1)574 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1)
575 {
576 uint32_t data = 0U;
577 switch(dac_align){
578 /* 12-bit right-aligned data */
579 case DAC_ALIGN_12B_R:
580 data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
581 DACC_R12DH = (uint32_t)data;
582 break;
583 /* 12-bit left-aligned data */
584 case DAC_ALIGN_12B_L:
585 data = (uint32_t)(((uint32_t)data1 << DH_12BIT_OFFSET) | data0);
586 DACC_L12DH = (uint32_t)data;
587 break;
588 /* 8-bit right-aligned data */
589 case DAC_ALIGN_8B_R:
590 data = (uint32_t)(((uint32_t)data1 << DH_8BIT_OFFSET) | data0);
591 DACC_R8DH = (uint32_t)data;
592 break;
593 default:
594 break;
595 }
596 }
597
598 /*!
599 \brief get DAC flag
600 \param[in] dac_out: DAC_OUT_x(x=0,1)
601 \param[in] dac_flag: DAC flag
602 only one parameter can be selected which is shown as below:
603 \arg DAC_FLAG_DDUDR0: DAC_OUT0 DMA underrun flag
604 \arg DAC_FLAG_FF0: DAC_OUT0 FIFO full flag
605 \arg DAC_FLAG_FE0: DAC_OUT0 FIFO empty flag
606 \arg DAC_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow flag
607 \arg DAC_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow flag
608 \arg DAC_FLAG_DDUDR1: DAC_OUT1 DMA underrun flag
609 \arg DAC_FLAG_FF1: DAC_OUT1 FIFO full flag
610 \arg DAC_FLAG_FE1: DAC_OUT1 FIFO empty flag
611 \arg DAC_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow flag
612 \arg DAC_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow flag
613 \param[out] none
614 \retval FlagStatus: SET or RESET
615 */
dac_flag_get(uint8_t dac_out,uint32_t flag)616 FlagStatus dac_flag_get(uint8_t dac_out, uint32_t flag)
617 {
618 if(DAC_OUT_0 == dac_out){
619 /* check DAC_OUT0 flag */
620 if(DAC_FLAG_DDUDR0 == flag){
621 if(RESET != (DAC_STAT0 & DAC_STAT0_DDUDR0)){
622 return SET;
623 }else{
624 return RESET;
625 }
626 }else{
627 if(RESET != (DAC_STAT1 & flag)){
628 return SET;
629 }else{
630 return RESET;
631 }
632 }
633 }else{
634 /* check DAC_OUT1 flag */
635 if(DAC_FLAG_DDUDR1 == flag){
636 if(RESET != (DAC_STAT0 & DAC_STAT0_DDUDR1)){
637 return SET;
638 }else{
639 return RESET;
640 }
641 }else{
642 if(RESET != (DAC_STAT1 & flag)){
643 return SET;
644 }else{
645 return RESET;
646 }
647 }
648 }
649 }
650
651 /*!
652 \brief clear DAC flag
653 \param[in] dac_out: DAC_OUT_x(x=0,1)
654 \param[in] flag: DAC flag
655 only one parameter can be selected which is shown as below:
656 \arg DAC_FLAG_DDUDR0: DAC_OUT0 DMA underrun flag
657 \arg DAC_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow flag
658 \arg DAC_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow flag
659 \arg DAC_FLAG_DDUDR1: DAC_OUT1 DMA underrun flag
660 \arg DAC_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow flag
661 \arg DAC_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow flag
662 \param[out] none
663 \retval none
664 */
dac_flag_clear(uint8_t dac_out,uint32_t flag)665 void dac_flag_clear(uint8_t dac_out, uint32_t flag)
666 {
667 if(DAC_OUT_0 == dac_out){
668 /* clear DAC_OUT0 flag */
669 if(DAC_FLAG_DDUDR0 == flag){
670 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR0;
671 }else{
672 DAC_STAT1 |= (uint32_t)flag;
673 }
674 }else{
675 /* clear DAC_OUT1 flag */
676 if(DAC_FLAG_DDUDR1 == flag){
677 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR1;
678 }else{
679 DAC_STAT1 |= (uint32_t)flag;
680 }
681 }
682 }
683
684 /*!
685 \brief enable DAC interrupt
686 \param[in] dac_out: DAC_OUT_x(x=0,1)
687 \param[in] interrupt: the DAC interrupt
688 only one parameter can be selected which is shown as below:
689 \arg DAC_INT_DDUDRIE0: DAC_OUT0 DMA underrun interrupt enable
690 \arg DAC_INT_FIFOOVRIE0: DAC_OUT0 FIFO overflow interrupt enable
691 \arg DAC_INT_FIFOUDRIE0: DAC_OUT0 FIFO underflow interrupt enable
692 \arg DAC_INT_DDUDRIE1: DAC_OUT1 DMA underrun interrupt enable
693 \arg DAC_INT_FIFOOVRIE1: DAC_OUT1 FIFO overflow interrupt enable
694 \arg DAC_INT_FIFOUDRIE1: DAC_OUT1 FIFO underflow interrupt enable
695 \param[out] none
696 \retval none
697 */
dac_interrupt_enable(uint8_t dac_out,uint32_t interrupt)698 void dac_interrupt_enable(uint8_t dac_out, uint32_t interrupt)
699 {
700 if(DAC_OUT_0 == dac_out){
701 /* enable DAC_OUT0 interrupt */
702 if(DAC_INT_DDUDRIE0 == interrupt){
703 DAC_CTL0 |= (uint32_t)DAC_CTL0_DDUDRIE0;
704 }else{
705 DAC_CTL1 |= (uint32_t)interrupt;
706 }
707 }else{
708 /* enable DAC_OUT1 interrupt */
709 if(DAC_INT_DDUDRIE1 == interrupt){
710 DAC_CTL0 |= (uint32_t)DAC_CTL0_DDUDRIE1;
711 }else{
712 DAC_CTL1 |= (uint32_t)interrupt;
713 }
714 }
715 }
716
717 /*!
718 \brief disable DAC interrupt
719 \param[in] dac_out: DAC_OUT_x(x=0,1)
720 \param[in] interrupt: the DAC interrupt
721 only one parameter can be selected which is shown as below:
722 \arg DAC_INT_DDUDRIE0: DAC_OUT0 DMA underrun interrupt disable
723 \arg DAC_INT_FIFOOVRIE0: DAC_OUT0 FIFO overflow interrupt disable
724 \arg DAC_INT_FIFOUDRIE0: DAC_OUT0 FIFO underflow interrupt disable
725 \arg DAC_INT_DDUDRIE1: DAC_OUT1 DMA underrun interrupt disable
726 \arg DAC_INT_FIFOOVRIE1: DAC_OUT1 FIFO overflow interrupt disable
727 \arg DAC_INT_FIFOUDRIE1: DAC_OUT1 FIFO underflow interrupt disable
728 \param[out] none
729 \retval none
730 */
dac_interrupt_disable(uint8_t dac_out,uint32_t interrupt)731 void dac_interrupt_disable(uint8_t dac_out, uint32_t interrupt)
732 {
733 if(DAC_OUT_0 == dac_out){
734 /* disable DAC_OUT0 interrupt */
735 if(DAC_INT_DDUDRIE0 == interrupt){
736 DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DDUDRIE0);
737 }else{
738 DAC_CTL1 &= (uint32_t)(~interrupt);
739 }
740 }else{
741 /* disable DAC_OUT1 interrupt */
742 if(DAC_INT_DDUDRIE1 == interrupt){
743 DAC_CTL0 &= (uint32_t)(~DAC_CTL0_DDUDRIE1);
744 }else{
745 DAC_CTL1 &= (uint32_t)(~interrupt);
746 }
747 }
748 }
749
750 /*!
751 \brief get DAC interrupt flag
752 \param[in] dac_out: DAC_OUT_x(x=0,1)
753 \param[in] int_flag: DAC interrupt flag
754 only one parameter can be selected which is shown as below:
755 \arg DAC_INT_FLAG_DDUDR0: DAC_OUT0 DMA underrun interrupt flag
756 \arg DAC_INT_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow interrupt flag
757 \arg DAC_INT_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow interrupt flag
758 \arg DAC_INT_FLAG_DDUDR1: DAC_OUT1 DMA underrun interrupt flag
759 \arg DAC_INT_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow interrupt flag
760 \arg DAC_INT_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow interrupt flag
761 \param[out] none
762 \retval the state of DAC interrupt flag(SET or RESET)
763 */
dac_interrupt_flag_get(uint8_t dac_out,uint32_t int_flag)764 FlagStatus dac_interrupt_flag_get(uint8_t dac_out, uint32_t int_flag)
765 {
766 uint32_t reg1 = 0U, reg2 = 0U;
767
768 /* check DAC_OUT0 flag */
769 if(DAC_OUT_0 == dac_out){
770 /* check DAC_OUT0 interrupt flag */
771 if(DAC_INT_FLAG_DDUDR0 == int_flag){
772 reg1 = DAC_STAT0 & DAC_STAT0_DDUDR0;
773 reg2 = DAC_CTL0 & DAC_CTL0_DDUDRIE0;
774 }else if(DAC_INT_FLAG_FIFOOVR0 == int_flag){
775 reg1 = DAC_STAT1 & DAC_STAT1_FIFOOVR0;
776 reg2 = DAC_CTL1 & DAC_CTL1_FIFOOVRIE0;
777 }else{
778 reg1 = DAC_STAT1 & DAC_FLAG_FIFOUDR0;
779 reg2 = DAC_CTL1 & DAC_INT_FIFOUDRIE0;
780 }
781 }else{
782 /* check DAC_OUT1 interrupt flag */
783 if(DAC_INT_FLAG_DDUDR1 == int_flag){
784 reg1 = DAC_STAT0 & DAC_STAT0_DDUDR1;
785 reg2 = DAC_CTL0 & DAC_CTL0_DDUDRIE1;
786 }else if(DAC_INT_FLAG_FIFOOVR1 == int_flag){
787 reg1 = DAC_STAT1 & DAC_STAT1_FIFOOVR1;
788 reg2 = DAC_CTL1 & DAC_CTL1_FIFOOVRIE1;
789 }else{
790 reg1 = DAC_STAT1 & DAC_FLAG_FIFOUDR1;
791 reg2 = DAC_CTL1 & DAC_INT_FIFOUDRIE1;
792 }
793 }
794
795 /*get DAC interrupt flag status */
796 if((RESET != reg1) && (RESET != reg2)){
797 return SET;
798 }else{
799 return RESET;
800 }
801 }
802
803 /*!
804 \brief clear DAC interrupt flag
805 \param[in] dac_out: DAC_OUT_x(x=0,1)
806 \param[in] int_flag: DAC interrupt flag
807 only one parameter can be selected which is shown as below:
808 \arg DAC_INT_FLAG_DDUDR0: DAC_OUT0 DMA underrun interrupt flag
809 \arg DAC_INT_FLAG_FIFOOVR0: DAC_OUT0 FIFO overflow interrupt flag
810 \arg DAC_INT_FLAG_FIFOUDR0: DAC_OUT0 FIFO underflow interrupt flag
811 \arg DAC_INT_FLAG_DDUDR1: DAC_OUT1 DMA underrun interrupt flag
812 \arg DAC_INT_FLAG_FIFOOVR1: DAC_OUT1 FIFO overflow interrupt flag
813 \arg DAC_INT_FLAG_FIFOUDR1: DAC_OUT1 FIFO underflow interrupt flag
814 \param[out] none
815 \retval none
816 */
dac_interrupt_flag_clear(uint8_t dac_out,uint32_t int_flag)817 void dac_interrupt_flag_clear(uint8_t dac_out, uint32_t int_flag)
818 {
819 if(DAC_OUT_0 == dac_out){
820 /* clear DAC_OUT0 interrupt flag */
821 if(DAC_INT_FLAG_DDUDR0 == int_flag){
822 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR0;
823 }else{
824 DAC_STAT1 |= (uint32_t)int_flag;
825 }
826 }else{
827 /* clear DAC_OUT1 interrupt flag */
828 if(DAC_INT_FLAG_DDUDR1 == int_flag){
829 DAC_STAT0 |= (uint32_t)DAC_STAT0_DDUDR1;
830 }else{
831 DAC_STAT1 |= (uint32_t)int_flag;
832 }
833 }
834 }
835
