1 /*! 2 \file gd32e50x_adc.h 3 \brief definitions for the ADC 4 5 \version 2020-03-10, V1.0.0, firmware for GD32E50x 6 \version 2020-08-26, V1.1.0, firmware for GD32E50x 7 \version 2021-03-23, V1.2.0, firmware for GD32E50x 8 */ 9 10 /* 11 Copyright (c) 2021, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32E50X_ADC_H 38 #define GD32E50X_ADC_H 39 40 #include "gd32e50x.h" 41 42 /* ADC definitions */ 43 #define ADC0 ADC_BASE 44 #define ADC1 (ADC_BASE + 0x00000400U) 45 #if (defined(GD32E50X_HD) || defined(GD32E50X_XD)||defined(GD32EPRT)) 46 #define ADC2 (ADC_BASE + 0x00001800U) 47 #endif 48 49 /* registers definitions */ 50 #define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */ 51 #define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */ 52 #define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */ 53 #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC sampling time register 0 */ 54 #define ADC_SAMPT1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC sampling time register 1 */ 55 #define ADC_IOFF0(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ 56 #define ADC_IOFF1(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ 57 #define ADC_IOFF2(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ 58 #define ADC_IOFF3(adcx) REG32((adcx) + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ 59 #define ADC_WDHT0(adcx) REG32((adcx) + 0x00000024U) /*!< ADC watchdog high threshold register 0 */ 60 #define ADC_WDLT0(adcx) REG32((adcx) + 0x00000028U) /*!< ADC watchdog low threshold register 0 */ 61 #define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence register 0 */ 62 #define ADC_RSQ1(adcx) REG32((adcx) + 0x00000030U) /*!< ADC regular sequence register 1 */ 63 #define ADC_RSQ2(adcx) REG32((adcx) + 0x00000034U) /*!< ADC regular sequence register 2 */ 64 #define ADC_ISQ(adcx) REG32((adcx) + 0x00000038U) /*!< ADC inserted sequence register */ 65 #define ADC_IDATA0(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC inserted data register 0 */ 66 #define ADC_IDATA1(adcx) REG32((adcx) + 0x00000040U) /*!< ADC inserted data register 1 */ 67 #define ADC_IDATA2(adcx) REG32((adcx) + 0x00000044U) /*!< ADC inserted data register 2 */ 68 #define ADC_IDATA3(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted data register 3 */ 69 #define ADC_RDATA(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC regular data register */ 70 #define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */ 71 #define ADC_WD1SR(adcx) REG32((adcx) + 0x000000A0U) /*!< ADC watchdog 1 channel selection register */ 72 #define ADC_WD2SR(adcx) REG32((adcx) + 0x000000A4U) /*!< ADC watchdog 2 channel selection register */ 73 #define ADC_WDT1(adcx) REG32((adcx) + 0x000000A8U) /*!< ADC watchdog threshold register 1 */ 74 #define ADC_WDT2(adcx) REG32((adcx) + 0x000000ACU) /*!< ADC watchdog threshold register 2 */ 75 #define ADC_DIFCTL(adcx) REG32((adcx) + 0x000000B0U) /*!< ADC differential mode control register */ 76 77 /* bits definitions */ 78 /* ADC_STAT */ 79 #define ADC_STAT_WDE0 BIT(0) /*!< analog watchdog 0 event flag */ 80 #define ADC_STAT_EOC BIT(1) /*!< end of conversion */ 81 #define ADC_STAT_EOIC BIT(2) /*!< inserted channel end of conversion */ 82 #define ADC_STAT_STIC BIT(3) /*!< inserted channel start flag */ 83 #define ADC_STAT_STRC BIT(4) /*!< regular channel start flag */ 84 #define ADC_STAT_WDE1 BIT(30) /*!< analog watchdog 1 event flag */ 85 #define ADC_STAT_WDE2 BIT(31) /*!< analog watchdog 2 event flag */ 86 87 /* ADC_CTL0 */ 88 #define ADC_CTL0_WD0CHSEL BITS(0, 4) /*!< analog watchdog 0 channel select bits */ 89 #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ 90 #define ADC_CTL0_WDE0IE BIT(6) /*!< analog watchdog 0 interrupt enable */ 91 #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ 92 #define ADC_CTL0_SM BIT(8) /*!< scan mode */ 93 #define ADC_CTL0_WD0SC BIT(9) /*!< when in scan mode, analog watchdog 0 is effective on a single channel */ 94 #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ 95 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ 96 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ 97 #define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */ 98 #define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */ 99 #define ADC_CTL0_IWD0EN BIT(22) /*!< analog watchdog 0 enable on inserted channels */ 100 #define ADC_CTL0_RWD0EN BIT(23) /*!< analog watchdog 0 enable on regular channels */ 101 #define ADC_CTL0_WDE1IE BIT(30) /*!< analog watchdog 1 interrupt enable */ 102 #define ADC_CTL0_WDE2IE BIT(31) /*!< analog watchdog 2 interrupt enable */ 103 104 /* ADC_CTL1 */ 105 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ 106 #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ 107 #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ 108 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ 109 #define ADC_CTL1_CLBNUM BITS(4, 6) /*!< ADC calibration times */ 110 #define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */ 111 #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ 112 #define ADC_CTL1_ETSIC (BIT(30) | BITS(12, 14)) /*!< external trigger select for inserted channel */ 113 #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ 114 #define ADC_CTL1_ETSRC (BIT(31) | BITS(17, 19)) /*!< external trigger select for regular channel */ 115 #define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ 116 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ 117 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ 118 #define ADC_CTL1_TSVREN BIT(23) /*!< channel 16 and 17 enable of ADC0 */ 119 #define ADC_CTL1_ETSIC4 BIT(30) /*!< bit 4 of ETSIC */ 120 #define ADC_CTL1_ETSRC4 BIT(31) /*!< bit 4 of ETSRC */ 121 122 /* ADC_SAMPTx x=0..1 */ 123 #define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n(n=0..17) sample time selection */ 124 125 /* ADC_IOFFx x=0..3 */ 126 #define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */ 127 128 /* ADC_WDHT */ 129 #define ADC_WDHT0_WDHT0 BITS(0, 11) /*!< analog watchdog 0 high threshold */ 130 131 /* ADC_WDLT */ 132 #define ADC_WDLT0_WDLT0 BITS(0, 11) /*!< analog watchdog 0 low threshold */ 133 134 /* ADC_RSQx x=0..2 */ 135 #define ADC_RSQX_RSQN BITS(0, 4) /*!< n conversion in regular sequence */ 136 #define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */ 137 138 /* ADC_ISQ */ 139 #define ADC_ISQ_ISQN BITS(0, 4) /*!< n conversion in regular sequence */ 140 #define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */ 141 142 /* ADC_IDATAx x=0..3 */ 143 #define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted channel x conversion data */ 144 145 /* ADC_RDATA */ 146 #define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */ 147 #define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */ 148 149 /* ADC_OVSAMPCTL */ 150 #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ 151 #define ADC_OVSAMPCTL_OVSR BITS(2, 4) /*!< oversampling ratio */ 152 #define ADC_OVSAMPCTL_OVSS BITS(5, 8) /*!< oversampling shift */ 153 #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ 154 #define ADC_OVSAMPCTL_DRES BITS(12, 13) /*!< ADC resolution */ 155 156 /* ADC_WD1SR */ 157 #define ADC_WD1SR_AWD1CS BITS(0, 17) /*!< analog watchdog 1 channel selection */ 158 159 /* ADC_WD2SR */ 160 #define ADC_WD2SR_AWD2CS BITS(0, 17) /*!< analog watchdog 2 channel selection */ 161 162 /* ADC_WDT1 */ 163 #define ADC_WDT1_WDLT1 BITS(0, 7) /*!< analog watchdog 1 low threshold */ 164 #define ADC_WDT1_WDHT1 BITS(16, 23) /*!< analog watchdog 1 high threshold */ 165 166 /* ADC_WDT2 */ 167 #define ADC_WDT2_WDLT2 BITS(0, 7) /*!< analog watchdog 2 low threshold */ 168 #define ADC_WDT2_WDHT2 BITS(16, 23) /*!< analog watchdog 2 high threshold */ 169 170 /* ADC_DIFCTL */ 171 #define ADC_DIFCTL_DIFCTL BITS(0, 17) /*!< Differential mode for channel 17..0 */ 172 173 /* constants definitions */ 174 /* ADC flag definitions */ 175 #define ADC_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event flag */ 176 #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ 177 #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ 178 #define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ 179 #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ 180 #define ADC_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event flag */ 181 #define ADC_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event flag */ 182 183 /* ADC_CTL0 register value */ 184 #define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ 185 186 /* ADC special function definitions */ 187 #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ 188 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ 189 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ 190 191 /* ADC synchronization mode */ 192 #define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ 193 #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ 194 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ 195 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ 196 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ 197 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ 198 #define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ 199 #define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ 200 #define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ 201 #define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ 202 #define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ 203 204 /* ADC calibration times */ 205 #define CTL1_CLBNUM(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4)) /*!< write value to ADC_CTL1_CLBNUM bit field */ 206 #define ADC_CALIBRATION_NUM1 CTL1_CLBNUM(0) /*!< ADC calibration 1 time */ 207 #define ADC_CALIBRATION_NUM2 CTL1_CLBNUM(1) /*!< ADC calibration 2 times */ 208 #define ADC_CALIBRATION_NUM4 CTL1_CLBNUM(2) /*!< ADC calibration 4 times */ 209 #define ADC_CALIBRATION_NUM8 CTL1_CLBNUM(3) /*!< ADC calibration 8 times */ 210 #define ADC_CALIBRATION_NUM16 CTL1_CLBNUM(4) /*!< ADC calibration 16 times */ 211 #define ADC_CALIBRATION_NUM32 CTL1_CLBNUM(5) /*!< ADC calibration 32 times */ 212 213 /* ADC data alignment */ 214 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ 215 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ 216 217 /* ADC external trigger select for regular channel */ 218 #define CTL1_ETSRC(regval) (BITS(17, 19) & ((uint32_t)(regval) << 17)) /*!< write value to ADC_CTL1_ETSRC bit field */ 219 #define ADC0_1_EXTTRIG_REGULAR_T0_CH0 CTL1_ETSRC(0) /*!< TIMER0 CH0 event select */ 220 #define ADC0_1_EXTTRIG_REGULAR_T0_CH1 CTL1_ETSRC(1) /*!< TIMER0 CH1 event select */ 221 #define ADC0_1_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ 222 #define ADC0_1_EXTTRIG_REGULAR_T1_CH1 CTL1_ETSRC(3) /*!< TIMER1 CH1 event select */ 223 #define ADC0_1_EXTTRIG_REGULAR_T2_TRGO CTL1_ETSRC(4) /*!< TIMER2 TRGO event select */ 224 #define ADC0_1_EXTTRIG_REGULAR_T3_CH3 CTL1_ETSRC(5) /*!< TIMER3 CH3 event select */ 225 #define ADC0_1_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(6) /*!< TIMER7 TRGO event select */ 226 #define ADC0_1_EXTTRIG_REGULAR_EXTI_11 CTL1_ETSRC(6) /*!< external interrupt line 11 */ 227 #define ADC0_1_2_EXTTRIG_REGULAR_NONE CTL1_ETSRC(7) /*!< software trigger */ 228 #if !defined (GD32EPRT) 229 #define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG0 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(0)) /*!< SHRTIMER_ADCTRG0 output select */ 230 #define ADC0_1_EXTTRIG_REGULAR_SHRTIMER_ADCTRG2 (ADC_CTL1_ETSRC4 | CTL1_ETSRC(1)) /*!< SHRTIMER_ADCTRG2 output select */ 231 #endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */ 232 #define ADC2_EXTTRIG_REGULAR_T2_CH0 CTL1_ETSRC(0) /*!< TIMER2 CH0 event select */ 233 #define ADC2_EXTTRIG_REGULAR_T1_CH2 CTL1_ETSRC(1) /*!< TIMER1 CH2 event select */ 234 #define ADC2_EXTTRIG_REGULAR_T0_CH2 CTL1_ETSRC(2) /*!< TIMER0 CH2 event select */ 235 #define ADC2_EXTTRIG_REGULAR_T7_CH0 CTL1_ETSRC(3) /*!< TIMER7 CH0 event select */ 236 #define ADC2_EXTTRIG_REGULAR_T7_TRGO CTL1_ETSRC(4) /*!< TIMER7 TRGO event select */ 237 #define ADC2_EXTTRIG_REGULAR_T4_CH0 CTL1_ETSRC(5) /*!< TIMER4 CH0 event select */ 238 #define ADC2_EXTTRIG_REGULAR_T4_CH2 CTL1_ETSRC(6) /*!< TIMER4 CH2 event select */ 239 240 /* ADC external trigger select for inserted channel */ 241 #define CTL1_ETSIC(regval) (BITS(12, 14) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_CTL1_ETSIC bit field */ 242 #define ADC0_1_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ 243 #define ADC0_1_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ 244 #define ADC0_1_EXTTRIG_INSERTED_T1_TRGO CTL1_ETSIC(2) /*!< TIMER1 TRGO event select */ 245 #define ADC0_1_EXTTRIG_INSERTED_T1_CH0 CTL1_ETSIC(3) /*!< TIMER1 CH0 event select */ 246 #define ADC0_1_EXTTRIG_INSERTED_T2_CH3 CTL1_ETSIC(4) /*!< TIMER2 CH3 event select */ 247 #define ADC0_1_EXTTRIG_INSERTED_T3_TRGO CTL1_ETSIC(5) /*!< TIMER3 TRGO event select */ 248 #define ADC0_1_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(6) /*!< TIMER7 CH3 event select */ 249 #define ADC0_1_EXTTRIG_INSERTED_EXTI_15 CTL1_ETSIC(6) /*!< external interrupt line 15 */ 250 #define ADC0_1_2_EXTTRIG_INSERTED_NONE CTL1_ETSIC(7) /*!< software trigger */ 251 #if !defined (GD32EPRT) 252 #define ADC0_1_EXTTRIG_INSERTED_SHRTIMER_ADCTRG1 (ADC_CTL1_ETSIC4 | CTL1_ETSIC(0)) /*!< SHRTIMER_ADCTRG1 output select */ 253 #define ADC0_1_EXTTRIG_INSERTED_SHRTIMER_ADCTRG3 (ADC_CTL1_ETSIC4 | CTL1_ETSIC(1)) /*!< SHRTIMER_ADCTRG3 output select */ 254 #endif /* defined (GD32E50X_HD) && defined (GD32E50X_XD) && defined (GD32E50X_CL) */ 255 #define ADC2_EXTTRIG_INSERTED_T0_TRGO CTL1_ETSIC(0) /*!< TIMER0 TRGO event select */ 256 #define ADC2_EXTTRIG_INSERTED_T0_CH3 CTL1_ETSIC(1) /*!< TIMER0 CH3 event select */ 257 #define ADC2_EXTTRIG_INSERTED_T3_CH2 CTL1_ETSIC(2) /*!< TIMER3 CH2 event select */ 258 #define ADC2_EXTTRIG_INSERTED_T7_CH1 CTL1_ETSIC(3) /*!< TIMER7 CH1 event select */ 259 #define ADC2_EXTTRIG_INSERTED_T7_CH3 CTL1_ETSIC(4) /*!< TIMER7 CH3 event select */ 260 #define ADC2_EXTTRIG_INSERTED_T4_TRGO CTL1_ETSIC(5) /*!< TIMER4 TRGO event select */ 261 #define ADC2_EXTTRIG_INSERTED_T4_CH3 CTL1_ETSIC(6) /*!< TIMER4 CH3 event select */ 262 263 /* ADC_SAMPTX register value */ 264 #define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ 265 #define ADC_SAMPLETIME_1POINT5 SAMPTX_SPT(0) /*!< 1.5 sampling cycles */ 266 #define ADC_SAMPLETIME_7POINT5 SAMPTX_SPT(1) /*!< 7.5 sampling cycles */ 267 #define ADC_SAMPLETIME_13POINT5 SAMPTX_SPT(2) /*!< 13.5 sampling cycles */ 268 #define ADC_SAMPLETIME_28POINT5 SAMPTX_SPT(3) /*!< 28.5 sampling cycles */ 269 #define ADC_SAMPLETIME_41POINT5 SAMPTX_SPT(4) /*!< 41.5 sampling cycles */ 270 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(5) /*!< 55.5 sampling cycles */ 271 #define ADC_SAMPLETIME_71POINT5 SAMPTX_SPT(6) /*!< 71.5 sampling cycles */ 272 #define ADC_SAMPLETIME_239POINT5 SAMPTX_SPT(7) /*!< 239.5 sampling cycles */ 273 274 /* ADC data offset for inserted channel x */ 275 #define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 276 277 /* ADC analog watchdog 0 high threshold */ 278 #define WDHT0_WDHT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 279 280 /* ADC analog watchdog 0 low threshold */ 281 #define WDLT0_WDLT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 282 283 /* ADC analog watchdog 1 high threshold */ 284 #define WDT1_WDHT1(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16)) 285 286 /* ADC analog watchdog 1 low threshold */ 287 #define WDT1_WDLT1(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0)) 288 289 /* ADC analog watchdog 2 high threshold */ 290 #define WDT2_WDHT2(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16)) 291 292 /* ADC analog watchdog 2 low threshold */ 293 #define WDT2_WDLT2(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0)) 294 295 /* ADC regular channel group length */ 296 #define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) 297 298 /* ADC inserted channel group length */ 299 #define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) 300 301 /* adc_ovsampctl register value */ 302 /* ADC resolution */ 303 #define OVSAMPCTL_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ 304 #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ 305 #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ 306 #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ 307 #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ 308 309 /* oversampling shift */ 310 #define OVSAMPCTL_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ 311 #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ 312 #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ 313 #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ 314 #define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ 315 #define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ 316 #define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ 317 #define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ 318 #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ 319 #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ 320 321 /* oversampling ratio */ 322 #define OVSAMPCTL_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ 323 #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ 324 #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ 325 #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ 326 #define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ 327 #define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ 328 #define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ 329 #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ 330 #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ 331 332 /* triggered oversampling */ 333 #define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ 334 #define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ 335 336 /* ADC channel group definitions */ 337 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ 338 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ 339 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ 340 341 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ 342 343 /* ADC inserted channel definitions */ 344 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ 345 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ 346 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ 347 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ 348 349 /* ADC channel definitions */ 350 #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ 351 #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ 352 #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ 353 #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ 354 #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ 355 #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ 356 #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ 357 #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ 358 #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ 359 #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ 360 #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ 361 #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ 362 #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ 363 #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ 364 #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ 365 #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ 366 #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ 367 #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ 368 369 /* analog watchdog 1/2 channel selection for channel n(n=0..17) */ 370 #define ADC_AWD1_2_SELECTION_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 analog watchdog 1/2 selection */ 371 #define ADC_AWD1_2_SELECTION_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 analog watchdog 1/2 selection */ 372 #define ADC_AWD1_2_SELECTION_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 analog watchdog 1/2 selection */ 373 #define ADC_AWD1_2_SELECTION_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 analog watchdog 1/2 selection */ 374 #define ADC_AWD1_2_SELECTION_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 analog watchdog 1/2 selection */ 375 #define ADC_AWD1_2_SELECTION_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 analog watchdog 1/2 selection */ 376 #define ADC_AWD1_2_SELECTION_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 analog watchdog 1/2 selection */ 377 #define ADC_AWD1_2_SELECTION_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 analog watchdog 1/2 selection */ 378 #define ADC_AWD1_2_SELECTION_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 analog watchdog 1/2 selection */ 379 #define ADC_AWD1_2_SELECTION_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 analog watchdog 1/2 selection */ 380 #define ADC_AWD1_2_SELECTION_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 analog watchdog 1/2 selection */ 381 #define ADC_AWD1_2_SELECTION_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 analog watchdog 1/2 selection */ 382 #define ADC_AWD1_2_SELECTION_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 analog watchdog 1/2 selection */ 383 #define ADC_AWD1_2_SELECTION_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 analog watchdog 1/2 selection */ 384 #define ADC_AWD1_2_SELECTION_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 analog watchdog 1/2 selection */ 385 #define ADC_AWD1_2_SELECTION_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 analog watchdog 1/2 selection */ 386 #define ADC_AWD1_2_SELECTION_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 analog watchdog 1/2 selection */ 387 #define ADC_AWD1_2_SELECTION_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 analog watchdog 1/2 selection */ 388 #define ADC_AWD1_2_SELECTION_CHANNEL_ALL ((uint32_t)0x0003FFFFU) /*!< all ADC channels analog watchdog 1/2 selection */ 389 390 /* Differential mode for channel n(n=0..17) */ 391 #define ADC_DIFFERENTIAL_MODE_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 differential mode */ 392 #define ADC_DIFFERENTIAL_MODE_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 differential mode */ 393 #define ADC_DIFFERENTIAL_MODE_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 differential mode */ 394 #define ADC_DIFFERENTIAL_MODE_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 differential mode */ 395 #define ADC_DIFFERENTIAL_MODE_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 differential mode */ 396 #define ADC_DIFFERENTIAL_MODE_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 differential mode */ 397 #define ADC_DIFFERENTIAL_MODE_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 differential mode */ 398 #define ADC_DIFFERENTIAL_MODE_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 differential mode */ 399 #define ADC_DIFFERENTIAL_MODE_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 differential mode */ 400 #define ADC_DIFFERENTIAL_MODE_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 differential mode */ 401 #define ADC_DIFFERENTIAL_MODE_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 differential mode */ 402 #define ADC_DIFFERENTIAL_MODE_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 differential mode */ 403 #define ADC_DIFFERENTIAL_MODE_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 differential mode */ 404 #define ADC_DIFFERENTIAL_MODE_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 differential mode */ 405 #define ADC_DIFFERENTIAL_MODE_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 differential mode */ 406 #define ADC_DIFFERENTIAL_MODE_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 differential mode */ 407 #define ADC_DIFFERENTIAL_MODE_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 differential mode */ 408 #define ADC_DIFFERENTIAL_MODE_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 differential mode */ 409 #define ADC_DIFFERENTIAL_MODE_CHANNEL_ALL ((uint32_t)0x00007FFFU) /*!< all ADC channelx(x=0..14) differential mode */ 410 411 /* ADC interrupt */ 412 #define ADC_INT_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt */ 413 #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ 414 #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ 415 #define ADC_INT_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt */ 416 #define ADC_INT_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event interrupt */ 417 418 /* ADC interrupt flag */ 419 #define ADC_INT_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt flag */ 420 #define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ 421 #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ 422 #define ADC_INT_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt flag */ 423 #define ADC_INT_FLAG_WDE2 ADC_STAT_WDE2 /*!< analog watchdog 2 event interrupt flag */ 424 /* function declarations */ 425 426 /* ADC deinitialization and initialization functions */ 427 /* reset ADC */ 428 void adc_deinit(uint32_t adc_periph); 429 /* enable ADC interface */ 430 void adc_enable(uint32_t adc_periph); 431 /* disable ADC interface */ 432 void adc_disable(uint32_t adc_periph); 433 434 /* ADC calibration and DMA functions */ 435 /* ADC calibration and reset calibration */ 436 void adc_calibration_enable(uint32_t adc_periph); 437 /* configure ADC calibration number */ 438 void adc_calibration_number(uint32_t adc_periph, uint32_t clb_num); 439 /* enable DMA request */ 440 void adc_dma_mode_enable(uint32_t adc_periph); 441 /* disable DMA request */ 442 void adc_dma_mode_disable(uint32_t adc_periph); 443 444 /* configure ADC temperature sensor and vrefint channel */ 445 /* enable the temperature sensor and vrefint channel */ 446 void adc_tempsensor_vrefint_enable(void); 447 /* disable the temperature sensor and vrefint channel */ 448 void adc_tempsensor_vrefint_disable(void); 449 450 /* ADC special function functions */ 451 /* configure ADC discontinuous mode */ 452 void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); 453 /* configure the ADC0 mode */ 454 void adc_mode_config(uint32_t mode); 455 /* configure ADC special function */ 456 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); 457 458 /* ADC channel configuration functions */ 459 /* configure ADC data alignment */ 460 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); 461 /* configure the length of regular channel group or inserted channel group */ 462 void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); 463 /* configure ADC regular channel */ 464 void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); 465 /* configure ADC inserted channel */ 466 void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); 467 /* configure ADC inserted channel offset */ 468 void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); 469 /* configure differential mode for channel */ 470 void adc_channel_differential_mode_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue); 471 472 /* ADC external trigger functions */ 473 /* configure ADC external trigger */ 474 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); 475 /* configure ADC external trigger source */ 476 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); 477 /* enable ADC software trigger */ 478 void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); 479 480 /* ADC data read functions */ 481 /* read ADC regular group data register */ 482 uint16_t adc_regular_data_read(uint32_t adc_periph); 483 /* read ADC inserted group data register */ 484 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); 485 /* read the last ADC0 and ADC1 conversion result data in sync mode */ 486 uint32_t adc_sync_mode_convert_value_read(void); 487 488 /* ADC analog watchdog functions */ 489 /* configure ADC analog watchdog 0 single channel */ 490 void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); 491 /* configure ADC analog watchdog 0 group channel */ 492 void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); 493 /* disable ADC analog watchdog 0 */ 494 void adc_watchdog0_disable(uint32_t adc_periph); 495 /* configure ADC analog watchdog 1 channel */ 496 void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue); 497 /* configure ADC analog watchdog 2 channel */ 498 void adc_watchdog2_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue); 499 /* disable ADC analog watchdog 1 */ 500 void adc_watchdog1_disable(uint32_t adc_periph); 501 /* disable ADC analog watchdog 2 */ 502 void adc_watchdog2_disable(uint32_t adc_periph); 503 /* configure ADC analog watchdog 0 threshold */ 504 void adc_watchdog0_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); 505 /* configure ADC analog watchdog 1 threshold */ 506 void adc_watchdog1_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold); 507 /* configure ADC analog watchdog 2 threshold */ 508 void adc_watchdog2_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold); 509 510 /* ADC resolution and oversample functions */ 511 /* configure ADC resolution */ 512 void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); 513 /* configure ADC oversample mode */ 514 void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio); 515 /* enable ADC oversample mode */ 516 void adc_oversample_mode_enable(uint32_t adc_periph); 517 /* disable ADC oversample mode */ 518 void adc_oversample_mode_disable(uint32_t adc_periph); 519 520 /* flag and interrupt functions */ 521 /* get the ADC flag */ 522 FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t flag); 523 /* clear the ADC flag */ 524 void adc_flag_clear(uint32_t adc_periph , uint32_t flag); 525 /* enable ADC interrupt */ 526 void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt); 527 /* disable ADC interrupt */ 528 void adc_interrupt_disable(uint32_t adc_periph , uint32_t interrupt); 529 /* get the ADC interrupt */ 530 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag); 531 /* clear the ADC flag */ 532 void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t int_flag); 533 534 #endif /* GD32E50X_ADC_H */ 535
