1 /* 2 * Copyright (c) 2022 Teslabs Engineering S.L. 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef GD32E507XX_AFIO_H_ 7 #define GD32E507XX_AFIO_H_ 8 9 #include "gd32-afio.h" 10 11 /** SPI0 (no remap) */ 12 #define GD32_SPI0_NORMP GD32_REMAP(0U, 0U, 0x1U, 0U) 13 /** SPI0 (remap) */ 14 #define GD32_SPI0_RMP GD32_REMAP(0U, 0U, 0x1U, 1U) 15 16 /** I2C0 (no remap) */ 17 #define GD32_I2C0_NORMP GD32_REMAP(0U, 1U, 0x1U, 0U) 18 /** I2C0 (remap) */ 19 #define GD32_I2C0_RMP GD32_REMAP(0U, 1U, 0x1U, 1U) 20 21 /** USART0 (no remap) */ 22 #define GD32_USART0_NORMP GD32_REMAP(0U, 2U, 0x1U, 0U) 23 /** USART0 (remap) */ 24 #define GD32_USART0_RMP GD32_REMAP(0U, 2U, 0x1U, 1U) 25 26 /** USART1 (no remap) */ 27 #define GD32_USART1_NORMP GD32_REMAP(0U, 3U, 0x1U, 0U) 28 /** USART1 (remap) */ 29 #define GD32_USART1_RMP GD32_REMAP(0U, 3U, 0x1U, 1U) 30 31 /** USART2 (no remap) */ 32 #define GD32_USART2_NORMP GD32_REMAP(0U, 4U, 0x3U, 0U) 33 /** USART2 (partial remap) */ 34 #define GD32_USART2_PRMP GD32_REMAP(0U, 4U, 0x3U, 1U) 35 /** USART2 (full remap) */ 36 #define GD32_USART2_FRMP GD32_REMAP(0U, 4U, 0x3U, 3U) 37 38 /** TIMER0 (no remap) */ 39 #define GD32_TIMER0_NORMP GD32_REMAP(0U, 6U, 0x3U, 0U) 40 /** TIMER0 (partial remap) */ 41 #define GD32_TIMER0_PRMP GD32_REMAP(0U, 6U, 0x3U, 1U) 42 /** TIMER0 (full remap) */ 43 #define GD32_TIMER0_FRMP GD32_REMAP(0U, 6U, 0x3U, 3U) 44 45 /** TIMER1 (no remap) */ 46 #define GD32_TIMER1_NORMP GD32_REMAP(0U, 8U, 0x3U, 0U) 47 /** TIMER1 (partial remap 1) */ 48 #define GD32_TIMER1_PRMP1 GD32_REMAP(0U, 8U, 0x3U, 1U) 49 /** TIMER1 (partial remap 2) */ 50 #define GD32_TIMER1_PRMP2 GD32_REMAP(0U, 8U, 0x3U, 2U) 51 /** TIMER1 (full remap) */ 52 #define GD32_TIMER1_FRMP GD32_REMAP(0U, 8U, 0x3U, 3U) 53 54 /** TIMER2 (no remap) */ 55 #define GD32_TIMER2_NORMP GD32_REMAP(0U, 10U, 0x3U, 0U) 56 /** TIMER2 (partial remap) */ 57 #define GD32_TIMER2_PRMP GD32_REMAP(0U, 10U, 0x3U, 2U) 58 /** TIMER2 (full remap) */ 59 #define GD32_TIMER2_FRMP GD32_REMAP(0U, 10U, 0x3U, 3U) 60 61 /** TIMER3 (no remap) */ 62 #define GD32_TIMER3_NORMP GD32_REMAP(0U, 12U, 0x1U, 0U) 63 /** TIMER3 (remap) */ 64 #define GD32_TIMER3_RMP GD32_REMAP(0U, 12U, 0x1U, 1U) 65 66 /** CAN0 (no remap) */ 67 #define GD32_CAN0_NORMP GD32_REMAP(0U, 13U, 0x3U, 0U) 68 /** CAN0 (partial remap) */ 69 #define GD32_CAN0_PRMP GD32_REMAP(0U, 13U, 0x3U, 2U) 70 /** CAN0 (full remap) */ 71 #define GD32_CAN0_FRMP GD32_REMAP(0U, 13U, 0x3U, 3U) 72 73 /** CAN1 (no remap) */ 74 #define GD32_CAN1_NORMP GD32_REMAP(0U, 22U, 0x1U, 0U) 75 /** CAN1 (remap) */ 76 #define GD32_CAN1_RMP GD32_REMAP(0U, 22U, 0x1U, 1U) 77 78 /** SPI2 (no remap) */ 79 #define GD32_SPI2_NORMP GD32_REMAP(0U, 28U, 0x1U, 0U) 80 /** SPI2 (remap) */ 81 #define GD32_SPI2_RMP GD32_REMAP(0U, 28U, 0x1U, 1U) 82 83 /** TIMER8 (no remap) */ 84 #define GD32_TIMER8_NORMP GD32_REMAP(1U, 5U, 0x1U, 0U) 85 /** TIMER8 (remap) */ 86 #define GD32_TIMER8_RMP GD32_REMAP(1U, 5U, 0x1U, 1U) 87 88 /** TIMER9 (no remap) */ 89 #define GD32_TIMER9_NORMP GD32_REMAP(1U, 6U, 0x1U, 0U) 90 /** TIMER9 (remap) */ 91 #define GD32_TIMER9_RMP GD32_REMAP(1U, 6U, 0x1U, 1U) 92 93 /** TIMER10 (no remap) */ 94 #define GD32_TIMER10_NORMP GD32_REMAP(1U, 7U, 0x1U, 0U) 95 /** TIMER10 (remap) */ 96 #define GD32_TIMER10_RMP GD32_REMAP(1U, 7U, 0x1U, 1U) 97 98 /** TIMER12 (no remap) */ 99 #define GD32_TIMER12_NORMP GD32_REMAP(1U, 8U, 0x1U, 0U) 100 /** TIMER12 (remap) */ 101 #define GD32_TIMER12_RMP GD32_REMAP(1U, 8U, 0x1U, 1U) 102 103 /** TIMER13 (no remap) */ 104 #define GD32_TIMER13_NORMP GD32_REMAP(1U, 9U, 0x1U, 0U) 105 /** TIMER13 (remap) */ 106 #define GD32_TIMER13_RMP GD32_REMAP(1U, 9U, 0x1U, 1U) 107 108 /** CTC (no remap) */ 109 #define GD32_CTC_NORMP GD32_REMAP(1U, 11U, 0x3U, 0U) 110 /** CTC (remap) */ 111 #define GD32_CTC_PRMP GD32_REMAP(1U, 11U, 0x3U, 1U) 112 113 #endif /* GD32E103XX_AFIO_H_ */ 114
