1 /*! 2 \file gd32e10x_usart.h 3 \brief definitions for the USART 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_USART_H 39 #define GD32E10X_USART_H 40 41 #include "gd32e10x.h" 42 43 /* USARTx(x=0,1,2)/UARTx(x=3,4) definitions */ 44 #define USART1 USART_BASE /*!< USART1 base address */ 45 #define USART2 (USART_BASE+0x00000400U) /*!< USART2 base address */ 46 #define UART3 (USART_BASE+0x00000800U) /*!< UART3 base address */ 47 #define UART4 (USART_BASE+0x00000C00U) /*!< UART4 base address */ 48 #define USART0 (USART_BASE+0x0000F400U) /*!< USART0 base address */ 49 50 /* registers definitions */ 51 #define USART_STAT0(usartx) REG32((usartx) + 0x00U) /*!< USART status register 0 */ 52 #define USART_DATA(usartx) REG32((usartx) + 0x04U) /*!< USART data register */ 53 #define USART_BAUD(usartx) REG32((usartx) + 0x08U) /*!< USART baud rate register */ 54 #define USART_CTL0(usartx) REG32((usartx) + 0x0CU) /*!< USART control register 0 */ 55 #define USART_CTL1(usartx) REG32((usartx) + 0x10U) /*!< USART control register 1 */ 56 #define USART_CTL2(usartx) REG32((usartx) + 0x14U) /*!< USART control register 2 */ 57 #define USART_GP(usartx) REG32((usartx) + 0x18U) /*!< USART guard time and prescaler register */ 58 #define USART_CTL3(usartx) REG32((usartx) + 0x80U) /*!< USART control register 3 */ 59 #define USART_RT(usartx) REG32((usartx) + 0x84U) /*!< USART receiver timeout register */ 60 #define USART_STAT1(usartx) REG32((usartx) + 0x88U) /*!< USART status register 1 */ 61 #define USART_CHC(usartx) REG32((usartx) + 0xC0U) /*!< USART coherence control register */ 62 63 /* bits definitions */ 64 /* USARTx_STAT0 */ 65 #define USART_STAT0_PERR BIT(0) /*!< parity error flag */ 66 #define USART_STAT0_FERR BIT(1) /*!< frame error flag */ 67 #define USART_STAT0_NERR BIT(2) /*!< noise error flag */ 68 #define USART_STAT0_ORERR BIT(3) /*!< overrun error */ 69 #define USART_STAT0_IDLEF BIT(4) /*!< IDLE frame detected flag */ 70 #define USART_STAT0_RBNE BIT(5) /*!< read data buffer not empty */ 71 #define USART_STAT0_TC BIT(6) /*!< transmission complete */ 72 #define USART_STAT0_TBE BIT(7) /*!< transmit data buffer empty */ 73 #define USART_STAT0_LBDF BIT(8) /*!< LIN break detected flag */ 74 #define USART_STAT0_CTSF BIT(9) /*!< CTS change flag */ 75 76 /* USARTx_DATA */ 77 #define USART_DATA_DATA BITS(0,8) /*!< transmit or read data value */ 78 79 /* USARTx_BAUD */ 80 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction part of baud-rate divider */ 81 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer part of baud-rate divider */ 82 83 /* USARTx_CTL0 */ 84 #define USART_CTL0_SBKCMD BIT(0) /*!< send break command */ 85 #define USART_CTL0_RWU BIT(1) /*!< receiver wakeup from mute mode */ 86 #define USART_CTL0_REN BIT(2) /*!< receiver enable */ 87 #define USART_CTL0_TEN BIT(3) /*!< transmitter enable */ 88 #define USART_CTL0_IDLEIE BIT(4) /*!< idle line detected interrupt enable */ 89 #define USART_CTL0_RBNEIE BIT(5) /*!< read data buffer not empty interrupt and overrun error interrupt enable */ 90 #define USART_CTL0_TCIE BIT(6) /*!< transmission complete interrupt enable */ 91 #define USART_CTL0_TBEIE BIT(7) /*!< transmitter buffer empty interrupt enable */ 92 #define USART_CTL0_PERRIE BIT(8) /*!< parity error interrupt enable */ 93 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 94 #define USART_CTL0_PCEN BIT(10) /*!< parity check function enable */ 95 #define USART_CTL0_WM BIT(11) /*!< wakeup method in mute mode */ 96 #define USART_CTL0_WL BIT(12) /*!< word length */ 97 #define USART_CTL0_UEN BIT(13) /*!< USART enable */ 98 99 /* USARTx_CTL1 */ 100 #define USART_CTL1_ADDR BITS(0,3) /*!< address of USART */ 101 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 102 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detected interrupt eanble */ 103 #define USART_CTL1_CLEN BIT(8) /*!< CK length */ 104 #define USART_CTL1_CPH BIT(9) /*!< CK phase */ 105 #define USART_CTL1_CPL BIT(10) /*!< CK polarity */ 106 #define USART_CTL1_CKEN BIT(11) /*!< CK pin enable */ 107 #define USART_CTL1_STB BITS(12,13) /*!< STOP bits length */ 108 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 109 110 /* USARTx_CTL2 */ 111 #define USART_CTL2_ERRIE BIT(0) /*!< error interrupt enable */ 112 #define USART_CTL2_IREN BIT(1) /*!< IrDA mode enable */ 113 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 114 #define USART_CTL2_HDEN BIT(3) /*!< half-duplex enable */ 115 #define USART_CTL2_NKEN BIT(4) /*!< NACK enable in smartcard mode */ 116 #define USART_CTL2_SCEN BIT(5) /*!< smartcard mode enable */ 117 #define USART_CTL2_DENR BIT(6) /*!< DMA request enable for reception */ 118 #define USART_CTL2_DENT BIT(7) /*!< DMA request enable for transmission */ 119 #define USART_CTL2_RTSEN BIT(8) /*!< RTS enable */ 120 #define USART_CTL2_CTSEN BIT(9) /*!< CTS enable */ 121 #define USART_CTL2_CTSIE BIT(10) /*!< CTS interrupt enable */ 122 123 /* USARTx_GP */ 124 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 125 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 126 127 /* USARTx_CTL3 */ 128 #define USART_CTL3_RTEN BIT(0) /*!< receiver timeout enable */ 129 #define USART_CTL3_SCRTNUM BITS(1,3) /*!< smartcard auto-retry number */ 130 #define USART_CTL3_RTIE BIT(4) /*!< interrupt enable bit of receive timeout event */ 131 #define USART_CTL3_EBIE BIT(5) /*!< interrupt enable bit of end of block event */ 132 #define USART_CTL3_RINV BIT(8) /*!< RX pin level inversion */ 133 #define USART_CTL3_TINV BIT(9) /*!< TX pin level inversion */ 134 #define USART_CTL3_DINV BIT(10) /*!< data bit level inversion */ 135 #define USART_CTL3_MSBF BIT(11) /*!< most significant bit first */ 136 137 /* USARTx_RT */ 138 #define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 139 #define USART_RT_BL BITS(24,31) /*!< block length */ 140 141 /* USARTx_STAT1 */ 142 #define USART_STAT1_RTF BIT(11) /*!< receiver timeout flag */ 143 #define USART_STAT1_EBF BIT(12) /*!< end of block flag */ 144 #define USART_STAT1_BSY BIT(16) /*!< busy flag */ 145 146 /* USARTx_CHC */ 147 #define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ 148 #define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ 149 150 /* constants definitions */ 151 /* define the USART bit position and its register index offset */ 152 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 153 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) 154 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 155 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 156 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 157 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 158 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) 159 160 /* register offset */ 161 #define USART_STAT0_REG_OFFSET 0x00U /*!< STAT0 register offset */ 162 #define USART_STAT1_REG_OFFSET 0x88U /*!< STAT1 register offset */ 163 #define USART_CTL0_REG_OFFSET 0x0CU /*!< CTL0 register offset */ 164 #define USART_CTL1_REG_OFFSET 0x10U /*!< CTL1 register offset */ 165 #define USART_CTL2_REG_OFFSET 0x14U /*!< CTL2 register offset */ 166 #define USART_CTL3_REG_OFFSET 0x80U /*!< CTL3 register offset */ 167 #define USART_CHC_REG_OFFSET 0xC0U /*!< CHC register offset */ 168 169 /* USART flags */ 170 typedef enum 171 { 172 /* flags in STAT0 register */ 173 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 9U), /*!< CTS change flag */ 174 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected flag */ 175 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 176 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete */ 177 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty */ 178 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 4U), /*!< IDLE frame detected flag */ 179 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 3U), /*!< overrun error */ 180 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 2U), /*!< noise error flag */ 181 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 1U), /*!< frame error flag */ 182 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT0_REG_OFFSET, 0U), /*!< parity error flag */ 183 /* flags in STAT1 register */ 184 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 16U), /*!< busy flag */ 185 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 12U), /*!< end of block flag */ 186 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT1_REG_OFFSET, 11U), /*!< receiver timeout flag */ 187 /* flags in CHC register */ 188 USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ 189 }usart_flag_enum; 190 191 /* USART interrupt flags */ 192 typedef enum 193 { 194 /* interrupt flags in CTL0 register */ 195 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT0_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 196 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 197 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 198 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 199 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT0_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 200 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 201 /* interrupt flags in CTL1 register */ 202 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT0_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 203 /* interrupt flags in CTL2 register */ 204 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT0_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 205 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 206 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 207 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT0_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 208 /* interrupt flags in CTL3 register */ 209 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 5U, USART_STAT1_REG_OFFSET, 12U), /*!< interrupt enable bit of end of block event and flag */ 210 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL3_REG_OFFSET, 4U, USART_STAT1_REG_OFFSET, 11U), /*!< interrupt enable bit of receive timeout event and flag */ 211 }usart_interrupt_flag_enum; 212 213 /* USART interrupt enable or disable */ 214 typedef enum 215 { 216 /* interrupt in CTL0 register */ 217 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 218 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 219 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 220 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 221 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 222 /* interrupt in CTL1 register */ 223 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 224 /* interrupt in CTL2 register */ 225 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 226 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 227 /* interrupt in CTL3 register */ 228 USART_INT_EB = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 5U), /*!< end of block interrupt */ 229 USART_INT_RT = USART_REGIDX_BIT(USART_CTL3_REG_OFFSET, 4U), /*!< receive timeout interrupt */ 230 }usart_interrupt_enum; 231 232 /* USART invert configure */ 233 typedef enum 234 { 235 /* data bit level inversion */ 236 USART_DINV_ENABLE, /*!< data bit level inversion */ 237 USART_DINV_DISABLE, /*!< data bit level not inversion */ 238 /* TX pin level inversion */ 239 USART_TXPIN_ENABLE, /*!< TX pin level inversion */ 240 USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 241 /* RX pin level inversion */ 242 USART_RXPIN_ENABLE, /*!< RX pin level inversion */ 243 USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 244 }usart_invert_enum; 245 246 /* USART receiver configure */ 247 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 248 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 249 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 250 251 /* USART transmitter configure */ 252 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 253 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 254 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 255 256 /* USART parity bits definitions */ 257 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 258 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 259 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 260 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 261 262 /* USART wakeup method in mute mode */ 263 #define CTL0_WM(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 264 #define USART_WM_IDLE CTL0_WM(0) /*!< idle line */ 265 #define USART_WM_ADDR CTL0_WM(1) /*!< address match */ 266 267 /* USART word length definitions */ 268 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 269 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 270 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 271 272 /* USART stop bits definitions */ 273 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 274 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 275 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 276 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 277 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 278 279 /* USART LIN break frame length */ 280 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 281 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits */ 282 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits */ 283 284 /* USART CK length */ 285 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 286 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< there are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame */ 287 #define USART_CLEN_EN CTL1_CLEN(1) /*!< there are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame */ 288 289 /* USART clock phase */ 290 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 291 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 292 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 293 294 /* USART clock polarity */ 295 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 296 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 297 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 298 299 /* USART DMA request for receive configure */ 300 #define CLT2_DENR(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 301 #define USART_DENR_ENABLE CLT2_DENR(1) /*!< DMA request enable for reception */ 302 #define USART_DENR_DISABLE CLT2_DENR(0) /*!< DMA request disable for reception */ 303 304 /* USART DMA request for transmission configure */ 305 #define CLT2_DENT(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 306 #define USART_DENT_ENABLE CLT2_DENT(1) /*!< DMA request enable for transmission */ 307 #define USART_DENT_DISABLE CLT2_DENT(0) /*!< DMA request disable for transmission */ 308 309 /* USART RTS configure */ 310 #define CLT2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 311 #define USART_RTS_ENABLE CLT2_RTSEN(1) /*!< RTS enable */ 312 #define USART_RTS_DISABLE CLT2_RTSEN(0) /*!< RTS disable */ 313 314 /* USART CTS configure */ 315 #define CLT2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 316 #define USART_CTS_ENABLE CLT2_CTSEN(1) /*!< CTS enable */ 317 #define USART_CTS_DISABLE CLT2_CTSEN(0) /*!< CTS disable */ 318 319 /* USART IrDA low-power enable */ 320 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 321 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 322 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 323 324 /* USART data is transmitted/received with the LSB/MSB first */ 325 #define USART_MSBF_LSB ((uint32_t)0x00000000U) /*!< LSB first */ 326 #define USART_MSBF_MSB USART_CTL3_MSBF /*!< MSB first */ 327 328 /* USART hardware flow control coherence mode */ 329 #define USART_RTS_NONE_COHERENCE ((uint32_t)0x00000000U) /*!< nRTS signal equals to the RBNE bit in USART_STAT0 */ 330 #define USART_RTS_COHERENCE USART_CHC_HCM /*!< nRTS signal is set when the last data bit has been sampled */ 331 332 /* function declarations */ 333 /* initialization functions */ 334 /* reset USART */ 335 void usart_deinit(uint32_t usart_periph); 336 /* configure USART baud rate value */ 337 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 338 /* configure USART parity function */ 339 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 340 /* configure USART word length */ 341 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 342 /* configure USART stop bit length */ 343 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 344 /* enable USART */ 345 void usart_enable(uint32_t usart_periph); 346 /* disable USART */ 347 void usart_disable(uint32_t usart_periph); 348 /* configure USART transmitter */ 349 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 350 /* configure USART receiver */ 351 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 352 353 /* USART normal mode communication */ 354 /* data is transmitted/received with the LSB/MSB first */ 355 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); 356 /* configure USART inverted */ 357 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); 358 /* enable receiver timeout */ 359 void usart_receiver_timeout_enable(uint32_t usart_periph); 360 /* disable receiver timeout */ 361 void usart_receiver_timeout_disable(uint32_t usart_periph); 362 /* configure receiver timeout threshold */ 363 void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); 364 /* USART transmit data function */ 365 void usart_data_transmit(uint32_t usart_periph, uint32_t data); 366 /* USART receive data function */ 367 uint16_t usart_data_receive(uint32_t usart_periph); 368 369 /* multi-processor communication */ 370 /* configure address of the USART */ 371 void usart_address_config(uint32_t usart_periph, uint8_t addr); 372 /* enable mute mode */ 373 void usart_mute_mode_enable(uint32_t usart_periph); 374 /* disable mute mode */ 375 void usart_mute_mode_disable(uint32_t usart_periph); 376 /* configure wakeup method in mute mode */ 377 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); 378 379 /* LIN mode communication */ 380 /* enable LIN mode */ 381 void usart_lin_mode_enable(uint32_t usart_periph); 382 /* disable LIN mode */ 383 void usart_lin_mode_disable(uint32_t usart_periph); 384 /* LIN break detection length */ 385 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 386 /* send break frame */ 387 void usart_send_break(uint32_t usart_periph); 388 389 /* half-duplex communication */ 390 /* enable half-duplex mode */ 391 void usart_halfduplex_enable(uint32_t usart_periph); 392 /* disable half-duplex mode */ 393 void usart_halfduplex_disable(uint32_t usart_periph); 394 395 /* synchronous communication */ 396 /* enable CK pin in synchronous mode */ 397 void usart_synchronous_clock_enable(uint32_t usart_periph); 398 /* disable CK pin in synchronous mode */ 399 void usart_synchronous_clock_disable(uint32_t usart_periph); 400 /* configure usart synchronous mode parameters */ 401 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 402 403 /* smartcard communication */ 404 /* configure guard time value in smartcard mode */ 405 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); 406 /* enable smartcard mode */ 407 void usart_smartcard_mode_enable(uint32_t usart_periph); 408 /* disable smartcard mode */ 409 void usart_smartcard_mode_disable(uint32_t usart_periph); 410 /* enable NACK in smartcard mode */ 411 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 412 /* disable NACK in smartcard mode */ 413 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 414 /* configure smartcard auto-retry number */ 415 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); 416 /* configure block length */ 417 void usart_block_length_config(uint32_t usart_periph, uint32_t bl); 418 419 /* IrDA communication */ 420 /* enable IrDA mode */ 421 void usart_irda_mode_enable(uint32_t usart_periph); 422 /* disable IrDA mode */ 423 void usart_irda_mode_disable(uint32_t usart_periph); 424 /* configure the peripheral clock prescaler */ 425 void usart_prescaler_config(uint32_t usart_periph, uint8_t psc); 426 /* configure IrDA low-power */ 427 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 428 429 /* hardware flow communication */ 430 /* configure hardware flow control RTS */ 431 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 432 /* configure hardware flow control CTS */ 433 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 434 435 /* DMA communication */ 436 /* configure USART DMA for reception */ 437 void usart_dma_receive_config(uint32_t usart_periph, uint32_t dmacmd); 438 /* configure USART DMA for transmission */ 439 void usart_dma_transmit_config(uint32_t usart_periph, uint32_t dmacmd); 440 441 /* coherence control */ 442 /* configure hardware flow control coherence mode */ 443 void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); 444 445 /* flag & interrupt functions */ 446 /* get flag in STAT0/STAT1 register */ 447 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 448 /* clear flag in STAT0/STAT1 register */ 449 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 450 /* enable USART interrupt */ 451 void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); 452 /* disable USART interrupt */ 453 void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); 454 /* get USART interrupt and flag status */ 455 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 456 /* clear interrupt flag in STAT0/STAT1 register */ 457 void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 458 459 #endif /* GD32E10X_USART_H */ 460
