1 /*! 2 \file gd32e10x_timer.h 3 \brief definitions for the TIMER 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_TIMER_H 39 #define GD32E10X_TIMER_H 40 41 #include "gd32e10x.h" 42 43 /* TIMERx(x=0..13) definitions */ 44 #define TIMER0 (TIMER_BASE + 0x00012C00U) 45 #define TIMER1 (TIMER_BASE + 0x00000000U) 46 #define TIMER2 (TIMER_BASE + 0x00000400U) 47 #define TIMER3 (TIMER_BASE + 0x00000800U) 48 #define TIMER4 (TIMER_BASE + 0x00000C00U) 49 #define TIMER5 (TIMER_BASE + 0x00001000U) 50 #define TIMER6 (TIMER_BASE + 0x00001400U) 51 #define TIMER7 (TIMER_BASE + 0x00013400U) 52 #define TIMER8 (TIMER_BASE + 0x00014C00U) 53 #define TIMER9 (TIMER_BASE + 0x00015000U) 54 #define TIMER10 (TIMER_BASE + 0x00015400U) 55 #define TIMER11 (TIMER_BASE + 0x00001800U) 56 #define TIMER12 (TIMER_BASE + 0x00001C00U) 57 #define TIMER13 (TIMER_BASE + 0x00002000U) 58 59 /* registers definitions */ 60 #define TIMER_CTL0(timerx) REG32((timerx) + 0x00U) /*!< TIMER control register 0 */ 61 #define TIMER_CTL1(timerx) REG32((timerx) + 0x04U) /*!< TIMER control register 1 */ 62 #define TIMER_SMCFG(timerx) REG32((timerx) + 0x08U) /*!< TIMER slave mode configuration register */ 63 #define TIMER_DMAINTEN(timerx) REG32((timerx) + 0x0CU) /*!< TIMER DMA and interrupt enable register */ 64 #define TIMER_INTF(timerx) REG32((timerx) + 0x10U) /*!< TIMER interrupt flag register */ 65 #define TIMER_SWEVG(timerx) REG32((timerx) + 0x14U) /*!< TIMER software event generation register */ 66 #define TIMER_CHCTL0(timerx) REG32((timerx) + 0x18U) /*!< TIMER channel control register 0 */ 67 #define TIMER_CHCTL1(timerx) REG32((timerx) + 0x1CU) /*!< TIMER channel control register 1 */ 68 #define TIMER_CHCTL2(timerx) REG32((timerx) + 0x20U) /*!< TIMER channel control register 2 */ 69 #define TIMER_CNT(timerx) REG32((timerx) + 0x24U) /*!< TIMER counter register */ 70 #define TIMER_PSC(timerx) REG32((timerx) + 0x28U) /*!< TIMER prescaler register */ 71 #define TIMER_CAR(timerx) REG32((timerx) + 0x2CU) /*!< TIMER counter auto reload register */ 72 #define TIMER_CREP(timerx) REG32((timerx) + 0x30U) /*!< TIMER counter repetition register */ 73 #define TIMER_CH0CV(timerx) REG32((timerx) + 0x34U) /*!< TIMER channel 0 capture/compare value register */ 74 #define TIMER_CH1CV(timerx) REG32((timerx) + 0x38U) /*!< TIMER channel 1 capture/compare value register */ 75 #define TIMER_CH2CV(timerx) REG32((timerx) + 0x3CU) /*!< TIMER channel 2 capture/compare value register */ 76 #define TIMER_CH3CV(timerx) REG32((timerx) + 0x40U) /*!< TIMER channel 3 capture/compare value register */ 77 #define TIMER_CCHP(timerx) REG32((timerx) + 0x44U) /*!< TIMER channel complementary protection register */ 78 #define TIMER_DMACFG(timerx) REG32((timerx) + 0x48U) /*!< TIMER DMA configuration register */ 79 #define TIMER_DMATB(timerx) REG32((timerx) + 0x4CU) /*!< TIMER DMA transfer buffer register */ 80 #define TIMER_CFG(timerx) REG32((timerx) + 0xFCU) /*!< TIMER configuration register */ 81 82 /* bits definitions */ 83 /* TIMER_CTL0 */ 84 #define TIMER_CTL0_CEN BIT(0) /*!< TIMER counter enable */ 85 #define TIMER_CTL0_UPDIS BIT(1) /*!< update disable */ 86 #define TIMER_CTL0_UPS BIT(2) /*!< update source */ 87 #define TIMER_CTL0_SPM BIT(3) /*!< single pulse mode */ 88 #define TIMER_CTL0_DIR BIT(4) /*!< timer counter direction */ 89 #define TIMER_CTL0_CAM BITS(5,6) /*!< center-aligned mode selection */ 90 #define TIMER_CTL0_ARSE BIT(7) /*!< auto-reload shadow enable */ 91 #define TIMER_CTL0_CKDIV BITS(8,9) /*!< clock division */ 92 93 /* TIMER_CTL1 */ 94 #define TIMER_CTL1_CCSE BIT(0) /*!< commutation control shadow enable */ 95 #define TIMER_CTL1_CCUC BIT(2) /*!< commutation control shadow register update control */ 96 #define TIMER_CTL1_DMAS BIT(3) /*!< DMA request source selection */ 97 #define TIMER_CTL1_MMC BITS(4,6) /*!< master mode control */ 98 #define TIMER_CTL1_TI0S BIT(7) /*!< channel 0 trigger input selection(hall mode selection) */ 99 #define TIMER_CTL1_ISO0 BIT(8) /*!< idle state of channel 0 output */ 100 #define TIMER_CTL1_ISO0N BIT(9) /*!< idle state of channel 0 complementary output */ 101 #define TIMER_CTL1_ISO1 BIT(10) /*!< idle state of channel 1 output */ 102 #define TIMER_CTL1_ISO1N BIT(11) /*!< idle state of channel 1 complementary output */ 103 #define TIMER_CTL1_ISO2 BIT(12) /*!< idle state of channel 2 output */ 104 #define TIMER_CTL1_ISO2N BIT(13) /*!< idle state of channel 2 complementary output */ 105 #define TIMER_CTL1_ISO3 BIT(14) /*!< idle state of channel 3 output */ 106 107 /* TIMER_SMCFG */ 108 #define TIMER_SMCFG_SMC BITS(0,2) /*!< slave mode control */ 109 #define TIMER_SMCFG_TRGS BITS(4,6) /*!< trigger selection */ 110 #define TIMER_SMCFG_MSM BIT(7) /*!< master-slave mode */ 111 #define TIMER_SMCFG_ETFC BITS(8,11) /*!< external trigger filter control */ 112 #define TIMER_SMCFG_ETPSC BITS(12,13) /*!< external trigger prescaler */ 113 #define TIMER_SMCFG_SMC1 BIT(14) /*!< part of SMC for enable external clock mode 1 */ 114 #define TIMER_SMCFG_ETP BIT(15) /*!< external trigger polarity */ 115 116 /* TIMER_DMAINTEN */ 117 #define TIMER_DMAINTEN_UPIE BIT(0) /*!< update interrupt enable */ 118 #define TIMER_DMAINTEN_CH0IE BIT(1) /*!< channel 0 capture/compare interrupt enable */ 119 #define TIMER_DMAINTEN_CH1IE BIT(2) /*!< channel 1 capture/compare interrupt enable */ 120 #define TIMER_DMAINTEN_CH2IE BIT(3) /*!< channel 2 capture/compare interrupt enable */ 121 #define TIMER_DMAINTEN_CH3IE BIT(4) /*!< channel 3 capture/compare interrupt enable */ 122 #define TIMER_DMAINTEN_CMTIE BIT(5) /*!< commutation interrupt request enable */ 123 #define TIMER_DMAINTEN_TRGIE BIT(6) /*!< trigger interrupt enable */ 124 #define TIMER_DMAINTEN_BRKIE BIT(7) /*!< break interrupt enable */ 125 #define TIMER_DMAINTEN_UPDEN BIT(8) /*!< update DMA request enable */ 126 #define TIMER_DMAINTEN_CH0DEN BIT(9) /*!< channel 0 capture/compare DMA request enable */ 127 #define TIMER_DMAINTEN_CH1DEN BIT(10) /*!< channel 1 capture/compare DMA request enable */ 128 #define TIMER_DMAINTEN_CH2DEN BIT(11) /*!< channel 2 capture/compare DMA request enable */ 129 #define TIMER_DMAINTEN_CH3DEN BIT(12) /*!< channel 3 capture/compare DMA request enable */ 130 #define TIMER_DMAINTEN_CMTDEN BIT(13) /*!< commutation DMA request enable */ 131 #define TIMER_DMAINTEN_TRGDEN BIT(14) /*!< trigger DMA request enable */ 132 133 /* TIMER_INTF */ 134 #define TIMER_INTF_UPIF BIT(0) /*!< update interrupt flag */ 135 #define TIMER_INTF_CH0IF BIT(1) /*!< channel 0 capture/compare interrupt flag */ 136 #define TIMER_INTF_CH1IF BIT(2) /*!< channel 1 capture/compare interrupt flag */ 137 #define TIMER_INTF_CH2IF BIT(3) /*!< channel 2 capture/compare interrupt flag */ 138 #define TIMER_INTF_CH3IF BIT(4) /*!< channel 3 capture/compare interrupt flag */ 139 #define TIMER_INTF_CMTIF BIT(5) /*!< channel commutation interrupt flag */ 140 #define TIMER_INTF_TRGIF BIT(6) /*!< trigger interrupt flag */ 141 #define TIMER_INTF_BRKIF BIT(7) /*!< break interrupt flag */ 142 #define TIMER_INTF_CH0OF BIT(9) /*!< channel 0 over capture flag */ 143 #define TIMER_INTF_CH1OF BIT(10) /*!< channel 1 over capture flag */ 144 #define TIMER_INTF_CH2OF BIT(11) /*!< channel 2 over capture flag */ 145 #define TIMER_INTF_CH3OF BIT(12) /*!< channel 3 over capture flag */ 146 147 /* TIMER_SWEVG */ 148 #define TIMER_SWEVG_UPG BIT(0) /*!< update event generate */ 149 #define TIMER_SWEVG_CH0G BIT(1) /*!< channel 0 capture or compare event generation */ 150 #define TIMER_SWEVG_CH1G BIT(2) /*!< channel 1 capture or compare event generation */ 151 #define TIMER_SWEVG_CH2G BIT(3) /*!< channel 2 capture or compare event generation */ 152 #define TIMER_SWEVG_CH3G BIT(4) /*!< channel 3 capture or compare event generation */ 153 #define TIMER_SWEVG_CMTG BIT(5) /*!< channel commutation event generation */ 154 #define TIMER_SWEVG_TRGG BIT(6) /*!< trigger event generation */ 155 #define TIMER_SWEVG_BRKG BIT(7) /*!< break event generation */ 156 157 /* TIMER_CHCTL0 */ 158 /* output compare mode */ 159 #define TIMER_CHCTL0_CH0MS BITS(0,1) /*!< channel 0 mode selection */ 160 #define TIMER_CHCTL0_CH0COMFEN BIT(2) /*!< channel 0 output compare fast enable */ 161 #define TIMER_CHCTL0_CH0COMSEN BIT(3) /*!< channel 0 output compare shadow enable */ 162 #define TIMER_CHCTL0_CH0COMCTL BITS(4,6) /*!< channel 0 output compare control */ 163 #define TIMER_CHCTL0_CH0COMCEN BIT(7) /*!< channel 0 output compare clear enable */ 164 #define TIMER_CHCTL0_CH1MS BITS(8,9) /*!< channel 1 mode selection */ 165 #define TIMER_CHCTL0_CH1COMFEN BIT(10) /*!< channel 1 output compare fast enable */ 166 #define TIMER_CHCTL0_CH1COMSEN BIT(11) /*!< channel 1 output compare shadow enable */ 167 #define TIMER_CHCTL0_CH1COMCTL BITS(12,14) /*!< channel 1 output compare control */ 168 #define TIMER_CHCTL0_CH1COMCEN BIT(15) /*!< channel 1 output compare clear enable */ 169 /* input capture mode */ 170 #define TIMER_CHCTL0_CH0CAPPSC BITS(2,3) /*!< channel 0 input capture prescaler */ 171 #define TIMER_CHCTL0_CH0CAPFLT BITS(4,7) /*!< channel 0 input capture filter control */ 172 #define TIMER_CHCTL0_CH1CAPPSC BITS(10,11) /*!< channel 1 input capture prescaler */ 173 #define TIMER_CHCTL0_CH1CAPFLT BITS(12,15) /*!< channel 1 input capture filter control */ 174 175 /* TIMER_CHCTL1 */ 176 /* output compare mode */ 177 #define TIMER_CHCTL1_CH2MS BITS(0,1) /*!< channel 2 mode selection */ 178 #define TIMER_CHCTL1_CH2COMFEN BIT(2) /*!< channel 2 output compare fast enable */ 179 #define TIMER_CHCTL1_CH2COMSEN BIT(3) /*!< channel 2 output compare shadow enable */ 180 #define TIMER_CHCTL1_CH2COMCTL BITS(4,6) /*!< channel 2 output compare control */ 181 #define TIMER_CHCTL1_CH2COMCEN BIT(7) /*!< channel 2 output compare clear enable */ 182 #define TIMER_CHCTL1_CH3MS BITS(8,9) /*!< channel 3 mode selection */ 183 #define TIMER_CHCTL1_CH3COMFEN BIT(10) /*!< channel 3 output compare fast enable */ 184 #define TIMER_CHCTL1_CH3COMSEN BIT(11) /*!< channel 3 output compare shadow enable */ 185 #define TIMER_CHCTL1_CH3COMCTL BITS(12,14) /*!< channel 3 output compare control */ 186 #define TIMER_CHCTL1_CH3COMCEN BIT(15) /*!< channel 3 output compare clear enable */ 187 /* input capture mode */ 188 #define TIMER_CHCTL1_CH2CAPPSC BITS(2,3) /*!< channel 2 input capture prescaler */ 189 #define TIMER_CHCTL1_CH2CAPFLT BITS(4,7) /*!< channel 2 input capture filter control */ 190 #define TIMER_CHCTL1_CH3CAPPSC BITS(10,11) /*!< channel 3 input capture prescaler */ 191 #define TIMER_CHCTL1_CH3CAPFLT BITS(12,15) /*!< channel 3 input capture filter control */ 192 193 /* TIMER_CHCTL2 */ 194 #define TIMER_CHCTL2_CH0EN BIT(0) /*!< channel 0 capture/compare function enable */ 195 #define TIMER_CHCTL2_CH0P BIT(1) /*!< channel 0 capture/compare function polarity */ 196 #define TIMER_CHCTL2_CH0NEN BIT(2) /*!< channel 0 complementary output enable */ 197 #define TIMER_CHCTL2_CH0NP BIT(3) /*!< channel 0 complementary output polarity */ 198 #define TIMER_CHCTL2_CH1EN BIT(4) /*!< channel 1 capture/compare function enable */ 199 #define TIMER_CHCTL2_CH1P BIT(5) /*!< channel 1 capture/compare function polarity */ 200 #define TIMER_CHCTL2_CH1NEN BIT(6) /*!< channel 1 complementary output enable */ 201 #define TIMER_CHCTL2_CH1NP BIT(7) /*!< channel 1 complementary output polarity */ 202 #define TIMER_CHCTL2_CH2EN BIT(8) /*!< channel 2 capture/compare function enable */ 203 #define TIMER_CHCTL2_CH2P BIT(9) /*!< channel 2 capture/compare function polarity */ 204 #define TIMER_CHCTL2_CH2NEN BIT(10) /*!< channel 2 complementary output enable */ 205 #define TIMER_CHCTL2_CH2NP BIT(11) /*!< channel 2 complementary output polarity */ 206 #define TIMER_CHCTL2_CH3EN BIT(12) /*!< channel 3 capture/compare function enable */ 207 #define TIMER_CHCTL2_CH3P BIT(13) /*!< channel 3 capture/compare function polarity */ 208 209 /* TIMER_CNT */ 210 #define TIMER_CNT_CNT BITS(0,15) /*!< 16 bit timer counter */ 211 212 /* TIMER_PSC */ 213 #define TIMER_PSC_PSC BITS(0,15) /*!< prescaler value of the counter clock */ 214 215 /* TIMER_CAR */ 216 #define TIMER_CAR_CARL BITS(0,15) /*!< 16 bit counter auto reload value */ 217 218 /* TIMER_CREP */ 219 #define TIMER_CREP_CREP BITS(0,7) /*!< counter repetition value */ 220 221 /* TIMER_CH0CV */ 222 #define TIMER_CH0CV_CH0VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 0 */ 223 224 /* TIMER_CH1CV */ 225 #define TIMER_CH1CV_CH1VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 1 */ 226 227 /* TIMER_CH2CV */ 228 #define TIMER_CH2CV_CH2VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 2 */ 229 230 /* TIMER_CH3CV */ 231 #define TIMER_CH3CV_CH3VAL BITS(0,15) /*!< 16 bit capture/compare value of channel 3 */ 232 233 /* TIMER_CCHP */ 234 #define TIMER_CCHP_DTCFG BITS(0,7) /*!< dead time configure */ 235 #define TIMER_CCHP_PROT BITS(8,9) /*!< complementary register protect control */ 236 #define TIMER_CCHP_IOS BIT(10) /*!< idle mode off-state configure */ 237 #define TIMER_CCHP_ROS BIT(11) /*!< run mode off-state configure */ 238 #define TIMER_CCHP_BRKEN BIT(12) /*!< break enable */ 239 #define TIMER_CCHP_BRKP BIT(13) /*!< break polarity */ 240 #define TIMER_CCHP_OAEN BIT(14) /*!< output automatic enable */ 241 #define TIMER_CCHP_POEN BIT(15) /*!< primary output enable */ 242 243 /* TIMER_DMACFG */ 244 #define TIMER_DMACFG_DMATA BITS(0,4) /*!< DMA transfer access start address */ 245 #define TIMER_DMACFG_DMATC BITS(8,12) /*!< DMA transfer count */ 246 247 /* TIMER_DMATB */ 248 #define TIMER_DMATB_DMATB BITS(0,15) /*!< DMA transfer buffer address */ 249 250 /* TIMER_CFG */ 251 #define TIMER_CFG_OUTSEL BIT(0) /*!< the output value selection */ 252 #define TIMER_CFG_CHVSEL BIT(1) /*!< write CHxVAL register selection */ 253 254 /* constants definitions */ 255 /* TIMER init parameter struct definitions */ 256 typedef struct 257 { 258 uint16_t prescaler; /*!< prescaler value */ 259 uint16_t alignedmode; /*!< aligned mode */ 260 uint16_t counterdirection; /*!< counter direction */ 261 uint32_t period; /*!< period value */ 262 uint16_t clockdivision; /*!< clock division value */ 263 uint8_t repetitioncounter; /*!< the counter repetition value */ 264 }timer_parameter_struct; 265 266 /* break parameter struct definitions */ 267 typedef struct 268 { 269 uint16_t runoffstate; /*!< run mode off-state */ 270 uint16_t ideloffstate; /*!< idle mode off-state */ 271 uint16_t deadtime; /*!< dead time */ 272 uint16_t breakpolarity; /*!< break polarity */ 273 uint16_t outputautostate; /*!< output automatic enable */ 274 uint16_t protectmode; /*!< complementary register protect control */ 275 uint16_t breakstate; /*!< break enable */ 276 }timer_break_parameter_struct; 277 278 /* channel output parameter struct definitions */ 279 typedef struct 280 { 281 uint16_t outputstate; /*!< channel output state */ 282 uint16_t outputnstate; /*!< channel complementary output state */ 283 uint16_t ocpolarity; /*!< channel output polarity */ 284 uint16_t ocnpolarity; /*!< channel complementary output polarity */ 285 uint16_t ocidlestate; /*!< idle state of channel output */ 286 uint16_t ocnidlestate; /*!< idle state of channel complementary output */ 287 }timer_oc_parameter_struct; 288 289 /* channel input parameter struct definitions */ 290 typedef struct 291 { 292 uint16_t icpolarity; /*!< channel input polarity */ 293 uint16_t icselection; /*!< channel input mode selection */ 294 uint16_t icprescaler; /*!< channel input capture prescaler */ 295 uint16_t icfilter; /*!< channel input capture filter control */ 296 }timer_ic_parameter_struct; 297 298 /* TIMER interrupt enable or disable */ 299 #define TIMER_INT_UP TIMER_DMAINTEN_UPIE /*!< update interrupt */ 300 #define TIMER_INT_CH0 TIMER_DMAINTEN_CH0IE /*!< channel 0 interrupt */ 301 #define TIMER_INT_CH1 TIMER_DMAINTEN_CH1IE /*!< channel 1 interrupt */ 302 #define TIMER_INT_CH2 TIMER_DMAINTEN_CH2IE /*!< channel 2 interrupt */ 303 #define TIMER_INT_CH3 TIMER_DMAINTEN_CH3IE /*!< channel 3 interrupt */ 304 #define TIMER_INT_CMT TIMER_DMAINTEN_CMTIE /*!< channel commutation interrupt flag */ 305 #define TIMER_INT_TRG TIMER_DMAINTEN_TRGIE /*!< trigger interrupt */ 306 #define TIMER_INT_BRK TIMER_DMAINTEN_BRKIE /*!< break interrupt */ 307 308 /* TIMER interrupt flag */ 309 #define TIMER_INT_FLAG_UP TIMER_INT_UP /*!< update interrupt */ 310 #define TIMER_INT_FLAG_CH0 TIMER_INT_CH0 /*!< channel 0 interrupt */ 311 #define TIMER_INT_FLAG_CH1 TIMER_INT_CH1 /*!< channel 1 interrupt */ 312 #define TIMER_INT_FLAG_CH2 TIMER_INT_CH2 /*!< channel 2 interrupt */ 313 #define TIMER_INT_FLAG_CH3 TIMER_INT_CH3 /*!< channel 3 interrupt */ 314 #define TIMER_INT_FLAG_CMT TIMER_INT_CMT /*!< channel commutation interrupt flag */ 315 #define TIMER_INT_FLAG_TRG TIMER_INT_TRG /*!< trigger interrupt */ 316 #define TIMER_INT_FLAG_BRK TIMER_INT_BRK 317 318 /* TIMER flag */ 319 #define TIMER_FLAG_UP TIMER_INTF_UPIF /*!< update flag */ 320 #define TIMER_FLAG_CH0 TIMER_INTF_CH0IF /*!< channel 0 flag */ 321 #define TIMER_FLAG_CH1 TIMER_INTF_CH1IF /*!< channel 1 flag */ 322 #define TIMER_FLAG_CH2 TIMER_INTF_CH2IF /*!< channel 2 flag */ 323 #define TIMER_FLAG_CH3 TIMER_INTF_CH3IF /*!< channel 3 flag */ 324 #define TIMER_FLAG_CMT TIMER_INTF_CMTIF /*!< channel control update flag */ 325 #define TIMER_FLAG_TRG TIMER_INTF_TRGIF /*!< trigger flag */ 326 #define TIMER_FLAG_BRK TIMER_INTF_BRKIF /*!< break flag */ 327 #define TIMER_FLAG_CH0O TIMER_INTF_CH0OF /*!< channel 0 overcapture flag */ 328 #define TIMER_FLAG_CH1O TIMER_INTF_CH1OF /*!< channel 1 overcapture flag */ 329 #define TIMER_FLAG_CH2O TIMER_INTF_CH2OF /*!< channel 2 overcapture flag */ 330 #define TIMER_FLAG_CH3O TIMER_INTF_CH3OF /*!< channel 3 overcapture flag */ 331 332 /* TIMER DMA source enable */ 333 #define TIMER_DMA_UPD ((uint16_t)TIMER_DMAINTEN_UPDEN) /*!< update DMA enable */ 334 #define TIMER_DMA_CH0D ((uint16_t)TIMER_DMAINTEN_CH0DEN) /*!< channel 0 DMA enable */ 335 #define TIMER_DMA_CH1D ((uint16_t)TIMER_DMAINTEN_CH1DEN) /*!< channel 1 DMA enable */ 336 #define TIMER_DMA_CH2D ((uint16_t)TIMER_DMAINTEN_CH2DEN) /*!< channel 2 DMA enable */ 337 #define TIMER_DMA_CH3D ((uint16_t)TIMER_DMAINTEN_CH3DEN) /*!< channel 3 DMA enable */ 338 #define TIMER_DMA_CMTD ((uint16_t)TIMER_DMAINTEN_CMTDEN) /*!< commutation DMA request enable */ 339 #define TIMER_DMA_TRGD ((uint16_t)TIMER_DMAINTEN_TRGDEN) /*!< trigger DMA enable */ 340 341 /* channel DMA request source selection */ 342 #define TIMER_DMAREQUEST_UPDATEEVENT TIMER_CTL1_DMAS /*!< DMA request of channel n is sent when update event occurs */ 343 #define TIMER_DMAREQUEST_CHANNELEVENT ((uint32_t)0x00000000U) /*!< DMA request of channel n is sent when channel n event occurs */ 344 345 /* DMA access base address */ 346 #define DMACFG_DMATA(regval) (BITS(0, 4) & ((uint32_t)(regval) << 0U)) 347 #define TIMER_DMACFG_DMATA_CTL0 DMACFG_DMATA(0) /*!< DMA transfer address is TIMER_CTL0 */ 348 #define TIMER_DMACFG_DMATA_CTL1 DMACFG_DMATA(1) /*!< DMA transfer address is TIMER_CTL1 */ 349 #define TIMER_DMACFG_DMATA_SMCFG DMACFG_DMATA(2) /*!< DMA transfer address is TIMER_SMCFG */ 350 #define TIMER_DMACFG_DMATA_DMAINTEN DMACFG_DMATA(3) /*!< DMA transfer address is TIMER_DMAINTEN */ 351 #define TIMER_DMACFG_DMATA_INTF DMACFG_DMATA(4) /*!< DMA transfer address is TIMER_INTF */ 352 #define TIMER_DMACFG_DMATA_SWEVG DMACFG_DMATA(5) /*!< DMA transfer address is TIMER_SWEVG */ 353 #define TIMER_DMACFG_DMATA_CHCTL0 DMACFG_DMATA(6) /*!< DMA transfer address is TIMER_CHCTL0 */ 354 #define TIMER_DMACFG_DMATA_CHCTL1 DMACFG_DMATA(7) /*!< DMA transfer address is TIMER_CHCTL1 */ 355 #define TIMER_DMACFG_DMATA_CHCTL2 DMACFG_DMATA(8) /*!< DMA transfer address is TIMER_CHCTL2 */ 356 #define TIMER_DMACFG_DMATA_CNT DMACFG_DMATA(9) /*!< DMA transfer address is TIMER_CNT */ 357 #define TIMER_DMACFG_DMATA_PSC DMACFG_DMATA(10) /*!< DMA transfer address is TIMER_PSC */ 358 #define TIMER_DMACFG_DMATA_CAR DMACFG_DMATA(11) /*!< DMA transfer address is TIMER_CAR */ 359 #define TIMER_DMACFG_DMATA_CREP DMACFG_DMATA(12) /*!< DMA transfer address is TIMER_CREP */ 360 #define TIMER_DMACFG_DMATA_CH0CV DMACFG_DMATA(13) /*!< DMA transfer address is TIMER_CH0CV */ 361 #define TIMER_DMACFG_DMATA_CH1CV DMACFG_DMATA(14) /*!< DMA transfer address is TIMER_CH1CV */ 362 #define TIMER_DMACFG_DMATA_CH2CV DMACFG_DMATA(15) /*!< DMA transfer address is TIMER_CH2CV */ 363 #define TIMER_DMACFG_DMATA_CH3CV DMACFG_DMATA(16) /*!< DMA transfer address is TIMER_CH3CV */ 364 #define TIMER_DMACFG_DMATA_CCHP DMACFG_DMATA(17) /*!< DMA transfer address is TIMER_CCHP */ 365 #define TIMER_DMACFG_DMATA_DMACFG DMACFG_DMATA(18) /*!< DMA transfer address is TIMER_DMACFG */ 366 367 /* DMA access burst length */ 368 #define DMACFG_DMATC(regval) (BITS(8, 12) & ((uint32_t)(regval) << 8U)) 369 #define TIMER_DMACFG_DMATC_1TRANSFER DMACFG_DMATC(0) /*!< DMA transfer 1 time */ 370 #define TIMER_DMACFG_DMATC_2TRANSFER DMACFG_DMATC(1) /*!< DMA transfer 2 times */ 371 #define TIMER_DMACFG_DMATC_3TRANSFER DMACFG_DMATC(2) /*!< DMA transfer 3 times */ 372 #define TIMER_DMACFG_DMATC_4TRANSFER DMACFG_DMATC(3) /*!< DMA transfer 4 times */ 373 #define TIMER_DMACFG_DMATC_5TRANSFER DMACFG_DMATC(4) /*!< DMA transfer 5 times */ 374 #define TIMER_DMACFG_DMATC_6TRANSFER DMACFG_DMATC(5) /*!< DMA transfer 6 times */ 375 #define TIMER_DMACFG_DMATC_7TRANSFER DMACFG_DMATC(6) /*!< DMA transfer 7 times */ 376 #define TIMER_DMACFG_DMATC_8TRANSFER DMACFG_DMATC(7) /*!< DMA transfer 8 times */ 377 #define TIMER_DMACFG_DMATC_9TRANSFER DMACFG_DMATC(8) /*!< DMA transfer 9 times */ 378 #define TIMER_DMACFG_DMATC_10TRANSFER DMACFG_DMATC(9) /*!< DMA transfer 10 times */ 379 #define TIMER_DMACFG_DMATC_11TRANSFER DMACFG_DMATC(10) /*!< DMA transfer 11 times */ 380 #define TIMER_DMACFG_DMATC_12TRANSFER DMACFG_DMATC(11) /*!< DMA transfer 12 times */ 381 #define TIMER_DMACFG_DMATC_13TRANSFER DMACFG_DMATC(12) /*!< DMA transfer 13 times */ 382 #define TIMER_DMACFG_DMATC_14TRANSFER DMACFG_DMATC(13) /*!< DMA transfer 14 times */ 383 #define TIMER_DMACFG_DMATC_15TRANSFER DMACFG_DMATC(14) /*!< DMA transfer 15 times */ 384 #define TIMER_DMACFG_DMATC_16TRANSFER DMACFG_DMATC(15) /*!< DMA transfer 16 times */ 385 #define TIMER_DMACFG_DMATC_17TRANSFER DMACFG_DMATC(16) /*!< DMA transfer 17 times */ 386 #define TIMER_DMACFG_DMATC_18TRANSFER DMACFG_DMATC(17) /*!< DMA transfer 18 times */ 387 388 /* TIMER software event generation source */ 389 #define TIMER_EVENT_SRC_UPG ((uint16_t)0x0001U) /*!< update event generation */ 390 #define TIMER_EVENT_SRC_CH0G ((uint16_t)0x0002U) /*!< channel 0 capture or compare event generation */ 391 #define TIMER_EVENT_SRC_CH1G ((uint16_t)0x0004U) /*!< channel 1 capture or compare event generation */ 392 #define TIMER_EVENT_SRC_CH2G ((uint16_t)0x0008U) /*!< channel 2 capture or compare event generation */ 393 #define TIMER_EVENT_SRC_CH3G ((uint16_t)0x0010U) /*!< channel 3 capture or compare event generation */ 394 #define TIMER_EVENT_SRC_CMTG ((uint16_t)0x0020U) /*!< channel commutation event generation */ 395 #define TIMER_EVENT_SRC_TRGG ((uint16_t)0x0040U) /*!< trigger event generation */ 396 #define TIMER_EVENT_SRC_BRKG ((uint16_t)0x0080U) /*!< break event generation */ 397 398 /* center-aligned mode selection */ 399 #define CTL0_CAM(regval) ((uint16_t)(BITS(5, 6) & ((uint32_t)(regval) << 5U))) 400 #define TIMER_COUNTER_EDGE CTL0_CAM(0) /*!< edge-aligned mode */ 401 #define TIMER_COUNTER_CENTER_DOWN CTL0_CAM(1) /*!< center-aligned and counting down assert mode */ 402 #define TIMER_COUNTER_CENTER_UP CTL0_CAM(2) /*!< center-aligned and counting up assert mode */ 403 #define TIMER_COUNTER_CENTER_BOTH CTL0_CAM(3) /*!< center-aligned and counting up/down assert mode */ 404 405 /* TIMER prescaler reload mode */ 406 #define TIMER_PSC_RELOAD_NOW TIMER_SWEVG_UPG /*!< the prescaler is loaded right now */ 407 #define TIMER_PSC_RELOAD_UPDATE ((uint32_t)0x00000000U) /*!< the prescaler is loaded at the next update event */ 408 409 /* count direction */ 410 #define TIMER_COUNTER_UP ((uint16_t)0x0000U) /*!< counter up direction */ 411 #define TIMER_COUNTER_DOWN ((uint16_t)TIMER_CTL0_DIR) /*!< counter down direction */ 412 413 /* specify division ratio between TIMER clock and dead-time and sampling clock */ 414 #define CTL0_CKDIV(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) 415 #define TIMER_CKDIV_DIV1 CTL0_CKDIV(0) /*!< clock division value is 1,fDTS=fTIMER_CK */ 416 #define TIMER_CKDIV_DIV2 CTL0_CKDIV(1) /*!< clock division value is 2,fDTS= fTIMER_CK/2 */ 417 #define TIMER_CKDIV_DIV4 CTL0_CKDIV(2) /*!< clock division value is 4, fDTS= fTIMER_CK/4 */ 418 419 /* single pulse mode */ 420 #define TIMER_SP_MODE_SINGLE TIMER_CTL0_SPM /*!< single pulse mode */ 421 #define TIMER_SP_MODE_REPETITIVE ((uint32_t)0x00000000U) /*!< repetitive pulse mode */ 422 423 /* update source */ 424 #define TIMER_UPDATE_SRC_REGULAR TIMER_CTL0_UPS /*!< update generate only by counter overflow/underflow */ 425 #define TIMER_UPDATE_SRC_GLOBAL ((uint32_t)0x00000000U) /*!< update generate by setting of UPG bit or the counter overflow/underflow,or the slave mode controller trigger */ 426 427 /* run mode off-state configure */ 428 #define TIMER_ROS_STATE_ENABLE ((uint16_t)TIMER_CCHP_ROS) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ 429 #define TIMER_ROS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is set, the channel output signals(CHx_O/CHx_ON) are disabled */ 430 431 432 /* idle mode off-state configure */ 433 #define TIMER_IOS_STATE_ENABLE ((uint16_t)TIMER_CCHP_IOS) /*!< when POEN bit is reset, he channel output signals(CHx_O/CHx_ON) are enabled, with relationship to CHxEN/CHxNEN bits */ 434 #define TIMER_IOS_STATE_DISABLE ((uint16_t)0x0000U) /*!< when POEN bit is reset, the channel output signals(CHx_O/CHx_ON) are disabled */ 435 436 /* break input polarity */ 437 #define TIMER_BREAK_POLARITY_LOW ((uint16_t)0x0000U) /*!< break input polarity is low */ 438 #define TIMER_BREAK_POLARITY_HIGH ((uint16_t)TIMER_CCHP_BRKP) /*!< break input polarity is high */ 439 440 /* output automatic enable */ 441 #define TIMER_OUTAUTO_ENABLE ((uint16_t)TIMER_CCHP_OAEN) /*!< output automatic enable */ 442 #define TIMER_OUTAUTO_DISABLE ((uint16_t)0x0000U) /*!< output automatic disable */ 443 444 /* complementary register protect control */ 445 #define CCHP_PROT(regval) ((uint16_t)(BITS(8, 9) & ((uint32_t)(regval) << 8U))) 446 #define TIMER_CCHP_PROT_OFF CCHP_PROT(0) /*!< protect disable */ 447 #define TIMER_CCHP_PROT_0 CCHP_PROT(1) /*!< PROT mode 0 */ 448 #define TIMER_CCHP_PROT_1 CCHP_PROT(2) /*!< PROT mode 1 */ 449 #define TIMER_CCHP_PROT_2 CCHP_PROT(3) /*!< PROT mode 2 */ 450 451 /* break input enable */ 452 #define TIMER_BREAK_ENABLE ((uint16_t)TIMER_CCHP_BRKEN) /*!< break input enable */ 453 #define TIMER_BREAK_DISABLE ((uint16_t)0x0000U) /*!< break input disable */ 454 455 /* TIMER channel n(n=0,1,2,3) */ 456 #define TIMER_CH_0 ((uint16_t)0x0000U) /*!< TIMER channel 0(TIMERx(x=0..4,7..13)) */ 457 #define TIMER_CH_1 ((uint16_t)0x0001U) /*!< TIMER channel 1(TIMERx(x=0..4,7,8,11)) */ 458 #define TIMER_CH_2 ((uint16_t)0x0002U) /*!< TIMER channel 2(TIMERx(x=0..4,7)) */ 459 #define TIMER_CH_3 ((uint16_t)0x0003U) /*!< TIMER channel 3(TIMERx(x=0..4,7)) */ 460 461 /* channel enable state */ 462 #define TIMER_CCX_ENABLE ((uint16_t)0x0001U) /*!< channel enable */ 463 #define TIMER_CCX_DISABLE ((uint16_t)0x0000U) /*!< channel disable */ 464 465 /* channel complementary output enable state */ 466 #define TIMER_CCXN_ENABLE ((uint16_t)0x0004U) /*!< channel complementary enable */ 467 #define TIMER_CCXN_DISABLE ((uint16_t)0x0000U) /*!< channel complementary disable */ 468 469 /* channel output polarity */ 470 #define TIMER_OC_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel output polarity is high */ 471 #define TIMER_OC_POLARITY_LOW ((uint16_t)0x0002U) /*!< channel output polarity is low */ 472 473 /* channel complementary output polarity */ 474 #define TIMER_OCN_POLARITY_HIGH ((uint16_t)0x0000U) /*!< channel complementary output polarity is high */ 475 #define TIMER_OCN_POLARITY_LOW ((uint16_t)0x0008U) /*!< channel complementary output polarity is low */ 476 477 /* idle state of channel output */ 478 #define TIMER_OC_IDLE_STATE_HIGH ((uint16_t)0x0100) /*!< idle state of channel output is high */ 479 #define TIMER_OC_IDLE_STATE_LOW ((uint16_t)0x0000) /*!< idle state of channel output is low */ 480 481 /* idle state of channel complementary output */ 482 #define TIMER_OCN_IDLE_STATE_HIGH ((uint16_t)0x0200U) /*!< idle state of channel complementary output is high */ 483 #define TIMER_OCN_IDLE_STATE_LOW ((uint16_t)0x0000U) /*!< idle state of channel complementary output is low */ 484 485 /* channel output compare mode */ 486 #define TIMER_OC_MODE_TIMING ((uint16_t)0x0000U) /*!< timing mode */ 487 #define TIMER_OC_MODE_ACTIVE ((uint16_t)0x0010U) /*!< active mode */ 488 #define TIMER_OC_MODE_INACTIVE ((uint16_t)0x0020U) /*!< inactive mode */ 489 #define TIMER_OC_MODE_TOGGLE ((uint16_t)0x0030U) /*!< toggle mode */ 490 #define TIMER_OC_MODE_LOW ((uint16_t)0x0040U) /*!< force low mode */ 491 #define TIMER_OC_MODE_HIGH ((uint16_t)0x0050U) /*!< force high mode */ 492 #define TIMER_OC_MODE_PWM0 ((uint16_t)0x0060U) /*!< PWM0 mode */ 493 #define TIMER_OC_MODE_PWM1 ((uint16_t)0x0070U) /*!< PWM1 mode */ 494 495 /* channel output compare shadow enable */ 496 #define TIMER_OC_SHADOW_ENABLE ((uint16_t)0x0008U) /*!< channel output shadow state enable */ 497 #define TIMER_OC_SHADOW_DISABLE ((uint16_t)0x0000U) /*!< channel output shadow state disable */ 498 499 /* channel output compare fast enable */ 500 #define TIMER_OC_FAST_ENABLE ((uint16_t)0x0004) /*!< channel output fast function enable */ 501 #define TIMER_OC_FAST_DISABLE ((uint16_t)0x0000) /*!< channel output fast function disable */ 502 503 /* channel output compare clear enable */ 504 #define TIMER_OC_CLEAR_ENABLE ((uint16_t)0x0080U) /*!< channel output clear function enable */ 505 #define TIMER_OC_CLEAR_DISABLE ((uint16_t)0x0000U) /*!< channel output clear function disable */ 506 507 /* channel control shadow register update control */ 508 #define TIMER_UPDATECTL_CCU ((uint32_t)0x00000000U) /*!< the shadow registers update by when CMTG bit is set */ 509 #define TIMER_UPDATECTL_CCUTRI TIMER_CTL1_CCUC /*!< the shadow registers update by when CMTG bit is set or an rising edge of TRGI occurs */ 510 511 /* channel input capture polarity */ 512 #define TIMER_IC_POLARITY_RISING ((uint16_t)0x0000U) /*!< input capture rising edge */ 513 #define TIMER_IC_POLARITY_FALLING ((uint16_t)0x0002U) /*!< input capture falling edge */ 514 #define TIMER_IC_POLARITY_BOTH_EDGE ((uint16_t)0x000AU) /*!< input capture both edge(only for TIMER8~TIMER13) */ 515 516 /* TIMER input capture selection */ 517 #define TIMER_IC_SELECTION_DIRECTTI ((uint16_t)0x0001U) /*!< channel n is configured as input and icy is mapped on CIy */ 518 #define TIMER_IC_SELECTION_INDIRECTTI ((uint16_t)0x0002U) /*!< channel n is configured as input and icy is mapped on opposite input */ 519 #define TIMER_IC_SELECTION_ITS ((uint16_t)0x0003U) /*!< channel n is configured as input and icy is mapped on ITS */ 520 521 /* channel input capture prescaler */ 522 #define TIMER_IC_PSC_DIV1 ((uint16_t)0x0000U) /*!< no prescaler */ 523 #define TIMER_IC_PSC_DIV2 ((uint16_t)0x0004U) /*!< divided by 2 */ 524 #define TIMER_IC_PSC_DIV4 ((uint16_t)0x0008U) /*!< divided by 4 */ 525 #define TIMER_IC_PSC_DIV8 ((uint16_t)0x000CU) /*!< divided by 8 */ 526 527 /* trigger selection */ 528 #define SMCFG_TRGSEL(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) 529 #define TIMER_SMCFG_TRGSEL_ITI0 SMCFG_TRGSEL(0) /*!< internal trigger 0 */ 530 #define TIMER_SMCFG_TRGSEL_ITI1 SMCFG_TRGSEL(1) /*!< internal trigger 1 */ 531 #define TIMER_SMCFG_TRGSEL_ITI2 SMCFG_TRGSEL(2) /*!< internal trigger 2 */ 532 #define TIMER_SMCFG_TRGSEL_ITI3 SMCFG_TRGSEL(3) /*!< internal trigger 3 */ 533 #define TIMER_SMCFG_TRGSEL_CI0F_ED SMCFG_TRGSEL(4) /*!< TI0 Edge Detector */ 534 #define TIMER_SMCFG_TRGSEL_CI0FE0 SMCFG_TRGSEL(5) /*!< filtered TIMER input 0 */ 535 #define TIMER_SMCFG_TRGSEL_CI1FE1 SMCFG_TRGSEL(6) /*!< filtered TIMER input 1 */ 536 #define TIMER_SMCFG_TRGSEL_ETIFP SMCFG_TRGSEL(7) /*!< filtered external trigger input */ 537 538 /* master mode control */ 539 #define CTL1_MMC(regval) (BITS(4, 6) & ((uint32_t)(regval) << 4U)) 540 #define TIMER_TRI_OUT_SRC_RESET CTL1_MMC(0) /*!< the UPG bit as trigger output */ 541 #define TIMER_TRI_OUT_SRC_ENABLE CTL1_MMC(1) /*!< the counter enable signal TIMER_CTL0_CEN as trigger output */ 542 #define TIMER_TRI_OUT_SRC_UPDATE CTL1_MMC(2) /*!< update event as trigger output */ 543 #define TIMER_TRI_OUT_SRC_CH0 CTL1_MMC(3) /*!< a capture or a compare match occurred in channel 0 as trigger output TRGO */ 544 #define TIMER_TRI_OUT_SRC_O0CPRE CTL1_MMC(4) /*!< O0CPRE as trigger output */ 545 #define TIMER_TRI_OUT_SRC_O1CPRE CTL1_MMC(5) /*!< O1CPRE as trigger output */ 546 #define TIMER_TRI_OUT_SRC_O2CPRE CTL1_MMC(6) /*!< O2CPRE as trigger output */ 547 #define TIMER_TRI_OUT_SRC_O3CPRE CTL1_MMC(7) /*!< O3CPRE as trigger output */ 548 549 /* slave mode control */ 550 #define SMCFG_SMC(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0U)) 551 #define TIMER_SLAVE_MODE_DISABLE SMCFG_SMC(0) /*!< slave mode disable */ 552 #define TIMER_ENCODER_MODE0 SMCFG_SMC(1) /*!< encoder mode 0 */ 553 #define TIMER_ENCODER_MODE1 SMCFG_SMC(2) /*!< encoder mode 1 */ 554 #define TIMER_ENCODER_MODE2 SMCFG_SMC(3) /*!< encoder mode 2 */ 555 #define TIMER_SLAVE_MODE_RESTART SMCFG_SMC(4) /*!< restart mode */ 556 #define TIMER_SLAVE_MODE_PAUSE SMCFG_SMC(5) /*!< pause mode */ 557 #define TIMER_SLAVE_MODE_EVENT SMCFG_SMC(6) /*!< event mode */ 558 #define TIMER_SLAVE_MODE_EXTERNAL0 SMCFG_SMC(7) /*!< external clock mode 0 */ 559 560 /* master slave mode selection */ 561 #define TIMER_MASTER_SLAVE_MODE_ENABLE TIMER_SMCFG_MSM /*!< master slave mode enable */ 562 #define TIMER_MASTER_SLAVE_MODE_DISABLE ((uint32_t)0x00000000U) /*!< master slave mode disable */ 563 564 /* external trigger prescaler */ 565 #define SMCFG_ETPSC(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12U)) 566 #define TIMER_EXT_TRI_PSC_OFF SMCFG_ETPSC(0) /*!< no divided */ 567 #define TIMER_EXT_TRI_PSC_DIV2 SMCFG_ETPSC(1) /*!< divided by 2 */ 568 #define TIMER_EXT_TRI_PSC_DIV4 SMCFG_ETPSC(2) /*!< divided by 4 */ 569 #define TIMER_EXT_TRI_PSC_DIV8 SMCFG_ETPSC(3) /*!< divided by 8 */ 570 571 /* external trigger polarity */ 572 #define TIMER_ETP_FALLING TIMER_SMCFG_ETP /*!< active low or falling edge active */ 573 #define TIMER_ETP_RISING ((uint32_t)0x00000000U) /*!< active high or rising edge active */ 574 575 /* channel 0 trigger input selection */ 576 #define TIMER_HALLINTERFACE_ENABLE TIMER_CTL1_TI0S /*!< TIMER hall sensor mode enable */ 577 #define TIMER_HALLINTERFACE_DISABLE ((uint32_t)0x00000000U) /*!< TIMER hall sensor mode disable */ 578 579 /* TIMERx(x=0..4,7..13) write CHxVAL register selection */ 580 #define TIMER_CHVSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< write CHxVAL register selection enable */ 581 #define TIMER_CHVSEL_DISABLE ((uint16_t)0x0000U) /*!< write CHxVAL register selection disable */ 582 583 /* TIMERx(x=0,7) output value selection */ 584 #define TIMER_OUTSEL_ENABLE ((uint16_t)TIMER_CFG_OUTSEL) /*!< output value selection enable */ 585 #define TIMER_OUTSEL_DISABLE ((uint16_t)0x0000U) /*!< output value selection disable */ 586 587 /* function declarations */ 588 /* TIMER timebase */ 589 /* deinit a timer */ 590 void timer_deinit(uint32_t timer_periph); 591 /* initialize TIMER init parameter struct */ 592 void timer_struct_para_init(timer_parameter_struct* initpara); 593 /* initialize TIMER counter */ 594 void gd32_timer_init(uint32_t timer_periph, timer_parameter_struct* initpara); 595 /* enable a timer */ 596 void timer_enable(uint32_t timer_periph); 597 /* disable a timer */ 598 void timer_disable(uint32_t timer_periph); 599 /* enable the auto reload shadow function */ 600 void timer_auto_reload_shadow_enable(uint32_t timer_periph); 601 /* disable the auto reload shadow function */ 602 void timer_auto_reload_shadow_disable(uint32_t timer_periph); 603 /* enable the update event */ 604 void timer_update_event_enable(uint32_t timer_periph); 605 /* disable the update event */ 606 void timer_update_event_disable(uint32_t timer_periph); 607 /* set TIMER counter alignment mode */ 608 void timer_counter_alignment(uint32_t timer_periph, uint16_t aligned); 609 /* set TIMER counter up direction */ 610 void timer_counter_up_direction(uint32_t timer_periph); 611 /* set TIMER counter down direction */ 612 void timer_counter_down_direction(uint32_t timer_periph); 613 614 /* configure TIMER prescaler */ 615 void timer_prescaler_config(uint32_t timer_periph, uint16_t prescaler, uint32_t pscreload); 616 /* configure TIMER repetition register value */ 617 void timer_repetition_value_config(uint32_t timer_periph, uint16_t repetition); 618 /* configure TIMER autoreload register value */ 619 void timer_autoreload_value_config(uint32_t timer_periph, uint16_t autoreload); 620 /* configure TIMER counter register value */ 621 void timer_counter_value_config(uint32_t timer_periph, uint16_t counter); 622 /* read TIMER counter value */ 623 uint32_t timer_counter_read(uint32_t timer_periph); 624 /* read TIMER prescaler value */ 625 uint16_t timer_prescaler_read(uint32_t timer_periph); 626 /* configure TIMER single pulse mode */ 627 void timer_single_pulse_mode_config(uint32_t timer_periph, uint32_t spmode); 628 /* configure TIMER update source */ 629 void timer_update_source_config(uint32_t timer_periph, uint32_t update); 630 631 /* TIMER DMA and event */ 632 /* enable the TIMER DMA */ 633 void timer_dma_enable(uint32_t timer_periph, uint16_t dma); 634 /* disable the TIMER DMA */ 635 void timer_dma_disable(uint32_t timer_periph, uint16_t dma); 636 /* channel DMA request source selection */ 637 void timer_channel_dma_request_source_select(uint32_t timer_periph, uint32_t dma_request); 638 /* configure the TIMER DMA transfer */ 639 void timer_dma_transfer_config(uint32_t timer_periph, uint32_t dma_baseaddr, uint32_t dma_lenth); 640 /* software generate events */ 641 void timer_event_software_generate(uint32_t timer_periph, uint16_t event); 642 643 /* TIMER channel complementary protection */ 644 /* initialize TIMER break parameter struct */ 645 void timer_break_struct_para_init(timer_break_parameter_struct* breakpara); 646 /* configure TIMER break function */ 647 void timer_break_config(uint32_t timer_periph, timer_break_parameter_struct* breakpara); 648 /* enable TIMER break function */ 649 void timer_break_enable(uint32_t timer_periph); 650 /* disable TIMER break function */ 651 void timer_break_disable(uint32_t timer_periph); 652 /* enable TIMER output automatic function */ 653 void timer_automatic_output_enable(uint32_t timer_periph); 654 /* disable TIMER output automatic function */ 655 void timer_automatic_output_disable(uint32_t timer_periph); 656 /* enable or disable TIMER primary output function */ 657 void timer_primary_output_config(uint32_t timer_periph, ControlStatus newvalue); 658 /* enable or disable channel capture/compare control shadow register */ 659 void timer_channel_control_shadow_config(uint32_t timer_periph, ControlStatus newvalue); 660 /* configure TIMER channel control shadow register update control */ 661 void timer_channel_control_shadow_update_config(uint32_t timer_periph, uint32_t ccuctl); 662 663 /* TIMER channel output */ 664 /* initialize TIMER channel output parameter struct */ 665 void timer_channel_output_struct_para_init(timer_oc_parameter_struct* ocpara); 666 /* configure TIMER channel output function */ 667 void timer_channel_output_config(uint32_t timer_periph, uint16_t channel, timer_oc_parameter_struct* ocpara); 668 /* configure TIMER channel output compare mode */ 669 void timer_channel_output_mode_config(uint32_t timer_periph, uint16_t channel, uint16_t ocmode); 670 /* configure TIMER channel output pulse value */ 671 void timer_channel_output_pulse_value_config(uint32_t timer_periph, uint16_t channel, uint32_t pulse); 672 /* configure TIMER channel output shadow function */ 673 void timer_channel_output_shadow_config(uint32_t timer_periph, uint16_t channel, uint16_t ocshadow); 674 /* configure TIMER channel output fast function */ 675 void timer_channel_output_fast_config(uint32_t timer_periph, uint16_t channel, uint16_t ocfast); 676 /* configure TIMER channel output clear function */ 677 void timer_channel_output_clear_config(uint32_t timer_periph, uint16_t channel, uint16_t occlear); 678 /* configure TIMER channel output polarity */ 679 void timer_channel_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocpolarity); 680 /* configure TIMER channel complementary output polarity */ 681 void timer_channel_complementary_output_polarity_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnpolarity); 682 /* configure TIMER channel enable state */ 683 void timer_channel_output_state_config(uint32_t timer_periph, uint16_t channel, uint32_t state); 684 /* configure TIMER channel complementary output enable state */ 685 void timer_channel_complementary_output_state_config(uint32_t timer_periph, uint16_t channel, uint16_t ocnstate); 686 687 /* TIMER channel input */ 688 /* initialize TIMER channel input parameter struct */ 689 void timer_channel_input_struct_para_init(timer_ic_parameter_struct* icpara); 690 /* configure TIMER input capture parameter */ 691 void timer_input_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpara); 692 /* configure TIMER channel input capture prescaler value */ 693 void timer_channel_input_capture_prescaler_config(uint32_t timer_periph, uint16_t channel, uint16_t prescaler); 694 /* read TIMER channel capture compare register value */ 695 uint32_t timer_channel_capture_value_register_read(uint32_t timer_periph, uint16_t channel); 696 /* configure TIMER input pwm capture function */ 697 void timer_input_pwm_capture_config(uint32_t timer_periph, uint16_t channel, timer_ic_parameter_struct* icpwm); 698 /* configure TIMER hall sensor mode */ 699 void timer_hall_mode_config(uint32_t timer_periph, uint32_t hallmode); 700 701 /* TIMER master and slave mode */ 702 /* select TIMER input trigger source */ 703 void timer_input_trigger_source_select(uint32_t timer_periph, uint32_t intrigger); 704 /* select TIMER master mode output trigger source */ 705 void timer_master_output_trigger_source_select(uint32_t timer_periph, uint32_t outrigger); 706 /* select TIMER slave mode */ 707 void timer_slave_mode_select(uint32_t timer_periph, uint32_t slavemode); 708 /* configure TIMER master slave mode */ 709 void timer_master_slave_mode_config(uint32_t timer_periph, uint32_t masterslave); 710 /* configure TIMER external trigger input */ 711 void timer_external_trigger_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 712 /* configure TIMER quadrature decoder mode */ 713 void timer_quadrature_decoder_mode_config(uint32_t timer_periph, uint32_t decomode, uint16_t ic0polarity, uint16_t ic1polarity); 714 /* configure TIMER internal clock mode */ 715 void timer_internal_clock_config(uint32_t timer_periph); 716 /* configure TIMER the internal trigger as external clock input */ 717 void timer_internal_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t intrigger); 718 /* configure TIMER the external trigger as external clock input */ 719 void timer_external_trigger_as_external_clock_config(uint32_t timer_periph, uint32_t extrigger, uint16_t extpolarity, uint32_t extfilter); 720 /* configure TIMER the external clock mode 0 */ 721 void timer_external_clock_mode0_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 722 /* configure TIMER the external clock mode 1 */ 723 void timer_external_clock_mode1_config(uint32_t timer_periph, uint32_t extprescaler, uint32_t extpolarity, uint32_t extfilter); 724 /* disable TIMER the external clock mode 1 */ 725 void timer_external_clock_mode1_disable(uint32_t timer_periph); 726 727 /* TIMER configure */ 728 /* configure TIMER write CHxVAL register selection */ 729 void timer_write_chxval_register_config(uint32_t timer_periph, uint16_t ccsel); 730 /* configure TIMER output value selection */ 731 void timer_output_value_selection_config(uint32_t timer_periph, uint16_t outsel); 732 733 /* TIMER interrupt and flag */ 734 /* enable the TIMER interrupt */ 735 void timer_interrupt_enable(uint32_t timer_periph, uint32_t interrupt); 736 /* disable the TIMER interrupt */ 737 void timer_interrupt_disable(uint32_t timer_periph, uint32_t interrupt); 738 /* get TIMER interrupt flag */ 739 FlagStatus timer_interrupt_flag_get(uint32_t timer_periph, uint32_t interrupt); 740 /* clear TIMER interrupt flag */ 741 void timer_interrupt_flag_clear(uint32_t timer_periph, uint32_t interrupt); 742 /* get TIMER flag */ 743 FlagStatus timer_flag_get(uint32_t timer_periph, uint32_t flag); 744 /* clear TIMER flag */ 745 void timer_flag_clear(uint32_t timer_periph, uint32_t flag); 746 747 #endif /* GD32E10X_TIMER_H */ 748
