1 /*! 2 \file gd32e10x_spi.h 3 \brief definitions for the SPI 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2021-05-31, V1.2.1, firmware for GD32E10x 9 \version 2022-06-16, V1.2.2, firmware for GD32E10x 10 \version 2022-06-30, V1.3.0, firmware for GD32E10x 11 */ 12 13 /* 14 Copyright (c) 2022, GigaDevice Semiconductor Inc. 15 16 Redistribution and use in source and binary forms, with or without modification, 17 are permitted provided that the following conditions are met: 18 19 1. Redistributions of source code must retain the above copyright notice, this 20 list of conditions and the following disclaimer. 21 2. Redistributions in binary form must reproduce the above copyright notice, 22 this list of conditions and the following disclaimer in the documentation 23 and/or other materials provided with the distribution. 24 3. Neither the name of the copyright holder nor the names of its contributors 25 may be used to endorse or promote products derived from this software without 26 specific prior written permission. 27 28 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 29 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 30 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 32 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 33 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 34 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 35 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 37 OF SUCH DAMAGE. 38 */ 39 40 #ifndef GD32E10X_SPI_H 41 #define GD32E10X_SPI_H 42 43 #include "gd32e10x.h" 44 45 /* SPIx(x=0,1,2) definitions */ 46 #define SPI0 (SPI_BASE + 0x0000F800U) 47 #define SPI1 SPI_BASE 48 #define SPI2 (SPI_BASE + 0x00000400U) 49 50 /* SPI registers definitions */ 51 #define SPI_CTL0(spix) REG32((spix) + 0x00U) /*!< SPI control register 0 */ 52 #define SPI_CTL1(spix) REG32((spix) + 0x04U) /*!< SPI control register 1*/ 53 #define SPI_STAT(spix) REG32((spix) + 0x08U) /*!< SPI status register */ 54 #define SPI_DATA(spix) REG32((spix) + 0x0CU) /*!< SPI data register */ 55 #define SPI_CRCPOLY(spix) REG32((spix) + 0x10U) /*!< SPI CRC polynomial register */ 56 #define SPI_RCRC(spix) REG32((spix) + 0x14U) /*!< SPI receive CRC register */ 57 #define SPI_TCRC(spix) REG32((spix) + 0x18U) /*!< SPI transmit CRC register */ 58 #define SPI_I2SCTL(spix) REG32((spix) + 0x1CU) /*!< SPI I2S control register */ 59 #define SPI_I2SPSC(spix) REG32((spix) + 0x20U) /*!< SPI I2S clock prescaler register */ 60 #define SPI_QCTL(spix) REG32((spix) + 0x80U) /*!< SPI quad mode control register(only SPI0) */ 61 62 /* bits definitions */ 63 /* SPI_CTL0 */ 64 #define SPI_CTL0_CKPH BIT(0) /*!< clock phase selection*/ 65 #define SPI_CTL0_CKPL BIT(1) /*!< clock polarity selection */ 66 #define SPI_CTL0_MSTMOD BIT(2) /*!< master mode enable */ 67 #define SPI_CTL0_PSC BITS(3,5) /*!< master clock prescaler selection */ 68 #define SPI_CTL0_SPIEN BIT(6) /*!< SPI enable*/ 69 #define SPI_CTL0_LF BIT(7) /*!< LSB first mode */ 70 #define SPI_CTL0_SWNSS BIT(8) /*!< NSS pin selection in NSS software mode */ 71 #define SPI_CTL0_SWNSSEN BIT(9) /*!< NSS software mode selection */ 72 #define SPI_CTL0_RO BIT(10) /*!< receive only */ 73 #define SPI_CTL0_FF16 BIT(11) /*!< data frame size */ 74 #define SPI_CTL0_CRCNT BIT(12) /*!< CRC next transfer */ 75 #define SPI_CTL0_CRCEN BIT(13) /*!< CRC calculation enable */ 76 #define SPI_CTL0_BDOEN BIT(14) /*!< bidirectional transmit output enable*/ 77 #define SPI_CTL0_BDEN BIT(15) /*!< bidirectional enable */ 78 79 /* SPI_CTL1 */ 80 #define SPI_CTL1_DMAREN BIT(0) /*!< receive buffer dma enable */ 81 #define SPI_CTL1_DMATEN BIT(1) /*!< transmit buffer dma enable */ 82 #define SPI_CTL1_NSSDRV BIT(2) /*!< drive NSS output */ 83 #define SPI_CTL1_NSSP BIT(3) /*!< SPI NSS pulse mode enable */ 84 #define SPI_CTL1_TMOD BIT(4) /*!< SPI TI mode enable */ 85 #define SPI_CTL1_ERRIE BIT(5) /*!< errors interrupt enable */ 86 #define SPI_CTL1_RBNEIE BIT(6) /*!< receive buffer not empty interrupt enable */ 87 #define SPI_CTL1_TBEIE BIT(7) /*!< transmit buffer empty interrupt enable */ 88 89 /* SPI_STAT */ 90 #define SPI_STAT_RBNE BIT(0) /*!< receive buffer not empty */ 91 #define SPI_STAT_TBE BIT(1) /*!< transmit buffer empty */ 92 #define SPI_STAT_I2SCH BIT(2) /*!< I2S channel side */ 93 #define SPI_STAT_TXURERR BIT(3) /*!< I2S transmission underrun error bit */ 94 #define SPI_STAT_CRCERR BIT(4) /*!< SPI CRC error bit */ 95 #define SPI_STAT_CONFERR BIT(5) /*!< SPI configuration error bit */ 96 #define SPI_STAT_RXORERR BIT(6) /*!< SPI reception overrun error bit */ 97 #define SPI_STAT_TRANS BIT(7) /*!< transmitting on-going bit */ 98 #define SPI_STAT_FERR BIT(8) /*!< format error bit */ 99 100 /* SPI_DATA */ 101 #define SPI_DATA_DATA BITS(0,15) /*!< data transfer register */ 102 103 /* SPI_CRCPOLY */ 104 #define SPI_CRCPOLY_CRCPOLY BITS(0,15) /*!< CRC polynomial value */ 105 106 /* SPI_RCRC */ 107 #define SPI_RCRC_RCRC BITS(0,15) /*!< RX CRC value */ 108 109 /* SPI_TCRC */ 110 #define SPI_TCRC_TCRC BITS(0,15) /*!< TX CRC value */ 111 112 /* SPI_I2SCTL */ 113 #define SPI_I2SCTL_CHLEN BIT(0) /*!< channel length */ 114 #define SPI_I2SCTL_DTLEN BITS(1,2) /*!< data length */ 115 #define SPI_I2SCTL_CKPL BIT(3) /*!< idle state clock polarity */ 116 #define SPI_I2SCTL_I2SSTD BITS(4,5) /*!< I2S standard selection */ 117 #define SPI_I2SCTL_PCMSMOD BIT(7) /*!< PCM frame synchronization mode */ 118 #define SPI_I2SCTL_I2SOPMOD BITS(8,9) /*!< I2S operation mode */ 119 #define SPI_I2SCTL_I2SEN BIT(10) /*!< I2S enable */ 120 #define SPI_I2SCTL_I2SSEL BIT(11) /*!< I2S mode selection */ 121 122 /* SPI_I2SPSC */ 123 #define SPI_I2SPSC_DIV BITS(0,7) /*!< dividing factor for the prescaler */ 124 #define SPI_I2SPSC_OF BIT(8) /*!< odd factor for the prescaler */ 125 #define SPI_I2SPSC_MCKOEN BIT(9) /*!< I2S MCK output enable */ 126 127 /* SPI_QCTL(only for SPI1) */ 128 #define SPI_QCTL_QMOD BIT(0) /*!< quad-SPI mode enable */ 129 #define SPI_QCTL_QRD BIT(1) /*!< quad-SPI mode read select */ 130 #define SPI_QCTL_IO23_DRV BIT(2) /*!< drive SPI_IO2 and SPI_IO3 enable */ 131 132 /* constants definitions */ 133 /* SPI and I2S parameter struct definitions */ 134 typedef struct 135 { 136 uint32_t device_mode; /*!< SPI master or slave */ 137 uint32_t trans_mode; /*!< SPI transtype */ 138 uint32_t frame_size; /*!< SPI frame size */ 139 uint32_t nss; /*!< SPI NSS control by handware or software */ 140 uint32_t endian; /*!< SPI big endian or little endian */ 141 uint32_t clock_polarity_phase; /*!< SPI clock phase and polarity */ 142 uint32_t prescale; /*!< SPI prescale factor */ 143 }spi_parameter_struct; 144 145 /* SPI mode definitions */ 146 #define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /*!< SPI as master */ 147 #define SPI_SLAVE ((uint32_t)0x00000000U) /*!< SPI as slave */ 148 149 /* SPI bidirectional transfer direction */ 150 #define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /*!< SPI work in transmit-only mode */ 151 #define SPI_BIDIRECTIONAL_RECEIVE (~SPI_CTL0_BDOEN) /*!< SPI work in receive-only mode */ 152 153 /* SPI transmit type */ 154 #define SPI_TRANSMODE_FULLDUPLEX ((uint32_t)0x00000000U) /*!< SPI receive and send data at fullduplex communication */ 155 #define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /*!< SPI only receive data */ 156 #define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /*!< bidirectional receive data */ 157 #define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /*!< bidirectional transmit data*/ 158 159 /* SPI frame size */ 160 #define SPI_FRAMESIZE_16BIT SPI_CTL0_FF16 /*!< SPI frame size is 16 bits */ 161 #define SPI_FRAMESIZE_8BIT ((uint32_t)0x00000000U) /*!< SPI frame size is 8 bits */ 162 163 /* SPI NSS control mode */ 164 #define SPI_NSS_SOFT SPI_CTL0_SWNSSEN /*!< SPI NSS control by sofrware */ 165 #define SPI_NSS_HARD ((uint32_t)0x00000000U) /*!< SPI NSS control by hardware */ 166 167 /* SPI transmit way */ 168 #define SPI_ENDIAN_MSB ((uint32_t)0x00000000U) /*!< SPI transmit way is big endian: transmit MSB first */ 169 #define SPI_ENDIAN_LSB SPI_CTL0_LF /*!< SPI transmit way is little endian: transmit LSB first */ 170 171 /* SPI clock phase and polarity */ 172 #define SPI_CK_PL_LOW_PH_1EDGE ((uint32_t)0x00000000U) /*!< SPI clock polarity is low level and phase is first edge */ 173 #define SPI_CK_PL_HIGH_PH_1EDGE SPI_CTL0_CKPL /*!< SPI clock polarity is high level and phase is first edge */ 174 #define SPI_CK_PL_LOW_PH_2EDGE SPI_CTL0_CKPH /*!< SPI clock polarity is low level and phase is second edge */ 175 #define SPI_CK_PL_HIGH_PH_2EDGE (SPI_CTL0_CKPL | SPI_CTL0_CKPH) /*!< SPI clock polarity is high level and phase is second edge */ 176 177 /* SPI clock prescale factor */ 178 #define CTL0_PSC(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) 179 #define SPI_PSC_2 CTL0_PSC(0) /*!< SPI clock prescale factor is 2 */ 180 #define SPI_PSC_4 CTL0_PSC(1) /*!< SPI clock prescale factor is 4 */ 181 #define SPI_PSC_8 CTL0_PSC(2) /*!< SPI clock prescale factor is 8 */ 182 #define SPI_PSC_16 CTL0_PSC(3) /*!< SPI clock prescale factor is 16 */ 183 #define SPI_PSC_32 CTL0_PSC(4) /*!< SPI clock prescale factor is 32 */ 184 #define SPI_PSC_64 CTL0_PSC(5) /*!< SPI clock prescale factor is 64 */ 185 #define SPI_PSC_128 CTL0_PSC(6) /*!< SPI clock prescale factor is 128 */ 186 #define SPI_PSC_256 CTL0_PSC(7) /*!< SPI clock prescale factor is 256 */ 187 188 /* I2S audio sample rate */ 189 #define I2S_AUDIOSAMPLE_8K ((uint32_t)8000U) /*!< I2S audio sample rate is 8KHz */ 190 #define I2S_AUDIOSAMPLE_11K ((uint32_t)11025U) /*!< I2S audio sample rate is 11KHz */ 191 #define I2S_AUDIOSAMPLE_16K ((uint32_t)16000U) /*!< I2S audio sample rate is 16KHz */ 192 #define I2S_AUDIOSAMPLE_22K ((uint32_t)22050U) /*!< I2S audio sample rate is 22KHz */ 193 #define I2S_AUDIOSAMPLE_32K ((uint32_t)32000U) /*!< I2S audio sample rate is 32KHz */ 194 #define I2S_AUDIOSAMPLE_44K ((uint32_t)44100U) /*!< I2S audio sample rate is 44KHz */ 195 #define I2S_AUDIOSAMPLE_48K ((uint32_t)48000U) /*!< I2S audio sample rate is 48KHz */ 196 #define I2S_AUDIOSAMPLE_96K ((uint32_t)96000U) /*!< I2S audio sample rate is 96KHz */ 197 #define I2S_AUDIOSAMPLE_192K ((uint32_t)192000U) /*!< I2S audio sample rate is 192KHz */ 198 199 /* I2S frame format */ 200 #define I2SCTL_DTLEN(regval) (BITS(1,2) & ((uint32_t)(regval) << 1)) 201 #define I2S_FRAMEFORMAT_DT16B_CH16B I2SCTL_DTLEN(0) /*!< I2S data length is 16 bit and channel length is 16 bit */ 202 #define I2S_FRAMEFORMAT_DT16B_CH32B (I2SCTL_DTLEN(0) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 16 bit and channel length is 32 bit */ 203 #define I2S_FRAMEFORMAT_DT24B_CH32B (I2SCTL_DTLEN(1) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 24 bit and channel length is 32 bit */ 204 #define I2S_FRAMEFORMAT_DT32B_CH32B (I2SCTL_DTLEN(2) | SPI_I2SCTL_CHLEN) /*!< I2S data length is 32 bit and channel length is 32 bit */ 205 206 /* I2S master clock output */ 207 #define I2S_MCKOUT_DISABLE ((uint32_t)0x00000000U) /*!< I2S master clock output disable */ 208 #define I2S_MCKOUT_ENABLE SPI_I2SPSC_MCKOEN /*!< I2S master clock output enable */ 209 210 /* I2S operation mode */ 211 #define I2SCTL_I2SOPMOD(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) 212 #define I2S_MODE_SLAVETX I2SCTL_I2SOPMOD(0) /*!< I2S slave transmit mode */ 213 #define I2S_MODE_SLAVERX I2SCTL_I2SOPMOD(1) /*!< I2S slave receive mode */ 214 #define I2S_MODE_MASTERTX I2SCTL_I2SOPMOD(2) /*!< I2S master transmit mode */ 215 #define I2S_MODE_MASTERRX I2SCTL_I2SOPMOD(3) /*!< I2S master receive mode */ 216 217 /* I2S standard */ 218 #define I2SCTL_I2SSTD(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 219 #define I2S_STD_PHILLIPS I2SCTL_I2SSTD(0) /*!< I2S phillips standard */ 220 #define I2S_STD_MSB I2SCTL_I2SSTD(1) /*!< I2S MSB standard */ 221 #define I2S_STD_LSB I2SCTL_I2SSTD(2) /*!< I2S LSB standard */ 222 #define I2S_STD_PCMSHORT I2SCTL_I2SSTD(3) /*!< I2S PCM short standard */ 223 #define I2S_STD_PCMLONG (I2SCTL_I2SSTD(3) | SPI_I2SCTL_PCMSMOD) /*!< I2S PCM long standard */ 224 225 /* I2S clock polarity */ 226 #define I2S_CKPL_LOW ((uint32_t)0x00000000U) /*!< I2S clock polarity low level */ 227 #define I2S_CKPL_HIGH SPI_I2SCTL_CKPL /*!< I2S clock polarity high level */ 228 229 /* SPI DMA constants definitions */ 230 #define SPI_DMA_TRANSMIT ((uint8_t)0x00U) /*!< SPI transmit data use DMA */ 231 #define SPI_DMA_RECEIVE ((uint8_t)0x01U) /*!< SPI receive data use DMA */ 232 233 /* SPI CRC constants definitions */ 234 #define SPI_CRC_TX ((uint8_t)0x00U) /*!< SPI transmit CRC value */ 235 #define SPI_CRC_RX ((uint8_t)0x01U) /*!< SPI receive CRC value */ 236 237 /* SPI/I2S interrupt enable/disable constants definitions */ 238 #define SPI_I2S_INT_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt */ 239 #define SPI_I2S_INT_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt */ 240 #define SPI_I2S_INT_ERR ((uint8_t)0x02U) /*!< error interrupt */ 241 242 /* SPI/I2S interrupt flag constants definitions */ 243 #define SPI_I2S_INT_FLAG_TBE ((uint8_t)0x00U) /*!< transmit buffer empty interrupt flag */ 244 #define SPI_I2S_INT_FLAG_RBNE ((uint8_t)0x01U) /*!< receive buffer not empty interrupt flag */ 245 #define SPI_I2S_INT_FLAG_RXORERR ((uint8_t)0x02U) /*!< overrun interrupt flag */ 246 #define SPI_INT_FLAG_CONFERR ((uint8_t)0x03U) /*!< config error interrupt flag */ 247 #define SPI_INT_FLAG_CRCERR ((uint8_t)0x04U) /*!< CRC error interrupt flag */ 248 #define I2S_INT_FLAG_TXURERR ((uint8_t)0x05U) /*!< underrun error interrupt flag */ 249 #define SPI_I2S_INT_FLAG_FERR ((uint8_t)0x06U) /*!< format error interrupt flag */ 250 251 /* SPI/I2S flag definitions */ 252 #define SPI_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ 253 #define SPI_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ 254 #define SPI_FLAG_CRCERR SPI_STAT_CRCERR /*!< CRC error flag */ 255 #define SPI_FLAG_CONFERR SPI_STAT_CONFERR /*!< mode config error flag */ 256 #define SPI_FLAG_RXORERR SPI_STAT_RXORERR /*!< receive overrun error flag */ 257 #define SPI_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ 258 #define SPI_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ 259 #define I2S_FLAG_RBNE SPI_STAT_RBNE /*!< receive buffer not empty flag */ 260 #define I2S_FLAG_TBE SPI_STAT_TBE /*!< transmit buffer empty flag */ 261 #define I2S_FLAG_CH SPI_STAT_I2SCH /*!< channel side flag */ 262 #define I2S_FLAG_TXURERR SPI_STAT_TXURERR /*!< underrun error flag */ 263 #define I2S_FLAG_RXORERR SPI_STAT_RXORERR /*!< overrun error flag */ 264 #define I2S_FLAG_TRANS SPI_STAT_TRANS /*!< transmit on-going flag */ 265 #define I2S_FLAG_FERR SPI_STAT_FERR /*!< format error interrupt flag */ 266 267 /* function declarations */ 268 /* SPI/I2S deinitialization and initialization functions */ 269 /* reset SPI and I2S */ 270 void spi_i2s_deinit(uint32_t spi_periph); 271 /* initialize the parameters of SPI struct with the default values */ 272 void spi_struct_para_init(spi_parameter_struct* spi_struct); 273 /* initialize SPI parameter */ 274 void spi_init(uint32_t spi_periph, spi_parameter_struct* spi_struct); 275 /* enable SPI */ 276 void spi_enable(uint32_t spi_periph); 277 /* disable SPI */ 278 void spi_disable(uint32_t spi_periph); 279 280 /* initialize I2S parameter */ 281 void i2s_init(uint32_t spi_periph, uint32_t mode, uint32_t standard, uint32_t ckpl); 282 /* configure I2S prescaler */ 283 void i2s_psc_config(uint32_t spi_periph, uint32_t audiosample, uint32_t frameformat, uint32_t mckout); 284 /* enable I2S */ 285 void i2s_enable(uint32_t spi_periph); 286 /* disable I2S */ 287 void i2s_disable(uint32_t spi_periph); 288 289 /* NSS functions */ 290 /* enable SPI NSS output */ 291 void spi_nss_output_enable(uint32_t spi_periph); 292 /* disable SPI NSS output */ 293 void spi_nss_output_disable(uint32_t spi_periph); 294 /* SPI NSS pin high level in software mode */ 295 void spi_nss_internal_high(uint32_t spi_periph); 296 /* SPI NSS pin low level in software mode */ 297 void spi_nss_internal_low(uint32_t spi_periph); 298 299 /* enable SPI DMA */ 300 void spi_dma_enable(uint32_t spi_periph, uint8_t dma); 301 /* disable SPI DMA */ 302 void spi_dma_disable(uint32_t spi_periph, uint8_t dma); 303 304 /* configure SPI/I2S data frame format */ 305 void spi_i2s_data_frame_format_config(uint32_t spi_periph, uint16_t frame_format); 306 /* SPI transmit data */ 307 void spi_i2s_data_transmit(uint32_t spi_periph, uint16_t data); 308 /* SPI receive data */ 309 uint16_t spi_i2s_data_receive(uint32_t spi_periph); 310 /* configure SPI bidirectional transfer direction */ 311 void spi_bidirectional_transfer_config(uint32_t spi_periph, uint32_t transfer_direction); 312 313 /* SPI CRC functions */ 314 /* set SPI CRC polynomial */ 315 void spi_crc_polynomial_set(uint32_t spi_periph, uint16_t crc_poly); 316 /* get SPI CRC polynomial */ 317 uint16_t spi_crc_polynomial_get(uint32_t spi_periph); 318 /* turn on SPI CRC function */ 319 void spi_crc_on(uint32_t spi_periph); 320 /* turn off SPI CRC function */ 321 void spi_crc_off(uint32_t spi_periph); 322 /* SPI next data is CRC value */ 323 void spi_crc_next(uint32_t spi_periph); 324 /* get SPI CRC send value or receive value */ 325 uint16_t spi_crc_get(uint32_t spi_periph, uint8_t crc); 326 327 /* SPI TI mode functions */ 328 /* enable SPI TI mode */ 329 void spi_ti_mode_enable(uint32_t spi_periph); 330 /* disable SPI TI mode */ 331 void spi_ti_mode_disable(uint32_t spi_periph); 332 333 /* SPI NSS pulse mode functions */ 334 /* enable SPI NSS pulse mode */ 335 void spi_nssp_mode_enable(uint32_t spi_periph); 336 /* disable SPI NSS pulse mode */ 337 void spi_nssp_mode_disable(uint32_t spi_periph); 338 339 /* quad wire SPI functions */ 340 /* enable SPI quad wire mode */ 341 void spi_quad_enable(uint32_t spi_periph); 342 /* disable SPI quad wire mode */ 343 void spi_quad_disable(uint32_t spi_periph); 344 /* enable SPI quad wire mode write */ 345 void spi_quad_write_enable(uint32_t spi_periph); 346 /* enable SPI quad wire mode read */ 347 void spi_quad_read_enable(uint32_t spi_periph); 348 /* enable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output */ 349 void spi_quad_io23_output_enable(uint32_t spi_periph); 350 /* disable SPI quad wire mode SPI_IO2 and SPI_IO3 pin output */ 351 void spi_quad_io23_output_disable(uint32_t spi_periph); 352 353 /* flag and interrupt functions */ 354 /* enable SPI and I2S interrupt */ 355 void spi_i2s_interrupt_enable(uint32_t spi_periph, uint8_t interrupt); 356 /* disable SPI and I2S interrupt */ 357 void spi_i2s_interrupt_disable(uint32_t spi_periph, uint8_t interrupt); 358 /* get SPI and I2S interrupt status */ 359 FlagStatus spi_i2s_interrupt_flag_get(uint32_t spi_periph, uint8_t interrupt); 360 /* get SPI and I2S flag status */ 361 FlagStatus spi_i2s_flag_get(uint32_t spi_periph, uint32_t flag); 362 /* clear SPI CRC error flag status */ 363 void spi_crc_error_clear(uint32_t spi_periph); 364 365 #endif /* GD32E10X_SPI_H */ 366
