1 /*! 2 \file gd32e10x_rtc.h 3 \brief definitions for the RTC 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_RTC_H 39 #define GD32E10X_RTC_H 40 41 #include "gd32e10x.h" 42 43 /* RTC definitions */ 44 #define RTC RTC_BASE 45 46 /* registers definitions */ 47 #define RTC_INTEN REG32(RTC + 0x00U) /*!< interrupt enable register */ 48 #define RTC_CTL REG32(RTC + 0x04U) /*!< control register */ 49 #define RTC_PSCH REG32(RTC + 0x08U) /*!< prescaler high register */ 50 #define RTC_PSCL REG32(RTC + 0x0CU) /*!< prescaler low register */ 51 #define RTC_DIVH REG32(RTC + 0x10U) /*!< divider high register */ 52 #define RTC_DIVL REG32(RTC + 0x14U) /*!< divider low register */ 53 #define RTC_CNTH REG32(RTC + 0x18U) /*!< counter high register */ 54 #define RTC_CNTL REG32(RTC + 0x1CU) /*!< counter low register */ 55 #define RTC_ALRMH REG32(RTC + 0x20U) /*!< alarm high register */ 56 #define RTC_ALRML REG32(RTC + 0x24U) /*!< alarm low register */ 57 58 /* bits definitions */ 59 /* RTC_INTEN */ 60 #define RTC_INTEN_SCIE BIT(0) /*!< second interrupt enable */ 61 #define RTC_INTEN_ALRMIE BIT(1) /*!< alarm interrupt enable */ 62 #define RTC_INTEN_OVIE BIT(2) /*!< overflow interrupt enable */ 63 64 /* RTC_CTL */ 65 #define RTC_CTL_SCIF BIT(0) /*!< second interrupt flag */ 66 #define RTC_CTL_ALRMIF BIT(1) /*!< alarm interrupt flag */ 67 #define RTC_CTL_OVIF BIT(2) /*!< overflow interrupt flag */ 68 #define RTC_CTL_RSYNF BIT(3) /*!< registers synchronized flag */ 69 #define RTC_CTL_CMF BIT(4) /*!< configuration mode flag */ 70 #define RTC_CTL_LWOFF BIT(5) /*!< last write operation finished flag */ 71 72 /* RTC_PSCH */ 73 #define RTC_PSCH_PSC BITS(0,3) /*!< prescaler high value */ 74 75 /* RTC_PSCL */ 76 #define RTC_PSCL_PSC BITS(0,15) /*!< prescaler low value */ 77 78 /* RTC_DIVH */ 79 #define RTC_DIVH_DIV BITS(0,3) /*!< divider high value */ 80 81 /* RTC_DIVL */ 82 #define RTC_DIVL_DIV BITS(0,15) /*!< divider low value */ 83 84 /* RTC_CNTH */ 85 #define RTC_CNTH_CNT BITS(0,15) /*!< counter high value */ 86 87 /* RTC_CNTL */ 88 #define RTC_CNTL_CNT BITS(0,15) /*!< counter low value */ 89 90 /* RTC_ALRMH */ 91 #define RTC_ALRMH_ALRM BITS(0,15) /*!< alarm high value */ 92 93 /* RTC_ALRML */ 94 #define RTC_ALRML_ALRM BITS(0,15) /*!< alarm low value */ 95 96 /* constants definitions */ 97 /* RTC interrupt enable or disable definitions */ 98 #define RTC_INT_SECOND RTC_INTEN_SCIE /*!< second interrupt enable */ 99 #define RTC_INT_ALARM RTC_INTEN_ALRMIE /*!< alarm interrupt enable */ 100 #define RTC_INT_OVERFLOW RTC_INTEN_OVIE /*!< overflow interrupt enable */ 101 102 /* RTC interrupt flag definitions */ 103 #define RTC_INT_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ 104 #define RTC_INT_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ 105 #define RTC_INT_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ 106 107 /* RTC flag definitions */ 108 #define RTC_FLAG_SECOND RTC_CTL_SCIF /*!< second interrupt flag */ 109 #define RTC_FLAG_ALARM RTC_CTL_ALRMIF /*!< alarm interrupt flag */ 110 #define RTC_FLAG_OVERFLOW RTC_CTL_OVIF /*!< overflow interrupt flag */ 111 #define RTC_FLAG_RSYN RTC_CTL_RSYNF /*!< registers synchronized flag */ 112 #define RTC_FLAG_LWOF RTC_CTL_LWOFF /*!< last write operation finished flag */ 113 114 /* function declarations */ 115 /* initialization functions */ 116 /* enter RTC configuration mode */ 117 void rtc_configuration_mode_enter(void); 118 /* exit RTC configuration mode */ 119 void rtc_configuration_mode_exit(void); 120 /* set RTC counter value */ 121 void rtc_counter_set(uint32_t cnt); 122 /* set RTC prescaler value */ 123 void rtc_prescaler_set(uint32_t psc); 124 125 /* operation functions */ 126 /* wait RTC last write operation finished flag set */ 127 void rtc_lwoff_wait(void); 128 /* wait RTC registers synchronized flag set */ 129 void rtc_register_sync_wait(void); 130 /* set RTC alarm value */ 131 void rtc_alarm_config(uint32_t alarm); 132 /* get RTC counter value */ 133 uint32_t rtc_counter_get(void); 134 /* get RTC divider value */ 135 uint32_t rtc_divider_get(void); 136 137 /* flag & interrupt functions */ 138 /* get RTC flag status */ 139 FlagStatus rtc_flag_get(uint32_t flag); 140 /* clear RTC flag status */ 141 void rtc_flag_clear(uint32_t flag); 142 /* get RTC interrupt flag status */ 143 FlagStatus rtc_interrupt_flag_get(uint32_t flag); 144 /* clear RTC interrupt flag status */ 145 void rtc_interrupt_flag_clear(uint32_t flag); 146 /* enable RTC interrupt */ 147 void rtc_interrupt_enable(uint32_t interrupt); 148 /* disable RTC interrupt */ 149 void rtc_interrupt_disable(uint32_t interrupt); 150 151 #endif /* GD32E10X_RTC_H */ 152
