1 /*! 2 \file gd32e10x_i2c.h 3 \brief definitions for the I2C 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2019-04-16, V1.0.1, firmware for GD32E10x 7 \version 2020-09-30, V1.1.0, firmware for GD32E10x 8 \version 2020-12-31, V1.2.0, firmware for GD32E10x 9 \version 2022-06-30, V1.3.0, firmware for GD32E10x 10 */ 11 12 /* 13 Copyright (c) 2022, GigaDevice Semiconductor Inc. 14 15 Redistribution and use in source and binary forms, with or without modification, 16 are permitted provided that the following conditions are met: 17 18 1. Redistributions of source code must retain the above copyright notice, this 19 list of conditions and the following disclaimer. 20 2. Redistributions in binary form must reproduce the above copyright notice, 21 this list of conditions and the following disclaimer in the documentation 22 and/or other materials provided with the distribution. 23 3. Neither the name of the copyright holder nor the names of its contributors 24 may be used to endorse or promote products derived from this software without 25 specific prior written permission. 26 27 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 28 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 29 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 32 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 33 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 34 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 35 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 36 OF SUCH DAMAGE. 37 */ 38 39 #ifndef GD32E10X_I2C_H 40 #define GD32E10X_I2C_H 41 42 #include "gd32e10x.h" 43 44 /* I2Cx(x=0,1) definitions */ 45 #define I2C0 I2C_BASE /*!< I2C0 base address */ 46 #define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ 47 48 /* registers definitions */ 49 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00000000U) /*!< I2C control register 0 */ 50 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x00000004U) /*!< I2C control register 1 */ 51 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x00000008U) /*!< I2C slave address register 0*/ 52 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0000000CU) /*!< I2C slave address register 1 */ 53 #define I2C_DATA(i2cx) REG32((i2cx) + 0x00000010U) /*!< I2C transfer buffer register */ 54 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x00000014U) /*!< I2C transfer status register 0 */ 55 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x00000018U) /*!< I2C transfer status register */ 56 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x0000001CU) /*!< I2C clock configure register */ 57 #define I2C_RT(i2cx) REG32((i2cx) + 0x00000020U) /*!< I2C rise time register */ 58 #define I2C_SAMCS(i2cx) REG32((i2cx) + 0x00000080U) /*!< I2C SAM control and status register */ 59 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x00000090U) /*!< I2C fast-mode-plus configure register */ 60 61 /* bits definitions */ 62 /* I2Cx_CTL0 */ 63 #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ 64 #define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ 65 #define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ 66 #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ 67 #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ 68 #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ 69 #define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ 70 #define I2C_CTL0_START BIT(8) /*!< start generation */ 71 #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ 72 #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ 73 #define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ 74 #define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ 75 #define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ 76 #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ 77 78 /* I2Cx_CTL1 */ 79 #define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ 80 #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ 81 #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ 82 #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ 83 #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ 84 #define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ 85 86 /* I2Cx_SADDR0 */ 87 #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ 88 #define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ 89 #define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ 90 #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ 91 92 /* I2Cx_SADDR1 */ 93 #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ 94 #define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ 95 96 /* I2Cx_DATA */ 97 #define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ 98 99 /* I2Cx_STAT0 */ 100 #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ 101 #define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ 102 #define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ 103 #define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ 104 #define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ 105 #define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ 106 #define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ 107 #define I2C_STAT0_BERR BIT(8) /*!< bus error */ 108 #define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ 109 #define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ 110 #define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ 111 #define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ 112 #define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ 113 #define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ 114 115 /* I2Cx_STAT1 */ 116 #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ 117 #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ 118 #define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ 119 #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ 120 #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ 121 #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ 122 #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ 123 #define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ 124 125 /* I2Cx_CKCFG */ 126 #define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode or fast mode plus(master mode) */ 127 #define I2C_CKCFG_DTCY BIT(14) /*!< duty cycle of fast mode or fast mode plus */ 128 #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ 129 130 /* I2Cx_RT */ 131 #define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode or fast mode plus(master mode) */ 132 133 /* I2Cx_SAMCS */ 134 #define I2C_SAMCS_SAMEN BIT(0) /*!< SAM_V interface enable */ 135 #define I2C_SAMCS_STOEN BIT(1) /*!< SAM_V interface timeout detect enable */ 136 #define I2C_SAMCS_TFFIE BIT(4) /*!< txframe fall interrupt enable */ 137 #define I2C_SAMCS_TFRIE BIT(5) /*!< txframe rise interrupt enable */ 138 #define I2C_SAMCS_RFFIE BIT(6) /*!< rxframe fall interrupt enable */ 139 #define I2C_SAMCS_RFRIE BIT(7) /*!< rxframe rise interrupt enable */ 140 #define I2C_SAMCS_TXF BIT(8) /*!< level of txframe signal */ 141 #define I2C_SAMCS_RXF BIT(9) /*!< level of rxframe signal */ 142 #define I2C_SAMCS_TFF BIT(12) /*!< txframe fall flag, cleared by software write 0 */ 143 #define I2C_SAMCS_TFR BIT(13) /*!< txframe rise flag, cleared by software write 0 */ 144 #define I2C_SAMCS_RFF BIT(14) /*!< rxframe fall flag, cleared by software write 0 */ 145 #define I2C_SAMCS_RFR BIT(15) /*!< rxframe rise flag, cleared by software write 0 */ 146 147 /* I2Cx_FMPCFG */ 148 #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable */ 149 150 /* constants definitions */ 151 /* define the I2C bit position and its register index offset */ 152 #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 153 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 154 #define I2C_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 155 #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 156 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 157 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) 158 #define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 159 160 /* register offset */ 161 #define I2C_CTL1_REG_OFFSET ((uint32_t)0x00000004U) /*!< CTL1 register offset */ 162 #define I2C_STAT0_REG_OFFSET ((uint32_t)0x00000014U) /*!< STAT0 register offset */ 163 #define I2C_STAT1_REG_OFFSET ((uint32_t)0x00000018U) /*!< STAT1 register offset */ 164 #define I2C_SAMCS_REG_OFFSET ((uint32_t)0x00000080U) /*!< SAMCS register offset */ 165 166 /* I2C flags */ 167 typedef enum{ 168 /* flags in STAT0 register */ 169 I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ 170 I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ 171 I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ 172 I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ 173 I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ 174 I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ 175 I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ 176 I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ 177 I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ 178 I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ 179 I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ 180 I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ 181 I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ 182 I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ 183 /* flags in STAT1 register */ 184 I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ 185 I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ 186 I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ 187 I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ 188 I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ 189 I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ 190 I2C_FLAG_DUMOD = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ 191 /* flags in SAMCS register */ 192 I2C_FLAG_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall flag */ 193 I2C_FLAG_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise flag */ 194 I2C_FLAG_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall flag */ 195 I2C_FLAG_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise flag */ 196 } i2c_flag_enum; 197 198 /* I2C interrupt flags */ 199 typedef enum { 200 /* interrupt flags in CTL1 register */ 201 I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ 202 I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ 203 I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes interrupt flag */ 204 I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ 205 I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ 206 I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ 207 I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U, I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ 208 I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ 209 I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ 210 I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ 211 I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ 212 I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ 213 I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ 214 I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U, I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status interrupt flag */ 215 /* interrupt flags in SAMCS register */ 216 I2C_INT_FLAG_TFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 4U, I2C_SAMCS_REG_OFFSET, 12U), /*!< txframe fall interrupt flag */ 217 I2C_INT_FLAG_TFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 5U, I2C_SAMCS_REG_OFFSET, 13U), /*!< txframe rise interrupt flag */ 218 I2C_INT_FLAG_RFF = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 6U, I2C_SAMCS_REG_OFFSET, 14U), /*!< rxframe fall interrupt flag */ 219 I2C_INT_FLAG_RFR = I2C_REGIDX_BIT2(I2C_SAMCS_REG_OFFSET, 7U, I2C_SAMCS_REG_OFFSET, 15U) /*!< rxframe rise interrupt flag */ 220 }i2c_interrupt_flag_enum; 221 222 /* I2C interrupt */ 223 typedef enum { 224 /* interrupt in CTL1 register */ 225 I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt */ 226 I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt */ 227 I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt */ 228 /* interrupt in SAMCS register */ 229 I2C_INT_TFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 4U), /*!< txframe fall interrupt */ 230 I2C_INT_TFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 5U), /*!< txframe rise interrupt */ 231 I2C_INT_RFF = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 6U), /*!< rxframe fall interrupt */ 232 I2C_INT_RFR = I2C_REGIDX_BIT(I2C_SAMCS_REG_OFFSET, 7U), /*!< rxframe rise interrupt */ 233 } i2c_interrupt_enum; 234 235 /* SMBus/I2C mode switch and SMBus type selection */ 236 #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ 237 #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ 238 239 /* SMBus/I2C mode switch and SMBus type selection */ 240 #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ 241 #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ 242 243 /* I2C transfer direction */ 244 #define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ 245 #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ 246 247 /* whether or not to send an ACK */ 248 #define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ 249 #define I2C_ACK_ENABLE I2C_CTL0_ACKEN /*!< ACK will be sent */ 250 251 /* I2C POAP position*/ 252 #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ 253 #define I2C_ACKPOS_NEXT I2C_CTL0_POAP /*!< ACKEN bit decides whether or not to send ACK for the next byte */ 254 255 /* whether or not to stretch SCL low */ 256 #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ 257 #define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ 258 259 /* whether or not to response to a general call */ 260 #define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ 261 #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ 262 263 /* software reset I2C */ 264 #define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ 265 #define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ 266 267 /* I2C DMA mode configure */ 268 /* DMA mode switch */ 269 #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< disable DMA mode */ 270 #define I2C_DMA_ON I2C_CTL1_DMAON /*!< enable DMA mode */ 271 272 /* flag indicating DMA last transfer */ 273 #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ 274 #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ 275 276 /* I2C PEC configure */ 277 /* PEC enable */ 278 #define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ 279 #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ 280 281 /* PEC transfer */ 282 #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ 283 #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC value */ 284 285 /* I2C SMBus configure */ 286 /* issue or not alert through SMBA pin */ 287 #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ 288 #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ 289 290 /* ARP protocol in SMBus switch */ 291 #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< disable ARP */ 292 #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< enable ARP */ 293 294 /* fast mode plus enable */ 295 #define I2C_FAST_MODE_PLUS_DISABLE ((uint32_t)0x00000000U) /*!< fast mode plus disable */ 296 #define I2C_FAST_MODE_PLUS_ENABLE I2C_FMPCFG_FMPEN /*!< fast mode plus enable */ 297 298 /* transmit I2C data */ 299 #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 300 301 /* receive I2C data */ 302 #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) 303 304 /* I2C duty cycle in fast mode or fast mode plus */ 305 #define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< Tlow/Thigh = 2 in I2C fast mode or fast mode plus */ 306 #define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< Tlow/Thigh = 16/9 in I2C fast mode or fast mode plus */ 307 308 /* address mode for the I2C slave */ 309 #define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address format is 7 bits */ 310 #define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address format is 10 bits */ 311 312 #define I2CCLK_MAX ((uint32_t)0x0000003FU)/*!< i2cclk maximum value */ 313 #define I2CCLK_MIN ((uint32_t)0x00000002U)/*!< i2cclk minimum value for standard mode */ 314 #define I2CCLK_FM_MIN ((uint32_t)0x00000008U)/*!< i2cclk minimum value for fast mode */ 315 #define I2CCLK_FM_PLUS_MIN ((uint32_t)0x00000018U)/*!< i2cclk minimum value for fast mode plus */ 316 317 /* function declarations */ 318 /* reset I2C */ 319 void i2c_deinit(uint32_t i2c_periph); 320 /* configure I2C clock */ 321 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); 322 /* configure I2C address */ 323 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode, uint32_t addformat, uint32_t addr); 324 /* select SMBus type */ 325 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); 326 /* whether or not to send an ACK */ 327 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); 328 /* configure I2C POAP position */ 329 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); 330 /* master sends slave address */ 331 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr, uint32_t trandirection); 332 /* enable dual-address mode */ 333 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t addr); 334 /* disable dual-address mode */ 335 void i2c_dualaddr_disable(uint32_t i2c_periph); 336 /* enable I2C */ 337 void i2c_enable(uint32_t i2c_periph); 338 /* disable I2C */ 339 void i2c_disable(uint32_t i2c_periph); 340 341 /* generate a START condition on I2C bus */ 342 void i2c_start_on_bus(uint32_t i2c_periph); 343 /* generate a STOP condition on I2C bus */ 344 void i2c_stop_on_bus(uint32_t i2c_periph); 345 /* I2C transmit data function */ 346 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); 347 /* I2C receive data function */ 348 uint8_t i2c_data_receive(uint32_t i2c_periph); 349 /* configure I2C DMA mode */ 350 void i2c_dma_config(uint32_t i2c_periph, uint32_t dmastate); 351 /* configure whether next DMA EOT is DMA last transfer or not */ 352 void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); 353 /* whether to stretch SCL low when data is not ready in slave mode */ 354 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); 355 /* whether or not to response to a general call */ 356 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); 357 /* configure software reset of I2C */ 358 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); 359 360 /* configure I2C PEC calculation */ 361 void i2c_pec_config(uint32_t i2c_periph, uint32_t pecstate); 362 /* configure whether to transfer PEC value */ 363 void i2c_pec_transfer_config(uint32_t i2c_periph, uint32_t pecpara); 364 /* get packet error checking value */ 365 uint8_t i2c_pec_value_get(uint32_t i2c_periph); 366 /* configure I2C alert through SMBA pin */ 367 void i2c_smbus_alert_config(uint32_t i2c_periph, uint32_t smbuspara); 368 /* configure I2C ARP protocol in SMBus */ 369 void i2c_smbus_arp_config(uint32_t i2c_periph, uint32_t arpstate); 370 371 /* enable SAM_V interface */ 372 void i2c_sam_enable(uint32_t i2c_periph); 373 /* disable SAM_V interface */ 374 void i2c_sam_disable(uint32_t i2c_periph); 375 /* enable SAM_V interface timeout detect */ 376 void i2c_sam_timeout_enable(uint32_t i2c_periph); 377 /* disable SAM_V interface timeout detect */ 378 void i2c_sam_timeout_disable(uint32_t i2c_periph); 379 380 /* get I2C flag status */ 381 FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); 382 /* clear I2C flag status */ 383 void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); 384 /* enable I2C interrupt */ 385 void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 386 /* disable I2C interrupt */ 387 void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 388 /* get I2C interrupt flag status */ 389 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 390 /* clear I2C interrupt flag status */ 391 void i2c_interrupt_flag_clear(uint32_t i2c_periph, i2c_interrupt_flag_enum int_flag); 392 393 #endif /* GD32E10X_I2C_H */ 394
