1 /*! 2 \file gd32e10x_gpio.h 3 \brief definitions for the GPIO 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_GPIO_H 39 #define GD32E10X_GPIO_H 40 41 #include "gd32e10x.h" 42 43 /* GPIOx(x=A,B,C,D,E) definitions */ 44 #define GPIOA (GPIO_BASE + 0x00000000U) 45 #define GPIOB (GPIO_BASE + 0x00000400U) 46 #define GPIOC (GPIO_BASE + 0x00000800U) 47 #define GPIOD (GPIO_BASE + 0x00000C00U) 48 #define GPIOE (GPIO_BASE + 0x00001000U) 49 50 /* AFIO definitions */ 51 #define AFIO AFIO_BASE 52 53 /* registers definitions */ 54 /* GPIO registers definitions */ 55 #define GPIO_CTL0(gpiox) REG32((gpiox) + 0x00U) /*!< GPIO port control register 0 */ 56 #define GPIO_CTL1(gpiox) REG32((gpiox) + 0x04U) /*!< GPIO port control register 1 */ 57 #define GPIO_ISTAT(gpiox) REG32((gpiox) + 0x08U) /*!< GPIO port input status register */ 58 #define GPIO_OCTL(gpiox) REG32((gpiox) + 0x0CU) /*!< GPIO port output control register */ 59 #define GPIO_BOP(gpiox) REG32((gpiox) + 0x10U) /*!< GPIO port bit operation register */ 60 #define GPIO_BC(gpiox) REG32((gpiox) + 0x14U) /*!< GPIO bit clear register */ 61 #define GPIO_LOCK(gpiox) REG32((gpiox) + 0x18U) /*!< GPIO port configuration lock register */ 62 #define GPIOx_SPD(gpiox) REG32((gpiox) + 0x3CU) /*!< GPIO port bit speed register */ 63 64 /* AFIO registers definitions */ 65 #define AFIO_EC REG32(AFIO + 0x00U) /*!< AFIO event control register */ 66 #define AFIO_PCF0 REG32(AFIO + 0x04U) /*!< AFIO port configuration register 0 */ 67 #define AFIO_EXTISS0 REG32(AFIO + 0x08U) /*!< AFIO port EXTI sources selection register 0 */ 68 #define AFIO_EXTISS1 REG32(AFIO + 0x0CU) /*!< AFIO port EXTI sources selection register 1 */ 69 #define AFIO_EXTISS2 REG32(AFIO + 0x10U) /*!< AFIO port EXTI sources selection register 2 */ 70 #define AFIO_EXTISS3 REG32(AFIO + 0x14U) /*!< AFIO port EXTI sources selection register 3 */ 71 #define AFIO_PCF1 REG32(AFIO + 0x1CU) /*!< AFIO port configuration register 1 */ 72 #define AFIO_CPSCTL REG32(AFIO + 0x20U) /*!< IO compensation control register */ 73 74 /* bits definitions */ 75 /* GPIO_CTL0 */ 76 #define GPIO_CTL0_MD0 BITS(0,1) /*!< port 0 mode bits */ 77 #define GPIO_CTL0_CTL0 BITS(2,3) /*!< pin 0 configuration bits */ 78 #define GPIO_CTL0_MD1 BITS(4,5) /*!< port 1 mode bits */ 79 #define GPIO_CTL0_CTL1 BITS(6,7) /*!< pin 1 configuration bits */ 80 #define GPIO_CTL0_MD2 BITS(8,9) /*!< port 2 mode bits */ 81 #define GPIO_CTL0_CTL2 BITS(10,11) /*!< pin 2 configuration bits */ 82 #define GPIO_CTL0_MD3 BITS(12,13) /*!< port 3 mode bits */ 83 #define GPIO_CTL0_CTL3 BITS(14,15) /*!< pin 3 configuration bits */ 84 #define GPIO_CTL0_MD4 BITS(16,17) /*!< port 4 mode bits */ 85 #define GPIO_CTL0_CTL4 BITS(18,19) /*!< pin 4 configuration bits */ 86 #define GPIO_CTL0_MD5 BITS(20,21) /*!< port 5 mode bits */ 87 #define GPIO_CTL0_CTL5 BITS(22,23) /*!< pin 5 configuration bits */ 88 #define GPIO_CTL0_MD6 BITS(24,25) /*!< port 6 mode bits */ 89 #define GPIO_CTL0_CTL6 BITS(26,27) /*!< pin 6 configuration bits */ 90 #define GPIO_CTL0_MD7 BITS(28,29) /*!< port 7 mode bits */ 91 #define GPIO_CTL0_CTL7 BITS(30,31) /*!< pin 7 configuration bits */ 92 93 /* GPIO_CTL1 */ 94 #define GPIO_CTL1_MD8 BITS(0,1) /*!< port 8 mode bits */ 95 #define GPIO_CTL1_CTL8 BITS(2,3) /*!< pin 8 configuration bits */ 96 #define GPIO_CTL1_MD9 BITS(4,5) /*!< port 9 mode bits */ 97 #define GPIO_CTL1_CTL9 BITS(6,7) /*!< pin 9 configuration bits */ 98 #define GPIO_CTL1_MD10 BITS(8,9) /*!< port 10 mode bits */ 99 #define GPIO_CTL1_CTL10 BITS(10,11) /*!< pin 10 configuration bits */ 100 #define GPIO_CTL1_MD11 BITS(12,13) /*!< port 11 mode bits */ 101 #define GPIO_CTL1_CTL11 BITS(14,15) /*!< pin 11 configuration bits */ 102 #define GPIO_CTL1_MD12 BITS(16,17) /*!< port 12 mode bits */ 103 #define GPIO_CTL1_CTL12 BITS(18,19) /*!< pin 12 configuration bits */ 104 #define GPIO_CTL1_MD13 BITS(20,21) /*!< port 13 mode bits */ 105 #define GPIO_CTL1_CTL13 BITS(22,23) /*!< pin 13 configuration bits */ 106 #define GPIO_CTL1_MD14 BITS(24,25) /*!< port 14 mode bits */ 107 #define GPIO_CTL1_CTL14 BITS(26,27) /*!< pin 14 configuration bits */ 108 #define GPIO_CTL1_MD15 BITS(28,29) /*!< port 15 mode bits */ 109 #define GPIO_CTL1_CTL15 BITS(30,31) /*!< pin 15 configuration bits */ 110 111 /* GPIO_ISTAT */ 112 #define GPIO_ISTAT_ISTAT0 BIT(0) /*!< pin 0 input status */ 113 #define GPIO_ISTAT_ISTAT1 BIT(1) /*!< pin 1 input status */ 114 #define GPIO_ISTAT_ISTAT2 BIT(2) /*!< pin 2 input status */ 115 #define GPIO_ISTAT_ISTAT3 BIT(3) /*!< pin 3 input status */ 116 #define GPIO_ISTAT_ISTAT4 BIT(4) /*!< pin 4 input status */ 117 #define GPIO_ISTAT_ISTAT5 BIT(5) /*!< pin 5 input status */ 118 #define GPIO_ISTAT_ISTAT6 BIT(6) /*!< pin 6 input status */ 119 #define GPIO_ISTAT_ISTAT7 BIT(7) /*!< pin 7 input status */ 120 #define GPIO_ISTAT_ISTAT8 BIT(8) /*!< pin 8 input status */ 121 #define GPIO_ISTAT_ISTAT9 BIT(9) /*!< pin 9 input status */ 122 #define GPIO_ISTAT_ISTAT10 BIT(10) /*!< pin 10 input status */ 123 #define GPIO_ISTAT_ISTAT11 BIT(11) /*!< pin 11 input status */ 124 #define GPIO_ISTAT_ISTAT12 BIT(12) /*!< pin 12 input status */ 125 #define GPIO_ISTAT_ISTAT13 BIT(13) /*!< pin 13 input status */ 126 #define GPIO_ISTAT_ISTAT14 BIT(14) /*!< pin 14 input status */ 127 #define GPIO_ISTAT_ISTAT15 BIT(15) /*!< pin 15 input status */ 128 129 /* GPIO_OCTL */ 130 #define GPIO_OCTL_OCTL0 BIT(0) /*!< pin 0 output bit */ 131 #define GPIO_OCTL_OCTL1 BIT(1) /*!< pin 1 output bit */ 132 #define GPIO_OCTL_OCTL2 BIT(2) /*!< pin 2 output bit */ 133 #define GPIO_OCTL_OCTL3 BIT(3) /*!< pin 3 output bit */ 134 #define GPIO_OCTL_OCTL4 BIT(4) /*!< pin 4 output bit */ 135 #define GPIO_OCTL_OCTL5 BIT(5) /*!< pin 5 output bit */ 136 #define GPIO_OCTL_OCTL6 BIT(6) /*!< pin 6 output bit */ 137 #define GPIO_OCTL_OCTL7 BIT(7) /*!< pin 7 output bit */ 138 #define GPIO_OCTL_OCTL8 BIT(8) /*!< pin 8 output bit */ 139 #define GPIO_OCTL_OCTL9 BIT(9) /*!< pin 9 output bit */ 140 #define GPIO_OCTL_OCTL10 BIT(10) /*!< pin 10 output bit */ 141 #define GPIO_OCTL_OCTL11 BIT(11) /*!< pin 11 output bit */ 142 #define GPIO_OCTL_OCTL12 BIT(12) /*!< pin 12 output bit */ 143 #define GPIO_OCTL_OCTL13 BIT(13) /*!< pin 13 output bit */ 144 #define GPIO_OCTL_OCTL14 BIT(14) /*!< pin 14 output bit */ 145 #define GPIO_OCTL_OCTL15 BIT(15) /*!< pin 15 output bit */ 146 147 /* GPIO_BOP */ 148 #define GPIO_BOP_BOP0 BIT(0) /*!< pin 0 set bit */ 149 #define GPIO_BOP_BOP1 BIT(1) /*!< pin 1 set bit */ 150 #define GPIO_BOP_BOP2 BIT(2) /*!< pin 2 set bit */ 151 #define GPIO_BOP_BOP3 BIT(3) /*!< pin 3 set bit */ 152 #define GPIO_BOP_BOP4 BIT(4) /*!< pin 4 set bit */ 153 #define GPIO_BOP_BOP5 BIT(5) /*!< pin 5 set bit */ 154 #define GPIO_BOP_BOP6 BIT(6) /*!< pin 6 set bit */ 155 #define GPIO_BOP_BOP7 BIT(7) /*!< pin 7 set bit */ 156 #define GPIO_BOP_BOP8 BIT(8) /*!< pin 8 set bit */ 157 #define GPIO_BOP_BOP9 BIT(9) /*!< pin 9 set bit */ 158 #define GPIO_BOP_BOP10 BIT(10) /*!< pin 10 set bit */ 159 #define GPIO_BOP_BOP11 BIT(11) /*!< pin 11 set bit */ 160 #define GPIO_BOP_BOP12 BIT(12) /*!< pin 12 set bit */ 161 #define GPIO_BOP_BOP13 BIT(13) /*!< pin 13 set bit */ 162 #define GPIO_BOP_BOP14 BIT(14) /*!< pin 14 set bit */ 163 #define GPIO_BOP_BOP15 BIT(15) /*!< pin 15 set bit */ 164 #define GPIO_BOP_CR0 BIT(16) /*!< pin 0 clear bit */ 165 #define GPIO_BOP_CR1 BIT(17) /*!< pin 1 clear bit */ 166 #define GPIO_BOP_CR2 BIT(18) /*!< pin 2 clear bit */ 167 #define GPIO_BOP_CR3 BIT(19) /*!< pin 3 clear bit */ 168 #define GPIO_BOP_CR4 BIT(20) /*!< pin 4 clear bit */ 169 #define GPIO_BOP_CR5 BIT(21) /*!< pin 5 clear bit */ 170 #define GPIO_BOP_CR6 BIT(22) /*!< pin 6 clear bit */ 171 #define GPIO_BOP_CR7 BIT(23) /*!< pin 7 clear bit */ 172 #define GPIO_BOP_CR8 BIT(24) /*!< pin 8 clear bit */ 173 #define GPIO_BOP_CR9 BIT(25) /*!< pin 9 clear bit */ 174 #define GPIO_BOP_CR10 BIT(26) /*!< pin 10 clear bit */ 175 #define GPIO_BOP_CR11 BIT(27) /*!< pin 11 clear bit */ 176 #define GPIO_BOP_CR12 BIT(28) /*!< pin 12 clear bit */ 177 #define GPIO_BOP_CR13 BIT(29) /*!< pin 13 clear bit */ 178 #define GPIO_BOP_CR14 BIT(30) /*!< pin 14 clear bit */ 179 #define GPIO_BOP_CR15 BIT(31) /*!< pin 15 clear bit */ 180 181 /* GPIO_BC */ 182 #define GPIO_BC_CR0 BIT(0) /*!< pin 0 clear bit */ 183 #define GPIO_BC_CR1 BIT(1) /*!< pin 1 clear bit */ 184 #define GPIO_BC_CR2 BIT(2) /*!< pin 2 clear bit */ 185 #define GPIO_BC_CR3 BIT(3) /*!< pin 3 clear bit */ 186 #define GPIO_BC_CR4 BIT(4) /*!< pin 4 clear bit */ 187 #define GPIO_BC_CR5 BIT(5) /*!< pin 5 clear bit */ 188 #define GPIO_BC_CR6 BIT(6) /*!< pin 6 clear bit */ 189 #define GPIO_BC_CR7 BIT(7) /*!< pin 7 clear bit */ 190 #define GPIO_BC_CR8 BIT(8) /*!< pin 8 clear bit */ 191 #define GPIO_BC_CR9 BIT(9) /*!< pin 9 clear bit */ 192 #define GPIO_BC_CR10 BIT(10) /*!< pin 10 clear bit */ 193 #define GPIO_BC_CR11 BIT(11) /*!< pin 11 clear bit */ 194 #define GPIO_BC_CR12 BIT(12) /*!< pin 12 clear bit */ 195 #define GPIO_BC_CR13 BIT(13) /*!< pin 13 clear bit */ 196 #define GPIO_BC_CR14 BIT(14) /*!< pin 14 clear bit */ 197 #define GPIO_BC_CR15 BIT(15) /*!< pin 15 clear bit */ 198 199 /* GPIO_LOCK */ 200 #define GPIO_LOCK_LK0 BIT(0) /*!< pin 0 lock bit */ 201 #define GPIO_LOCK_LK1 BIT(1) /*!< pin 1 lock bit */ 202 #define GPIO_LOCK_LK2 BIT(2) /*!< pin 2 lock bit */ 203 #define GPIO_LOCK_LK3 BIT(3) /*!< pin 3 lock bit */ 204 #define GPIO_LOCK_LK4 BIT(4) /*!< pin 4 lock bit */ 205 #define GPIO_LOCK_LK5 BIT(5) /*!< pin 5 lock bit */ 206 #define GPIO_LOCK_LK6 BIT(6) /*!< pin 6 lock bit */ 207 #define GPIO_LOCK_LK7 BIT(7) /*!< pin 7 lock bit */ 208 #define GPIO_LOCK_LK8 BIT(8) /*!< pin 8 lock bit */ 209 #define GPIO_LOCK_LK9 BIT(9) /*!< pin 9 lock bit */ 210 #define GPIO_LOCK_LK10 BIT(10) /*!< pin 10 lock bit */ 211 #define GPIO_LOCK_LK11 BIT(11) /*!< pin 11 lock bit */ 212 #define GPIO_LOCK_LK12 BIT(12) /*!< pin 12 lock bit */ 213 #define GPIO_LOCK_LK13 BIT(13) /*!< pin 13 lock bit */ 214 #define GPIO_LOCK_LK14 BIT(14) /*!< pin 14 lock bit */ 215 #define GPIO_LOCK_LK15 BIT(15) /*!< pin 15 lock bit */ 216 #define GPIO_LOCK_LKK BIT(16) /*!< pin sequence lock key */ 217 218 /* GPIO_SPD */ 219 #define GPIO_SPD_SPD0 BIT(0) /*!< pin 0 set very high output speed when MDx is 0b11 */ 220 #define GPIO_SPD_SPD1 BIT(1) /*!< pin 1 set very high output speed when MDx is 0b11 */ 221 #define GPIO_SPD_SPD2 BIT(2) /*!< pin 2 set very high output speed when MDx is 0b11 */ 222 #define GPIO_SPD_SPD3 BIT(3) /*!< pin 3 set very high output speed when MDx is 0b11 */ 223 #define GPIO_SPD_SPD4 BIT(4) /*!< pin 4 set very high output speed when MDx is 0b11 */ 224 #define GPIO_SPD_SPD5 BIT(5) /*!< pin 5 set very high output speed when MDx is 0b11 */ 225 #define GPIO_SPD_SPD6 BIT(6) /*!< pin 6 set very high output speed when MDx is 0b11 */ 226 #define GPIO_SPD_SPD7 BIT(7) /*!< pin 7 set very high output speed when MDx is 0b11 */ 227 #define GPIO_SPD_SPD8 BIT(8) /*!< pin 8 set very high output speed when MDx is 0b11 */ 228 #define GPIO_SPD_SPD9 BIT(9) /*!< pin 9 set very high output speed when MDx is 0b11 */ 229 #define GPIO_SPD_SPD10 BIT(10) /*!< pin 10 set very high output speed when MDx is 0b11 */ 230 #define GPIO_SPD_SPD11 BIT(11) /*!< pin 11 set very high output speed when MDx is 0b11 */ 231 #define GPIO_SPD_SPD12 BIT(12) /*!< pin 12 set very high output speed when MDx is 0b11 */ 232 #define GPIO_SPD_SPD13 BIT(13) /*!< pin 13 set very high output speed when MDx is 0b11 */ 233 #define GPIO_SPD_SPD14 BIT(14) /*!< pin 14 set very high output speed when MDx is 0b11 */ 234 #define GPIO_SPD_SPD15 BIT(15) /*!< pin 15 set very high output speed when MDx is 0b11 */ 235 236 /* AFIO_EC */ 237 #define AFIO_EC_PIN BITS(0,3) /*!< event output pin selection */ 238 #define AFIO_EC_PORT BITS(4,6) /*!< event output port selection */ 239 #define AFIO_EC_EOE BIT(7) /*!< event output enable */ 240 241 /* AFIO_PCF0 */ 242 /* memory map and bit definitions */ 243 #define AFIO_PCF0_SPI0_REMAP BIT(0) /*!< SPI0 remapping */ 244 #define AFIO_PCF0_I2C0_REMAP BIT(1) /*!< I2C0 remapping */ 245 #define AFIO_PCF0_USART0_REMAP BIT(2) /*!< USART0 remapping */ 246 #define AFIO_PCF0_USART1_REMAP BIT(3) /*!< USART1 remapping */ 247 #define AFIO_PCF0_USART2_REMAP BITS(4,5) /*!< USART2 remapping */ 248 #define AFIO_PCF0_TIMER0_REMAP BITS(6,7) /*!< TIMER0 remapping */ 249 #define AFIO_PCF0_TIMER1_REMAP BITS(8,9) /*!< TIMER1 remapping */ 250 #define AFIO_PCF0_TIMER2_REMAP BITS(10,11) /*!< TIMER2 remapping */ 251 #define AFIO_PCF0_TIMER3_REMAP BIT(12) /*!< TIMER3 remapping */ 252 #define AFIO_PCF0_PD01_REMAP BIT(15) /*!< port D0/port D1 mapping on OSC_IN/OSC_OUT */ 253 #define AFIO_PCF0_TIMER4CH3_IREMAP BIT(16) /*!< TIMER4 channel3 internal remapping */ 254 #define AFIO_PCF0_ADC0_ETRGRT_REMAP BIT(18) /*!< ADC 0 external trigger routine conversion remapping */ 255 #define AFIO_PCF0_ADC1_ETRGRT_REMAP BIT(20) /*!< ADC 1 external trigger routine conversion remapping */ 256 #define AFIO_PCF0_SWJ_CFG BITS(24,26) /*!< serial wire JTAG configuration */ 257 #define AFIO_PCF0_SPI2_REMAP BIT(28) /*!< SPI2/I2S2 remapping */ 258 #define AFIO_PCF0_TIMER1ITI1_REMAP BIT(29) /*!< TIMER1 internal trigger 1 remapping */ 259 260 /* AFIO_EXTISS0 */ 261 #define AFIO_EXTI0_SS BITS(0,3) /*!< EXTI 0 sources selection */ 262 #define AFIO_EXTI1_SS BITS(4,7) /*!< EXTI 1 sources selection */ 263 #define AFIO_EXTI2_SS BITS(8,11) /*!< EXTI 2 sources selection */ 264 #define AFIO_EXTI3_SS BITS(12,15) /*!< EXTI 3 sources selection */ 265 266 /* AFIO_EXTISS1 */ 267 #define AFIO_EXTI4_SS BITS(0,3) /*!< EXTI 4 sources selection */ 268 #define AFIO_EXTI5_SS BITS(4,7) /*!< EXTI 5 sources selection */ 269 #define AFIO_EXTI6_SS BITS(8,11) /*!< EXTI 6 sources selection */ 270 #define AFIO_EXTI7_SS BITS(12,15) /*!< EXTI 7 sources selection */ 271 272 /* AFIO_EXTISS2 */ 273 #define AFIO_EXTI8_SS BITS(0,3) /*!< EXTI 8 sources selection */ 274 #define AFIO_EXTI9_SS BITS(4,7) /*!< EXTI 9 sources selection */ 275 #define AFIO_EXTI10_SS BITS(8,11) /*!< EXTI 10 sources selection */ 276 #define AFIO_EXTI11_SS BITS(12,15) /*!< EXTI 11 sources selection */ 277 278 /* AFIO_EXTISS3 */ 279 #define AFIO_EXTI12_SS BITS(0,3) /*!< EXTI 12 sources selection */ 280 #define AFIO_EXTI13_SS BITS(4,7) /*!< EXTI 13 sources selection */ 281 #define AFIO_EXTI14_SS BITS(8,11) /*!< EXTI 14 sources selection */ 282 #define AFIO_EXTI15_SS BITS(12,15) /*!< EXTI 15 sources selection */ 283 284 /* AFIO_PCF1 */ 285 #define AFIO_PCF1_TIMER8_REMAP BIT(5) /*!< TIMER8 remapping */ 286 #define AFIO_PCF1_EXMC_NADV BIT(10) /*!< EXMC_NADV connect/disconnect */ 287 #define AFIO_PCF1_CTC_REMAP BITS(11,12) /*!< CTC remapping */ 288 289 /* AFIO_CPSCTL */ 290 #define AFIO_CPSCTL_CPS_EN BIT(0) /*!< I/O compensation cell enable */ 291 #define AFIO_CPSCTL_CPS_RDY BIT(8) /*!< I/O compensation cell is ready or not */ 292 293 /* constants definitions */ 294 typedef FlagStatus bit_status; 295 296 /* GPIO mode values set */ 297 #define GPIO_MODE_SET(n, mode) ((uint32_t)((uint32_t)(mode) << (4U * (n)))) 298 #define GPIO_MODE_MASK(n) (0xFU << (4U * (n))) 299 300 /* GPIO mode definitions */ 301 #define GPIO_MODE_AIN ((uint8_t)0x00U) /*!< analog input mode */ 302 #define GPIO_MODE_IN_FLOATING ((uint8_t)0x04U) /*!< floating input mode */ 303 #define GPIO_MODE_IPD ((uint8_t)0x28U) /*!< pull-down input mode */ 304 #define GPIO_MODE_IPU ((uint8_t)0x48U) /*!< pull-up input mode */ 305 #define GPIO_MODE_OUT_OD ((uint8_t)0x14U) /*!< GPIO output with open-drain */ 306 #define GPIO_MODE_OUT_PP ((uint8_t)0x10U) /*!< GPIO output with push-pull */ 307 #define GPIO_MODE_AF_OD ((uint8_t)0x1CU) /*!< AFIO output with open-drain */ 308 #define GPIO_MODE_AF_PP ((uint8_t)0x18U) /*!< AFIO output with push-pull */ 309 310 /* GPIO output max speed value */ 311 #define GPIO_OSPEED_10MHZ ((uint8_t)0x01U) /*!< output max speed 10MHz */ 312 #define GPIO_OSPEED_2MHZ ((uint8_t)0x02U) /*!< output max speed 2MHz */ 313 #define GPIO_OSPEED_50MHZ ((uint8_t)0x03U) /*!< output max speed 50MHz */ 314 #define GPIO_OSPEED_MAX ((uint8_t)0x04U) /*!< GPIO very high output speed, max speed more than 50MHz */ 315 316 /* GPIO event output port definitions */ 317 #define GPIO_EVENT_PORT_GPIOA ((uint8_t)0x00U) /*!< event output port A */ 318 #define GPIO_EVENT_PORT_GPIOB ((uint8_t)0x01U) /*!< event output port B */ 319 #define GPIO_EVENT_PORT_GPIOC ((uint8_t)0x02U) /*!< event output port C */ 320 #define GPIO_EVENT_PORT_GPIOD ((uint8_t)0x03U) /*!< event output port D */ 321 #define GPIO_EVENT_PORT_GPIOE ((uint8_t)0x04U) /*!< event output port E */ 322 323 /* GPIO output port source definitions */ 324 #define GPIO_PORT_SOURCE_GPIOA ((uint8_t)0x00U) /*!< output port source A */ 325 #define GPIO_PORT_SOURCE_GPIOB ((uint8_t)0x01U) /*!< output port source B */ 326 #define GPIO_PORT_SOURCE_GPIOC ((uint8_t)0x02U) /*!< output port source C */ 327 #define GPIO_PORT_SOURCE_GPIOD ((uint8_t)0x03U) /*!< output port source D */ 328 #define GPIO_PORT_SOURCE_GPIOE ((uint8_t)0x04U) /*!< output port source E */ 329 330 /* GPIO event output pin definitions */ 331 #define GPIO_EVENT_PIN_0 ((uint8_t)0x00U) /*!< GPIO event pin 0 */ 332 #define GPIO_EVENT_PIN_1 ((uint8_t)0x01U) /*!< GPIO event pin 1 */ 333 #define GPIO_EVENT_PIN_2 ((uint8_t)0x02U) /*!< GPIO event pin 2 */ 334 #define GPIO_EVENT_PIN_3 ((uint8_t)0x03U) /*!< GPIO event pin 3 */ 335 #define GPIO_EVENT_PIN_4 ((uint8_t)0x04U) /*!< GPIO event pin 4 */ 336 #define GPIO_EVENT_PIN_5 ((uint8_t)0x05U) /*!< GPIO event pin 5 */ 337 #define GPIO_EVENT_PIN_6 ((uint8_t)0x06U) /*!< GPIO event pin 6 */ 338 #define GPIO_EVENT_PIN_7 ((uint8_t)0x07U) /*!< GPIO event pin 7 */ 339 #define GPIO_EVENT_PIN_8 ((uint8_t)0x08U) /*!< GPIO event pin 8 */ 340 #define GPIO_EVENT_PIN_9 ((uint8_t)0x09U) /*!< GPIO event pin 9 */ 341 #define GPIO_EVENT_PIN_10 ((uint8_t)0x0AU) /*!< GPIO event pin 10 */ 342 #define GPIO_EVENT_PIN_11 ((uint8_t)0x0BU) /*!< GPIO event pin 11 */ 343 #define GPIO_EVENT_PIN_12 ((uint8_t)0x0CU) /*!< GPIO event pin 12 */ 344 #define GPIO_EVENT_PIN_13 ((uint8_t)0x0DU) /*!< GPIO event pin 13 */ 345 #define GPIO_EVENT_PIN_14 ((uint8_t)0x0EU) /*!< GPIO event pin 14 */ 346 #define GPIO_EVENT_PIN_15 ((uint8_t)0x0FU) /*!< GPIO event pin 15 */ 347 348 /* GPIO output pin source definitions */ 349 #define GPIO_PIN_SOURCE_0 ((uint8_t)0x00U) /*!< GPIO pin source 0 */ 350 #define GPIO_PIN_SOURCE_1 ((uint8_t)0x01U) /*!< GPIO pin source 1 */ 351 #define GPIO_PIN_SOURCE_2 ((uint8_t)0x02U) /*!< GPIO pin source 2 */ 352 #define GPIO_PIN_SOURCE_3 ((uint8_t)0x03U) /*!< GPIO pin source 3 */ 353 #define GPIO_PIN_SOURCE_4 ((uint8_t)0x04U) /*!< GPIO pin source 4 */ 354 #define GPIO_PIN_SOURCE_5 ((uint8_t)0x05U) /*!< GPIO pin source 5 */ 355 #define GPIO_PIN_SOURCE_6 ((uint8_t)0x06U) /*!< GPIO pin source 6 */ 356 #define GPIO_PIN_SOURCE_7 ((uint8_t)0x07U) /*!< GPIO pin source 7 */ 357 #define GPIO_PIN_SOURCE_8 ((uint8_t)0x08U) /*!< GPIO pin source 8 */ 358 #define GPIO_PIN_SOURCE_9 ((uint8_t)0x09U) /*!< GPIO pin source 9 */ 359 #define GPIO_PIN_SOURCE_10 ((uint8_t)0x0AU) /*!< GPIO pin source 10 */ 360 #define GPIO_PIN_SOURCE_11 ((uint8_t)0x0BU) /*!< GPIO pin source 11 */ 361 #define GPIO_PIN_SOURCE_12 ((uint8_t)0x0CU) /*!< GPIO pin source 12 */ 362 #define GPIO_PIN_SOURCE_13 ((uint8_t)0x0DU) /*!< GPIO pin source 13 */ 363 #define GPIO_PIN_SOURCE_14 ((uint8_t)0x0EU) /*!< GPIO pin source 14 */ 364 #define GPIO_PIN_SOURCE_15 ((uint8_t)0x0FU) /*!< GPIO pin source 15 */ 365 366 /* GPIO pin definitions */ 367 #define GPIO_PIN_0 BIT(0) /*!< GPIO pin 0 */ 368 #define GPIO_PIN_1 BIT(1) /*!< GPIO pin 1 */ 369 #define GPIO_PIN_2 BIT(2) /*!< GPIO pin 2 */ 370 #define GPIO_PIN_3 BIT(3) /*!< GPIO pin 3 */ 371 #define GPIO_PIN_4 BIT(4) /*!< GPIO pin 4 */ 372 #define GPIO_PIN_5 BIT(5) /*!< GPIO pin 5 */ 373 #define GPIO_PIN_6 BIT(6) /*!< GPIO pin 6 */ 374 #define GPIO_PIN_7 BIT(7) /*!< GPIO pin 7 */ 375 #define GPIO_PIN_8 BIT(8) /*!< GPIO pin 8 */ 376 #define GPIO_PIN_9 BIT(9) /*!< GPIO pin 9 */ 377 #define GPIO_PIN_10 BIT(10) /*!< GPIO pin 10 */ 378 #define GPIO_PIN_11 BIT(11) /*!< GPIO pin 11 */ 379 #define GPIO_PIN_12 BIT(12) /*!< GPIO pin 12 */ 380 #define GPIO_PIN_13 BIT(13) /*!< GPIO pin 13 */ 381 #define GPIO_PIN_14 BIT(14) /*!< GPIO pin 14 */ 382 #define GPIO_PIN_15 BIT(15) /*!< GPIO pin 15 */ 383 #define GPIO_PIN_ALL BITS(0,15) /*!< GPIO pin all */ 384 385 /* AFIO remap */ 386 #define PCF0_USART2_REMAP(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) /*!< USART2 remapping */ 387 #define PCF0_TIMER0_REMAP(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) /*!< TIMER0 remapping */ 388 #define PCF0_TIMER1_REMAP(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< TIMER1 remapping */ 389 #define PCF0_TIMER2_REMAP(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< TIMER2 remapping */ 390 #define PCF0_SWJ_CFG(regval) (BITS(24,26) & ((uint32_t)(regval) << 24)) /*!< serial wire JTAG configuration */ 391 #define PCF1_CTC_REMAP(regval) (BITS(11,12) & ((uint32_t)(regval) << 11)) /*!< CTC remapping */ 392 393 /* GPIO remap definitions */ 394 #define GPIO_SPI0_REMAP AFIO_PCF0_SPI0_REMAP /*!< SPI0 remapping */ 395 #define GPIO_I2C0_REMAP AFIO_PCF0_I2C0_REMAP /*!< I2C0 remapping */ 396 #define GPIO_USART0_REMAP AFIO_PCF0_USART0_REMAP /*!< USART0 remapping */ 397 #define GPIO_USART1_REMAP AFIO_PCF0_USART1_REMAP /*!< USART1 remapping */ 398 #define GPIO_USART2_PARTIAL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(1)) /*!< USART2 partial remapping */ 399 #define GPIO_USART2_FULL_REMAP ((uint32_t)0x00140000U | PCF0_USART2_REMAP(3)) /*!< USART2 full remapping */ 400 #define GPIO_TIMER0_PARTIAL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(1)) /*!< TIMER0 partial remapping */ 401 #define GPIO_TIMER0_FULL_REMAP ((uint32_t)0x00160000U | PCF0_TIMER0_REMAP(3)) /*!< TIMER0 full remapping */ 402 #define GPIO_TIMER1_PARTIAL_REMAP0 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(1)) /*!< TIMER1 partial remapping */ 403 #define GPIO_TIMER1_PARTIAL_REMAP1 ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(2)) /*!< TIMER1 partial remapping */ 404 #define GPIO_TIMER1_FULL_REMAP ((uint32_t)0x00180000U | PCF0_TIMER1_REMAP(3)) /*!< TIMER1 full remapping */ 405 #define GPIO_TIMER2_PARTIAL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(2)) /*!< TIMER2 partial remapping */ 406 #define GPIO_TIMER2_FULL_REMAP ((uint32_t)0x001A0000U | PCF0_TIMER2_REMAP(3)) /*!< TIMER2 full remapping */ 407 #define GPIO_TIMER3_REMAP AFIO_PCF0_TIMER3_REMAP /*!< TIMER3 remapping */ 408 #define GPIO_PD01_REMAP AFIO_PCF0_PD01_REMAP /*!< PD01 remapping */ 409 #define GPIO_TIMER4CH3_IREMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER4CH3_IREMAP >> 16)) /*!< TIMER4 channel3 internal remapping */ 410 #define GPIO_ADC0_ETRGRT_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC0_ETRGRT_REMAP >> 16)) /*!< ADC 0 external trigger routine conversion remapping */ 411 #define GPIO_ADC1_ETRGRT_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_ADC1_ETRGRT_REMAP >> 16)) /*!< ADC 1 external trigger routine conversion remapping */ 412 #define GPIO_SWJ_NONJTRST_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(1) >> 16)) /*!< full SWJ(JTAG-DP + SW-DP),but without NJTRST */ 413 #define GPIO_SWJ_SWDPENABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(2) >> 16)) /*!< JTAG-DP disabled and SW-DP enabled */ 414 #define GPIO_SWJ_DISABLE_REMAP ((uint32_t)0x00300000U | (PCF0_SWJ_CFG(4) >> 16)) /*!< JTAG-DP disabled and SW-DP disabled */ 415 #define GPIO_SPI2_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_SPI2_REMAP >> 16)) /*!< SPI2 remapping */ 416 #define GPIO_TIMER1ITI1_REMAP ((uint32_t)0x00200000U | (AFIO_PCF0_TIMER1ITI1_REMAP >> 16)) /*!< TIMER1 internal trigger 1 remapping */ 417 #define GPIO_TIMER8_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_TIMER8_REMAP) /*!< TIMER8 remapping */ 418 #define GPIO_EXMC_NADV_REMAP ((uint32_t)0x80000000U | AFIO_PCF1_EXMC_NADV) /*!< EXMC_NADV connect/disconnect */ 419 #define GPIO_CTC_REMAP0 ((uint32_t)0x801B0000U | PCF1_CTC_REMAP(1)) /*!< CTC remapping(PD15)*/ 420 421 /* I/O compensation cell enable/disable */ 422 #define GPIO_COMPENSATION_ENABLE AFIO_CPSCTL_CPS_EN /*!< I/O compensation cell is enable */ 423 #define GPIO_COMPENSATION_DISABLE ((uint32_t)0x00000000U) /*!< I/O compensation cell is disable */ 424 425 /* function declarations */ 426 /* reset GPIO port */ 427 void gpio_deinit(uint32_t gpio_periph); 428 /* reset alternate function I/O(AFIO) */ 429 void gpio_afio_deinit(void); 430 /* GPIO parameter initialization */ 431 void gpio_init(uint32_t gpio_periph, uint32_t mode, uint32_t speed, uint32_t pin); 432 433 /* set GPIO pin bit */ 434 void gpio_bit_set(uint32_t gpio_periph, uint32_t pin); 435 /* reset GPIO pin bit */ 436 void gpio_bit_reset(uint32_t gpio_periph, uint32_t pin); 437 /* write data to the specified GPIO pin */ 438 void gpio_bit_write(uint32_t gpio_periph, uint32_t pin, bit_status bit_value); 439 /* write data to the specified GPIO port */ 440 void gpio_port_write(uint32_t gpio_periph, uint16_t data); 441 442 /* get GPIO pin input status */ 443 FlagStatus gpio_input_bit_get(uint32_t gpio_periph, uint32_t pin); 444 /* get GPIO port input status */ 445 uint16_t gpio_input_port_get(uint32_t gpio_periph); 446 /* get GPIO pin output status */ 447 FlagStatus gpio_output_bit_get(uint32_t gpio_periph, uint32_t pin); 448 /* get GPIO port output status */ 449 uint16_t gpio_output_port_get(uint32_t gpio_periph); 450 451 /* configure GPIO pin remap */ 452 void gpio_pin_remap_config(uint32_t remap, ControlStatus newvalue); 453 454 /* select GPIO pin exti sources */ 455 void gpio_exti_source_select(uint8_t output_port, uint8_t output_pin); 456 /* configure GPIO pin event output */ 457 void gpio_event_output_config(uint8_t output_port, uint8_t output_pin); 458 /* enable GPIO pin event output */ 459 void gpio_event_output_enable(void); 460 /* disable GPIO pin event output */ 461 void gpio_event_output_disable(void); 462 463 /* lock GPIO pin bit */ 464 void gpio_pin_lock(uint32_t gpio_periph, uint32_t pin); 465 466 /* configure the I/O compensation cell */ 467 void gpio_compensation_config(uint32_t compensation); 468 /* check the I/O compensation cell is ready or not */ 469 FlagStatus gpio_compensation_flag_get(void); 470 471 #endif /* GD32E10X_GPIO_H */ 472
