1 /*! 2 \file gd32e10x_exmc.h 3 \brief definitions for the EXMC 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_EXMC_H 39 #define GD32E10X_EXMC_H 40 41 #include "gd32e10x.h" 42 43 /* EXMC definitions */ 44 #define EXMC (EXMC_BASE) /*!< EXMC register base address */ 45 46 /* registers definitions */ 47 /* NOR/PSRAM */ 48 #define EXMC_SNCTL REG32(EXMC + 0x00U) /*!< EXMC SRAM/NOR flash control register */ 49 #define EXMC_SNTCFG REG32(EXMC + 0x04U) /*!< EXMC SRAM/NOR flash timing configuration register */ 50 #define EXMC_SNWTCFG REG32(EXMC + 0x104U) /*!< EXMC SRAM/NOR flash write timing configuration register */ 51 52 /* bits definitions */ 53 /* EXMC_SNCTL */ 54 #define EXMC_SNCTL_NRBKEN BIT(0) /*!< NOR region enable */ 55 #define EXMC_SNCTL_NRMUX BIT(1) /*!< NOR region memory address/data multiplexing */ 56 #define EXMC_SNCTL_NRTP BITS(2,3) /*!< NOR region memory type */ 57 #define EXMC_SNCTL_NRW BITS(4,5) /*!< NOR region memory data bus width */ 58 #define EXMC_SNCTL_NREN BIT(6) /*!< NOR flash access enable */ 59 #define EXMC_SNCTL_SBRSTEN BIT(8) /*!< synchronous burst enable */ 60 #define EXMC_SNCTL_NRWTPOL BIT(9) /*!< NWAIT signal polarity */ 61 #define EXMC_SNCTL_WRAPEN BIT(10) /*!< wrapped burst mode enable */ 62 #define EXMC_SNCTL_NRWTCFG BIT(11) /*!< NWAIT signal configuration, only work in synchronous mode */ 63 #define EXMC_SNCTL_WREN BIT(12) /*!< write enable */ 64 #define EXMC_SNCTL_NRWTEN BIT(13) /*!< NWAIT signal enable */ 65 #define EXMC_SNCTL_EXMODEN BIT(14) /*!< extended mode enable */ 66 #define EXMC_SNCTL_ASYNCWAIT BIT(15) /*!< asynchronous wait */ 67 #define EXMC_SNCTL_CPS BITS(16,18) /*!< CRAM page size */ 68 #define EXMC_SNCTL_SYNCWR BIT(19) /*!< synchronous write */ 69 70 /* EXMC_SNTCFG */ 71 #define EXMC_SNTCFG_ASET BITS(0,3) /*!< address setup time */ 72 #define EXMC_SNTCFG_AHLD BITS(4,7) /*!< address hold time */ 73 #define EXMC_SNTCFG_DSET BITS(8,15) /*!< data setup time */ 74 #define EXMC_SNTCFG_BUSLAT BITS(16,19) /*!< bus latency */ 75 #define EXMC_SNTCFG_CKDIV BITS(20,23) /*!< synchronous clock divide ratio */ 76 #define EXMC_SNTCFG_DLAT BITS(24,27) /*!< data latency for NOR flash */ 77 #define EXMC_SNTCFG_ASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 78 79 /* EXMC_SNWTCFG */ 80 #define EXMC_SNWTCFG_WASET BITS(0,3) /*!< address setup time */ 81 #define EXMC_SNWTCFG_WAHLD BITS(4,7) /*!< address hold time */ 82 #define EXMC_SNWTCFG_WDSET BITS(8,15) /*!< data setup time */ 83 #define EXMC_SNWTCFG_WBUSLAT BITS(16,19) /*!< bus latency */ 84 #define EXMC_SNWTCFG_WASYNCMOD BITS(28,29) /*!< asynchronous access mode */ 85 86 /* constants definitions */ 87 /* EXMC NOR/SRAM timing initialize struct */ 88 typedef struct 89 { 90 uint32_t asyn_access_mode; /*!< asynchronous access mode */ 91 uint32_t syn_data_latency; /*!< configure the data latency */ 92 uint32_t syn_clk_division; /*!< configure the clock divide ratio */ 93 uint32_t bus_latency; /*!< configure the bus latency, the value can be 1 ~ 16, can't be 0 */ 94 uint32_t asyn_data_setuptime; /*!< configure the data setup time, the value can be 2 ~ 256, can't be 0 */ 95 uint32_t asyn_address_holdtime; /*!< configure the address hold time, the value can be 2 ~ 16, can't be 0 */ 96 uint32_t asyn_address_setuptime; /*!< configure the address setup time, the value can be 1 ~ 16, can't be 0 */ 97 }exmc_norsram_timing_parameter_struct; 98 99 /* EXMC NOR/SRAM initialize struct */ 100 typedef struct 101 { 102 uint32_t write_mode; /*!< the write mode, synchronous mode or asynchronous mode */ 103 uint32_t extended_mode; /*!< enable or disable the extended mode */ 104 uint32_t asyn_wait; /*!< enable or disable the asynchronous wait function */ 105 uint32_t nwait_signal; /*!< enable or disable the NWAIT signal while in synchronous bust mode */ 106 uint32_t memory_write; /*!< enable or disable the write operation */ 107 uint32_t nwait_config; /*!< NWAIT signal configuration */ 108 uint32_t wrap_burst_mode; /*!< enable or disable the wrap burst mode */ 109 uint32_t nwait_polarity; /*!< specifies the polarity of NWAIT signal from memory */ 110 uint32_t burst_mode; /*!< enable or disable the burst mode */ 111 uint32_t databus_width; /*!< specifies the databus width of external memory */ 112 uint32_t memory_type; /*!< specifies the type of external memory */ 113 uint32_t address_data_mux; /*!< specifies whether the data bus and address bus are multiplexed */ 114 exmc_norsram_timing_parameter_struct* read_write_timing; /*!< timing parameters for read and write if the extended mode is not used or the timing 115 parameters for read if the extended mode is used */ 116 exmc_norsram_timing_parameter_struct* write_timing; /*!< timing parameters for write when the extended mode is used */ 117 }exmc_norsram_parameter_struct; 118 119 /* CRAM page size */ 120 #define SNCTL_CPS(regval) (BITS(16,18) & ((uint32_t)(regval) << 16)) 121 #define EXMC_CRAM_AUTO_SPLIT SNCTL_CPS(0) /*!< automatic burst split on page boundary crossing */ 122 #define EXMC_CRAM_PAGE_SIZE_128_BYTES SNCTL_CPS(1) /*!< page size is 128 bytes */ 123 #define EXMC_CRAM_PAGE_SIZE_256_BYTES SNCTL_CPS(2) /*!< page size is 256 bytes */ 124 #define EXMC_CRAM_PAGE_SIZE_512_BYTES SNCTL_CPS(3) /*!< page size is 512 bytes */ 125 #define EXMC_CRAM_PAGE_SIZE_1024_BYTES SNCTL_CPS(4) /*!< page size is 1024 bytes */ 126 127 /* NOR region memory data bus width */ 128 #define SNCTL_NRW(regval) (BITS(4,5) & ((uint32_t)(regval) << 4)) 129 #define EXMC_NOR_DATABUS_WIDTH_8B SNCTL_NRW(0) /*!< NOR data width 8 bits */ 130 #define EXMC_NOR_DATABUS_WIDTH_16B SNCTL_NRW(1) /*!< NOR data width 16 bits */ 131 132 /* NOR region memory type */ 133 #define SNCTL_NRTP(regval) (BITS(2,3) & ((uint32_t)(regval) << 2)) 134 #define EXMC_MEMORY_TYPE_SRAM SNCTL_NRTP(0) /*!< SRAM,ROM */ 135 #define EXMC_MEMORY_TYPE_PSRAM SNCTL_NRTP(1) /*!< PSRAM,CRAM */ 136 #define EXMC_MEMORY_TYPE_NOR SNCTL_NRTP(2) /*!< NOR flash */ 137 138 /* asynchronous access mode */ 139 #define SNTCFG_ASYNCMOD(regval) (BITS(28,29) & ((uint32_t)(regval) << 28)) 140 #define EXMC_ACCESS_MODE_A SNTCFG_ASYNCMOD(0) /*!< mode A access */ 141 #define EXMC_ACCESS_MODE_B SNTCFG_ASYNCMOD(1) /*!< mode B access */ 142 #define EXMC_ACCESS_MODE_C SNTCFG_ASYNCMOD(2) /*!< mode C access */ 143 #define EXMC_ACCESS_MODE_D SNTCFG_ASYNCMOD(3) /*!< mode D access */ 144 145 /* data latency for NOR flash */ 146 #define SNTCFG_DLAT(regval) (BITS(24,27) & ((uint32_t)(regval) << 24)) 147 #define EXMC_DATALAT_2_CLK SNTCFG_DLAT(0) /*!< data latency 2 EXMC_CLK */ 148 #define EXMC_DATALAT_3_CLK SNTCFG_DLAT(1) /*!< data latency 3 EXMC_CLK */ 149 #define EXMC_DATALAT_4_CLK SNTCFG_DLAT(2) /*!< data latency 4 EXMC_CLK */ 150 #define EXMC_DATALAT_5_CLK SNTCFG_DLAT(3) /*!< data latency 5 EXMC_CLK */ 151 #define EXMC_DATALAT_6_CLK SNTCFG_DLAT(4) /*!< data latency 6 EXMC_CLK */ 152 #define EXMC_DATALAT_7_CLK SNTCFG_DLAT(5) /*!< data latency 7 EXMC_CLK */ 153 #define EXMC_DATALAT_8_CLK SNTCFG_DLAT(6) /*!< data latency 8 EXMC_CLK */ 154 #define EXMC_DATALAT_9_CLK SNTCFG_DLAT(7) /*!< data latency 9 EXMC_CLK */ 155 #define EXMC_DATALAT_10_CLK SNTCFG_DLAT(8) /*!< data latency 10 EXMC_CLK */ 156 #define EXMC_DATALAT_11_CLK SNTCFG_DLAT(9) /*!< data latency 11 EXMC_CLK */ 157 #define EXMC_DATALAT_12_CLK SNTCFG_DLAT(10) /*!< data latency 12 EXMC_CLK */ 158 #define EXMC_DATALAT_13_CLK SNTCFG_DLAT(11) /*!< data latency 13 EXMC_CLK */ 159 #define EXMC_DATALAT_14_CLK SNTCFG_DLAT(12) /*!< data latency 14 EXMC_CLK */ 160 #define EXMC_DATALAT_15_CLK SNTCFG_DLAT(13) /*!< data latency 15 EXMC_CLK */ 161 #define EXMC_DATALAT_16_CLK SNTCFG_DLAT(14) /*!< data latency 16 EXMC_CLK */ 162 #define EXMC_DATALAT_17_CLK SNTCFG_DLAT(15) /*!< data latency 17 EXMC_CLK */ 163 164 /* synchronous clock divide ratio */ 165 #define SNTCFG_CKDIV(regval) (BITS(20,23) & ((uint32_t)(regval) << 20)) 166 #define EXMC_SYN_CLOCK_RATIO_DISABLE SNTCFG_CKDIV(0) /*!< EXMC_CLK disable */ 167 #define EXMC_SYN_CLOCK_RATIO_2_CLK SNTCFG_CKDIV(1) /*!< frequency EXMC_CLK = HCLK/2 */ 168 #define EXMC_SYN_CLOCK_RATIO_3_CLK SNTCFG_CKDIV(2) /*!< frequency EXMC_CLK = HCLK/3 */ 169 #define EXMC_SYN_CLOCK_RATIO_4_CLK SNTCFG_CKDIV(3) /*!< frequency EXMC_CLK = HCLK/4 */ 170 #define EXMC_SYN_CLOCK_RATIO_5_CLK SNTCFG_CKDIV(4) /*!< frequency EXMC_CLK = HCLK/5 */ 171 #define EXMC_SYN_CLOCK_RATIO_6_CLK SNTCFG_CKDIV(5) /*!< frequency EXMC_CLK = HCLK/6 */ 172 #define EXMC_SYN_CLOCK_RATIO_7_CLK SNTCFG_CKDIV(6) /*!< frequency EXMC_CLK = HCLK/7 */ 173 #define EXMC_SYN_CLOCK_RATIO_8_CLK SNTCFG_CKDIV(7) /*!< frequency EXMC_CLK = HCLK/8 */ 174 #define EXMC_SYN_CLOCK_RATIO_9_CLK SNTCFG_CKDIV(8) /*!< frequency EXMC_CLK = HCLK/9 */ 175 #define EXMC_SYN_CLOCK_RATIO_10_CLK SNTCFG_CKDIV(9) /*!< frequency EXMC_CLK = HCLK/10 */ 176 #define EXMC_SYN_CLOCK_RATIO_11_CLK SNTCFG_CKDIV(10) /*!< frequency EXMC_CLK = HCLK/11 */ 177 #define EXMC_SYN_CLOCK_RATIO_12_CLK SNTCFG_CKDIV(11) /*!< frequency EXMC_CLK = HCLK/12 */ 178 #define EXMC_SYN_CLOCK_RATIO_13_CLK SNTCFG_CKDIV(12) /*!< frequency EXMC_CLK = HCLK/13 */ 179 #define EXMC_SYN_CLOCK_RATIO_14_CLK SNTCFG_CKDIV(13) /*!< frequency EXMC_CLK = HCLK/14 */ 180 #define EXMC_SYN_CLOCK_RATIO_15_CLK SNTCFG_CKDIV(14) /*!< frequency EXMC_CLK = HCLK/15 */ 181 #define EXMC_SYN_CLOCK_RATIO_16_CLK SNTCFG_CKDIV(15) /*!< frequency EXMC_CLK = HCLK/16 */ 182 183 /* EXMC NOR/SRAM write mode */ 184 #define EXMC_ASYN_WRITE ((uint32_t)0x00000000U) /*!< asynchronous write mode */ 185 #define EXMC_SYN_WRITE EXMC_SNCTL_SYNCWR /*!< synchronous write mode */ 186 187 /* EXMC NWAIT signal configuration */ 188 #define EXMC_NWAIT_CONFIG_BEFORE ((uint32_t)0x00000000U) /*!< NWAIT signal is active one data cycle before wait state */ 189 #define EXMC_NWAIT_CONFIG_DURING EXMC_SNCTL_NRWTCFG /*!< NWAIT signal is active during wait state */ 190 191 /* EXMC NWAIT signal polarity configuration */ 192 #define EXMC_NWAIT_POLARITY_LOW ((uint32_t)0x00000000U) /*!< low level is active of NWAIT */ 193 #define EXMC_NWAIT_POLARITY_HIGH EXMC_SNCTL_NRWTPOL /*!< high level is active of NWAIT */ 194 195 /* function declarations */ 196 /* NOR/SRAM initializtion */ 197 /* deinitialize EXMC NOR/SRAM bank */ 198 void exmc_norsram_deinit(void); 199 /* exmc_norsram_parameter_struct parameter initialize */ 200 void exmc_norsram_struct_para_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 201 /* initialize EXMC NOR/SRAM bank */ 202 void exmc_norsram_init(exmc_norsram_parameter_struct* exmc_norsram_init_struct); 203 204 /* NOR/SRAM enable */ 205 /* enable EXMC NOR/SRAM bank */ 206 void exmc_norsram_enable(void); 207 /* disable EXMC NOR/SRAM bank */ 208 void exmc_norsram_disable(void); 209 210 /* NOR/SRAM configuration */ 211 /* configure CRAM page size */ 212 void exmc_norsram_page_size_config(uint32_t page_size); 213 214 #endif /* GD32E10X_EXMC_H */ 215
