1 /*! 2 \file gd32e10x_dma.h 3 \brief definitions for the DMA 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_DMA_H 39 #define GD32E10X_DMA_H 40 41 #include "gd32e10x.h" 42 43 /* DMA definitions */ 44 #define DMA0 (DMA_BASE) /*!< DMA0 base address */ 45 #define DMA1 (DMA_BASE + 0x0400U) /*!< DMA1 base address */ 46 47 /* registers definitions */ 48 #define DMA_INTF(dmax) REG32((dmax) + 0x00U) /*!< DMA interrupt flag register */ 49 #define DMA_INTC(dmax) REG32((dmax) + 0x04U) /*!< DMA interrupt flag clear register */ 50 #define DMA_CH0CTL(dmax) REG32((dmax) + 0x08U) /*!< DMA channel 0 control register */ 51 #define DMA_CH0CNT(dmax) REG32((dmax) + 0x0CU) /*!< DMA channel 0 counter register */ 52 #define DMA_CH0PADDR(dmax) REG32((dmax) + 0x10U) /*!< DMA channel 0 peripheral base address register */ 53 #define DMA_CH0MADDR(dmax) REG32((dmax) + 0x14U) /*!< DMA channel 0 memory base address register */ 54 #define DMA_CH1CTL(dmax) REG32((dmax) + 0x1CU) /*!< DMA channel 1 control register */ 55 #define DMA_CH1CNT(dmax) REG32((dmax) + 0x20U) /*!< DMA channel 1 counter register */ 56 #define DMA_CH1PADDR(dmax) REG32((dmax) + 0x24U) /*!< DMA channel 1 peripheral base address register */ 57 #define DMA_CH1MADDR(dmax) REG32((dmax) + 0x28U) /*!< DMA channel 1 memory base address register */ 58 #define DMA_CH2CTL(dmax) REG32((dmax) + 0x30U) /*!< DMA channel 2 control register */ 59 #define DMA_CH2CNT(dmax) REG32((dmax) + 0x34U) /*!< DMA channel 2 counter register */ 60 #define DMA_CH2PADDR(dmax) REG32((dmax) + 0x38U) /*!< DMA channel 2 peripheral base address register */ 61 #define DMA_CH2MADDR(dmax) REG32((dmax) + 0x3CU) /*!< DMA channel 2 memory base address register */ 62 #define DMA_CH3CTL(dmax) REG32((dmax) + 0x44U) /*!< DMA channel 3 control register */ 63 #define DMA_CH3CNT(dmax) REG32((dmax) + 0x48U) /*!< DMA channel 3 counter register */ 64 #define DMA_CH3PADDR(dmax) REG32((dmax) + 0x4CU) /*!< DMA channel 3 peripheral base address register */ 65 #define DMA_CH3MADDR(dmax) REG32((dmax) + 0x50U) /*!< DMA channel 3 memory base address register */ 66 #define DMA_CH4CTL(dmax) REG32((dmax) + 0x58U) /*!< DMA channel 4 control register */ 67 #define DMA_CH4CNT(dmax) REG32((dmax) + 0x5CU) /*!< DMA channel 4 counter register */ 68 #define DMA_CH4PADDR(dmax) REG32((dmax) + 0x60U) /*!< DMA channel 4 peripheral base address register */ 69 #define DMA_CH4MADDR(dmax) REG32((dmax) + 0x64U) /*!< DMA channel 4 memory base address register */ 70 #define DMA_CH5CTL(dmax) REG32((dmax) + 0x6CU) /*!< DMA channel 5 control register */ 71 #define DMA_CH5CNT(dmax) REG32((dmax) + 0x70U) /*!< DMA channel 5 counter register */ 72 #define DMA_CH5PADDR(dmax) REG32((dmax) + 0x74U) /*!< DMA channel 5 peripheral base address register */ 73 #define DMA_CH5MADDR(dmax) REG32((dmax) + 0x78U) /*!< DMA channel 5 memory base address register */ 74 #define DMA_CH6CTL(dmax) REG32((dmax) + 0x80U) /*!< DMA channel 6 control register */ 75 #define DMA_CH6CNT(dmax) REG32((dmax) + 0x84U) /*!< DMA channel 6 counter register */ 76 #define DMA_CH6PADDR(dmax) REG32((dmax) + 0x88U) /*!< DMA channel 6 peripheral base address register */ 77 #define DMA_CH6MADDR(dmax) REG32((dmax) + 0x8CU) /*!< DMA channel 6 memory base address register */ 78 79 /* bits definitions */ 80 /* DMA_INTF */ 81 #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ 82 #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ 83 #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ 84 #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ 85 86 /* DMA_INTC */ 87 #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ 88 #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ 89 #define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ 90 #define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ 91 92 /* DMA_CHxCTL, x=0..6 */ 93 #define DMA_CHXCTL_CHEN BIT(0) /*!< channel enable */ 94 #define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel full transfer finish interrupt */ 95 #define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel half transfer finish interrupt */ 96 #define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel error interrupt */ 97 #define DMA_CHXCTL_DIR BIT(4) /*!< transfer direction */ 98 #define DMA_CHXCTL_CMEN BIT(5) /*!< circular mode enable */ 99 #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ 100 #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ 101 #define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data width of peripheral */ 102 #define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data width of memory */ 103 #define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level */ 104 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ 105 106 /* DMA_CHxCNT,x=0..6 */ 107 #define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ 108 109 /* DMA_CHxPADDR,x=0..6 */ 110 #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ 111 112 /* DMA_CHxMADDR,x=0..6 */ 113 #define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ 114 115 /* constants definitions */ 116 /* DMA channel select */ 117 typedef enum 118 { 119 DMA_CH0 = 0, /*!< DMA channel 0 */ 120 DMA_CH1, /*!< DMA channel 1 */ 121 DMA_CH2, /*!< DMA channel 2 */ 122 DMA_CH3, /*!< DMA channel 3 */ 123 DMA_CH4, /*!< DMA channel 4 */ 124 DMA_CH5, /*!< DMA channel 5 */ 125 DMA_CH6 /*!< DMA channel 6 */ 126 } dma_channel_enum; 127 128 /* DMA initialize struct */ 129 typedef struct 130 { 131 uint32_t periph_addr; /*!< peripheral base address */ 132 uint32_t periph_width; /*!< transfer data size of peripheral */ 133 uint32_t memory_addr; /*!< memory base address */ 134 uint32_t memory_width; /*!< transfer data size of memory */ 135 uint32_t number; /*!< channel transfer number */ 136 uint32_t priority; /*!< channel priority level */ 137 uint8_t periph_inc; /*!< peripheral increasing mode */ 138 uint8_t memory_inc; /*!< memory increasing mode */ 139 uint8_t direction; /*!< channel data transfer direction */ 140 }dma_parameter_struct; 141 142 #define DMA_FLAG_ADD(flag, shift) ((flag) << ((shift) * 4U)) /*!< DMA channel flag shift */ 143 144 /* DMA_register address */ 145 #define DMA_CHCTL(dma, channel) REG32(((dma) + 0x08U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ 146 #define DMA_CHCNT(dma, channel) REG32(((dma) + 0x0CU) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ 147 #define DMA_CHPADDR(dma, channel) REG32(((dma) + 0x10U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ 148 #define DMA_CHMADDR(dma, channel) REG32(((dma) + 0x14U) + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ 149 150 /* DMA reset value */ 151 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ 152 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ 153 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ 154 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ 155 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ 156 DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ 157 158 /* DMA_INTF register */ 159 /* interrupt flag bits */ 160 #define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 161 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of channel */ 162 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of channel */ 163 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of channel */ 164 165 /* flag bits */ 166 #define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of channel */ 167 #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of channel */ 168 #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of channel */ 169 #define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of channel */ 170 171 /* DMA_CHxCTL register */ 172 /* interrupt enable bits */ 173 #define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for channel full transfer finish interrupt */ 174 #define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for channel half transfer finish interrupt */ 175 #define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for channel error interrupt */ 176 177 /* transfer direction */ 178 #define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x0000U) /*!< read from peripheral and write to memory */ 179 #define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x0001U) /*!< read from memory and write to peripheral */ 180 181 /* peripheral increasing mode */ 182 #define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of peripheral is fixed address mode */ 183 #define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of peripheral is increasing address mode */ 184 185 /* memory increasing mode */ 186 #define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x0000U) /*!< next address of memory is fixed address mode */ 187 #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x0001U) /*!< next address of memory is increasing address mode */ 188 189 /* transfer data size of peripheral */ 190 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((uint32_t)(regval) << 8)) /*!< transfer data size of peripheral */ 191 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0) /*!< transfer data size of peripheral is 8-bit */ 192 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1) /*!< transfer data size of peripheral is 16-bit */ 193 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2) /*!< transfer data size of peripheral is 32-bit */ 194 195 /* transfer data size of memory */ 196 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((uint32_t)(regval) << 10)) /*!< transfer data size of memory */ 197 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0) /*!< transfer data size of memory is 8-bit */ 198 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1) /*!< transfer data size of memory is 16-bit */ 199 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2) /*!< transfer data size of memory is 32-bit */ 200 201 /* channel priority level */ 202 #define CHCTL_PRIO(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) /*!< DMA channel priority level */ 203 #define DMA_PRIORITY_LOW CHCTL_PRIO(0) /*!< low priority */ 204 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1) /*!< medium priority */ 205 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2) /*!< high priority */ 206 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3) /*!< ultra high priority */ 207 208 /* DMA_CHxCNT register */ 209 /* transfer counter */ 210 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ 211 212 /* function declarations */ 213 /* DMA deinitialization and initialization functions */ 214 /* deinitialize DMA a channel registers */ 215 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx); 216 /* initialize the parameters of DMA struct with the default values */ 217 void dma_struct_para_init(dma_parameter_struct* init_struct); 218 /* initialize DMA channel */ 219 void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct); 220 /* enable DMA circulation mode */ 221 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx); 222 /* disable DMA circulation mode */ 223 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx); 224 /* enable memory to memory mode */ 225 void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx); 226 /* disable memory to memory mode */ 227 void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx); 228 /* enable DMA channel */ 229 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx); 230 /* disable DMA channel */ 231 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx); 232 233 /* DMA configuration functions */ 234 /* set DMA peripheral base address */ 235 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); 236 /* set DMA memory base address */ 237 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address); 238 /* set the number of remaining data to be transferred by the DMA */ 239 void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number); 240 /* get the number of remaining data to be transferred by the DMA */ 241 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx); 242 /* configure priority level of DMA channel */ 243 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority); 244 /* configure transfer data size of memory */ 245 void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth); 246 /* configure transfer data size of peripheral */ 247 void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth); 248 /* enable next address increasement algorithm of memory */ 249 void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); 250 /* disable next address increasement algorithm of memory */ 251 void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); 252 /* enable next address increasement algorithm of peripheral */ 253 void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx); 254 /* disable next address increasement algorithm of peripheral */ 255 void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx); 256 /* configure the direction of data transfer on the channel */ 257 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction); 258 259 /* flag and interrupt functions */ 260 /* check DMA flag is set or not */ 261 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 262 /* clear the flag of a DMA channel */ 263 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 264 /* check DMA flag and interrupt enable bit is set or not */ 265 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 266 /* clear the interrupt flag of a DMA channel */ 267 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag); 268 /* enable DMA interrupt */ 269 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 270 /* disable DMA interrupt */ 271 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source); 272 273 #endif /* GD32E10X_DMA_H */ 274
