1 /*!
2 \file gd32e10x_dbg.c
3 \brief DBG driver
4
5 \version 2017-12-26, V1.0.0, firmware for GD32E10x
6 \version 2020-09-30, V1.1.0, firmware for GD32E10x
7 \version 2020-12-31, V1.2.0, firmware for GD32E10x
8 \version 2022-06-30, V1.3.0, firmware for GD32E10x
9 */
10
11 /*
12 Copyright (c) 2022, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32e10x_dbg.h"
39
40 /*!
41 \brief read DBG_ID code register
42 \param[in] none
43 \param[out] none
44 \retval DBG_ID code
45 */
dbg_id_get(void)46 uint32_t dbg_id_get(void)
47 {
48 return DBG_ID;
49 }
50
51 /*!
52 \brief enable low power behavior when the mcu is in debug mode
53 \param[in] dbg_low_power:
54 one or more parameters can be selected which are shown as below:
55 \arg DBG_LOW_POWER_SLEEP: keep debugger connection during sleep mode
56 \arg DBG_LOW_POWER_DEEPSLEEP: keep debugger connection during deepsleep mode
57 \arg DBG_LOW_POWER_STANDBY: keep debugger connection during standby mode
58 \param[out] none
59 \retval none
60 */
dbg_low_power_enable(uint32_t dbg_low_power)61 void dbg_low_power_enable(uint32_t dbg_low_power)
62 {
63 DBG_CTL |= dbg_low_power;
64 }
65
66 /*!
67 \brief disable low power behavior when the mcu is in debug mode
68 \param[in] dbg_low_power:
69 one or more parameters can be selected which are shown as below:
70 \arg DBG_LOW_POWER_SLEEP: donot keep debugger connection during sleep mode
71 \arg DBG_LOW_POWER_DEEPSLEEP: donot keep debugger connection during deepsleep mode
72 \arg DBG_LOW_POWER_STANDBY: donot keep debugger connection during standby mode
73 \param[out] none
74 \retval none
75 */
dbg_low_power_disable(uint32_t dbg_low_power)76 void dbg_low_power_disable(uint32_t dbg_low_power)
77 {
78 DBG_CTL &= ~dbg_low_power;
79 }
80
81 /*!
82 \brief enable peripheral behavior when the mcu is in debug mode
83 \param[in] dbg_periph: refer to dbg_periph_enum
84 one or more parameters can be selected which are shown as below:
85 \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
86 \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
87 \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CANx counter when core is halted
88 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
89 \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13,TIMER8..13 are not available for HD series): hold TIMERx counter when core is halted
90 \param[out] none
91 \retval none
92 */
dbg_periph_enable(dbg_periph_enum dbg_periph)93 void dbg_periph_enable(dbg_periph_enum dbg_periph)
94 {
95 DBG_CTL |= (uint32_t)dbg_periph;
96 }
97
98 /*!
99 \brief disable peripheral behavior when the mcu is in debug mode
100 \param[in] dbg_periph: refer to dbg_periph_enum
101 one or more parameters can be selected which are shown as below:
102 \arg DBG_FWDGT_HOLD : debug FWDGT kept when core is halted
103 \arg DBG_WWDGT_HOLD : debug WWDGT kept when core is halted
104 \arg DBG_CANx_HOLD (x=0,1,CAN1 is only available for CL series): hold CAN0 counter when core is halted
105 \arg DBG_I2Cx_HOLD (x=0,1): hold I2Cx smbus when core is halted
106 \arg DBG_TIMERx_HOLD (x=0,1,2,3,4,5,6,7,8,9,10,11,12,13): hold TIMERx counter when core is halted
107 \param[out] none
108 \retval none
109 */
dbg_periph_disable(dbg_periph_enum dbg_periph)110 void dbg_periph_disable(dbg_periph_enum dbg_periph)
111 {
112 DBG_CTL &= ~(uint32_t)dbg_periph;
113 }
114
115 /*!
116 \brief enable trace pin assignment
117 \param[in] none
118 \param[out] none
119 \retval none
120 */
dbg_trace_pin_enable(void)121 void dbg_trace_pin_enable(void)
122 {
123 DBG_CTL |= DBG_CTL_TRACE_IOEN;
124 }
125
126 /*!
127 \brief disable trace pin assignment
128 \param[in] none
129 \param[out] none
130 \retval none
131 */
dbg_trace_pin_disable(void)132 void dbg_trace_pin_disable(void)
133 {
134 DBG_CTL &= ~DBG_CTL_TRACE_IOEN;
135 }
136
137
