1 /*! 2 \file gd32e10x_dac.h 3 \brief definitions for the DAC 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_DAC_H 39 #define GD32E10X_DAC_H 40 41 #include "gd32e10x.h" 42 43 /* DACx(x=0,1) definitions */ 44 #define DAC DAC_BASE 45 #define DAC0 0U 46 #define DAC1 1U 47 48 /* registers definitions */ 49 #define DAC_CTL REG32(DAC + 0x00U) /*!< DAC control register */ 50 #define DAC_SWT REG32(DAC + 0x04U) /*!< DAC software trigger register */ 51 #define DAC0_R12DH REG32(DAC + 0x08U) /*!< DAC0 12-bit right-aligned data holding register */ 52 #define DAC0_L12DH REG32(DAC + 0x0CU) /*!< DAC0 12-bit left-aligned data holding register */ 53 #define DAC0_R8DH REG32(DAC + 0x10U) /*!< DAC0 8-bit right-aligned data holding register */ 54 #define DAC1_R12DH REG32(DAC + 0x14U) /*!< DAC1 12-bit right-aligned data holding register */ 55 #define DAC1_L12DH REG32(DAC + 0x18U) /*!< DAC1 12-bit left-aligned data holding register */ 56 #define DAC1_R8DH REG32(DAC + 0x1CU) /*!< DAC1 8-bit right-aligned data holding register */ 57 #define DACC_R12DH REG32(DAC + 0x20U) /*!< DAC concurrent mode 12-bit right-aligned data holding register */ 58 #define DACC_L12DH REG32(DAC + 0x24U) /*!< DAC concurrent mode 12-bit left-aligned data holding register */ 59 #define DACC_R8DH REG32(DAC + 0x28U) /*!< DAC concurrent mode 8-bit right-aligned data holding register */ 60 #define DAC0_DO REG32(DAC + 0x2CU) /*!< DAC0 data output register */ 61 #define DAC1_DO REG32(DAC + 0x30U) /*!< DAC1 data output register */ 62 63 /* bits definitions */ 64 /* DAC_CTL */ 65 #define DAC_CTL_DEN0 BIT(0) /*!< DAC0 enable/disable bit */ 66 #define DAC_CTL_DBOFF0 BIT(1) /*!< DAC0 output buffer turn on/turn off bit */ 67 #define DAC_CTL_DTEN0 BIT(2) /*!< DAC0 trigger enable/disable bit */ 68 #define DAC_CTL_DTSEL0 BITS(3,5) /*!< DAC0 trigger source selection enable/disable bits */ 69 #define DAC_CTL_DWM0 BITS(6,7) /*!< DAC0 noise wave mode */ 70 #define DAC_CTL_DWBW0 BITS(8,11) /*!< DAC0 noise wave bit width */ 71 #define DAC_CTL_DDMAEN0 BIT(12) /*!< DAC0 DMA enable/disable bit */ 72 #define DAC_CTL_DEN1 BIT(16) /*!< DAC1 enable/disable bit */ 73 #define DAC_CTL_DBOFF1 BIT(17) /*!< DAC1 output buffer turn on/turn off bit */ 74 #define DAC_CTL_DTEN1 BIT(18) /*!< DAC1 trigger enable/disable bit */ 75 #define DAC_CTL_DTSEL1 BITS(19,21) /*!< DAC1 trigger source selection enable/disable bits */ 76 #define DAC_CTL_DWM1 BITS(22,23) /*!< DAC1 noise wave mode */ 77 #define DAC_CTL_DWBW1 BITS(24,27) /*!< DAC1 noise wave bit width */ 78 #define DAC_CTL_DDMAEN1 BIT(28) /*!< DAC1 DMA enable/disable bit */ 79 80 /* DAC_SWT */ 81 #define DAC_SWT_SWTR0 BIT(0) /*!< DAC0 software trigger bit, cleared by hardware */ 82 #define DAC_SWT_SWTR1 BIT(1) /*!< DAC1 software trigger bit, cleared by hardware */ 83 84 /* DAC0_R12DH */ 85 #define DAC0_R12DH_DAC0_DH BITS(0,11) /*!< DAC0 12-bit right-aligned data bits */ 86 87 /* DAC0_L12DH */ 88 #define DAC0_L12DH_DAC0_DH BITS(4,15) /*!< DAC0 12-bit left-aligned data bits */ 89 90 /* DAC0_R8DH */ 91 #define DAC0_R8DH_DAC0_DH BITS(0,7) /*!< DAC0 8-bit right-aligned data bits */ 92 93 /* DAC1_R12DH */ 94 #define DAC1_R12DH_DAC1_DH BITS(0,11) /*!< DAC1 12-bit right-aligned data bits */ 95 96 /* DAC1_L12DH */ 97 #define DAC1_L12DH_DAC1_DH BITS(4,15) /*!< DAC1 12-bit left-aligned data bits */ 98 99 /* DAC1_R8DH */ 100 #define DAC1_R8DH_DAC1_DH BITS(0,7) /*!< DAC1 8-bit right-aligned data bits */ 101 102 /* DACC_R12DH */ 103 #define DACC_R12DH_DAC0_DH BITS(0,11) /*!< DAC concurrent mode DAC0 12-bit right-aligned data bits */ 104 #define DACC_R12DH_DAC1_DH BITS(16,27) /*!< DAC concurrent mode DAC1 12-bit right-aligned data bits */ 105 106 /* DACC_L12DH */ 107 #define DACC_L12DH_DAC0_DH BITS(4,15) /*!< DAC concurrent mode DAC0 12-bit left-aligned data bits */ 108 #define DACC_L12DH_DAC1_DH BITS(20,31) /*!< DAC concurrent mode DAC1 12-bit left-aligned data bits */ 109 110 /* DACC_R8DH */ 111 #define DACC_R8DH_DAC0_DH BITS(0,7) /*!< DAC concurrent mode DAC0 8-bit right-aligned data bits */ 112 #define DACC_R8DH_DAC1_DH BITS(8,15) /*!< DAC concurrent mode DAC1 8-bit right-aligned data bits */ 113 114 /* DAC0_DO */ 115 #define DAC0_DO_DAC0_DO BITS(0,11) /*!< DAC0 12-bit output data bits */ 116 117 /* DAC1_DO */ 118 #define DAC1_DO_DAC1_DO BITS(0,11) /*!< DAC1 12-bit output data bits */ 119 120 /* constants definitions */ 121 /* DAC trigger source */ 122 #define CTL_DTSEL(regval) (BITS(3,5) & ((uint32_t)(regval) << 3)) 123 #define DAC_TRIGGER_T5_TRGO CTL_DTSEL(0) /*!< TIMER5 TRGO */ 124 #define DAC_TRIGGER_T2_TRGO CTL_DTSEL(1) /*!< TIMER2 TRGO */ 125 #define DAC_TRIGGER_T6_TRGO CTL_DTSEL(2) /*!< TIMER6 TRGO */ 126 #define DAC_TRIGGER_T4_TRGO CTL_DTSEL(3) /*!< TIMER4 TRGO */ 127 #define DAC_TRIGGER_T1_TRGO CTL_DTSEL(4) /*!< TIMER1 TRGO */ 128 #define DAC_TRIGGER_T3_TRGO CTL_DTSEL(5) /*!< TIMER3 TRGO */ 129 #define DAC_TRIGGER_EXTI_9 CTL_DTSEL(6) /*!< EXTI interrupt line9 event */ 130 #define DAC_TRIGGER_SOFTWARE CTL_DTSEL(7) /*!< software trigger */ 131 132 /* DAC noise wave mode */ 133 #define CTL_DWM(regval) (BITS(6,7) & ((uint32_t)(regval) << 6)) 134 #define DAC_WAVE_DISABLE CTL_DWM(0) /*!< wave disable */ 135 #define DAC_WAVE_MODE_LFSR CTL_DWM(1) /*!< LFSR noise mode */ 136 #define DAC_WAVE_MODE_TRIANGLE CTL_DWM(2) /*!< triangle noise mode */ 137 138 /* DAC noise wave bit width */ 139 #define DWBW(regval) (BITS(8,11) & ((uint32_t)(regval) << 8)) 140 #define DAC_WAVE_BIT_WIDTH_1 DWBW(0) /*!< bit width of the wave signal is 1 */ 141 #define DAC_WAVE_BIT_WIDTH_2 DWBW(1) /*!< bit width of the wave signal is 2 */ 142 #define DAC_WAVE_BIT_WIDTH_3 DWBW(2) /*!< bit width of the wave signal is 3 */ 143 #define DAC_WAVE_BIT_WIDTH_4 DWBW(3) /*!< bit width of the wave signal is 4 */ 144 #define DAC_WAVE_BIT_WIDTH_5 DWBW(4) /*!< bit width of the wave signal is 5 */ 145 #define DAC_WAVE_BIT_WIDTH_6 DWBW(5) /*!< bit width of the wave signal is 6 */ 146 #define DAC_WAVE_BIT_WIDTH_7 DWBW(6) /*!< bit width of the wave signal is 7 */ 147 #define DAC_WAVE_BIT_WIDTH_8 DWBW(7) /*!< bit width of the wave signal is 8 */ 148 #define DAC_WAVE_BIT_WIDTH_9 DWBW(8) /*!< bit width of the wave signal is 9 */ 149 #define DAC_WAVE_BIT_WIDTH_10 DWBW(9) /*!< bit width of the wave signal is 10 */ 150 #define DAC_WAVE_BIT_WIDTH_11 DWBW(10) /*!< bit width of the wave signal is 11 */ 151 #define DAC_WAVE_BIT_WIDTH_12 DWBW(11) /*!< bit width of the wave signal is 12 */ 152 153 /* unmask LFSR bits in DAC LFSR noise mode */ 154 #define DAC_LFSR_BIT0 DAC_WAVE_BIT_WIDTH_1 /*!< unmask the LFSR bit0 */ 155 #define DAC_LFSR_BITS1_0 DAC_WAVE_BIT_WIDTH_2 /*!< unmask the LFSR bits[1:0] */ 156 #define DAC_LFSR_BITS2_0 DAC_WAVE_BIT_WIDTH_3 /*!< unmask the LFSR bits[2:0] */ 157 #define DAC_LFSR_BITS3_0 DAC_WAVE_BIT_WIDTH_4 /*!< unmask the LFSR bits[3:0] */ 158 #define DAC_LFSR_BITS4_0 DAC_WAVE_BIT_WIDTH_5 /*!< unmask the LFSR bits[4:0] */ 159 #define DAC_LFSR_BITS5_0 DAC_WAVE_BIT_WIDTH_6 /*!< unmask the LFSR bits[5:0] */ 160 #define DAC_LFSR_BITS6_0 DAC_WAVE_BIT_WIDTH_7 /*!< unmask the LFSR bits[6:0] */ 161 #define DAC_LFSR_BITS7_0 DAC_WAVE_BIT_WIDTH_8 /*!< unmask the LFSR bits[7:0] */ 162 #define DAC_LFSR_BITS8_0 DAC_WAVE_BIT_WIDTH_9 /*!< unmask the LFSR bits[8:0] */ 163 #define DAC_LFSR_BITS9_0 DAC_WAVE_BIT_WIDTH_10 /*!< unmask the LFSR bits[9:0] */ 164 #define DAC_LFSR_BITS10_0 DAC_WAVE_BIT_WIDTH_11 /*!< unmask the LFSR bits[10:0] */ 165 #define DAC_LFSR_BITS11_0 DAC_WAVE_BIT_WIDTH_12 /*!< unmask the LFSR bits[11:0] */ 166 167 /* DAC data alignment */ 168 #define DATA_ALIGN(regval) (BITS(0,1) & ((uint32_t)(regval) << 0)) 169 #define DAC_ALIGN_12B_R DATA_ALIGN(0) /*!< data right 12 bit alignment */ 170 #define DAC_ALIGN_12B_L DATA_ALIGN(1) /*!< data left 12 bit alignment */ 171 #define DAC_ALIGN_8B_R DATA_ALIGN(2) /*!< data right 8 bit alignment */ 172 173 /* triangle amplitude in DAC triangle noise mode */ 174 #define DAC_TRIANGLE_AMPLITUDE_1 DAC_WAVE_BIT_WIDTH_1 /*!< triangle amplitude is 1 */ 175 #define DAC_TRIANGLE_AMPLITUDE_3 DAC_WAVE_BIT_WIDTH_2 /*!< triangle amplitude is 3 */ 176 #define DAC_TRIANGLE_AMPLITUDE_7 DAC_WAVE_BIT_WIDTH_3 /*!< triangle amplitude is 7 */ 177 #define DAC_TRIANGLE_AMPLITUDE_15 DAC_WAVE_BIT_WIDTH_4 /*!< triangle amplitude is 15 */ 178 #define DAC_TRIANGLE_AMPLITUDE_31 DAC_WAVE_BIT_WIDTH_5 /*!< triangle amplitude is 31 */ 179 #define DAC_TRIANGLE_AMPLITUDE_63 DAC_WAVE_BIT_WIDTH_6 /*!< triangle amplitude is 63 */ 180 #define DAC_TRIANGLE_AMPLITUDE_127 DAC_WAVE_BIT_WIDTH_7 /*!< triangle amplitude is 127 */ 181 #define DAC_TRIANGLE_AMPLITUDE_255 DAC_WAVE_BIT_WIDTH_8 /*!< triangle amplitude is 255 */ 182 #define DAC_TRIANGLE_AMPLITUDE_511 DAC_WAVE_BIT_WIDTH_9 /*!< triangle amplitude is 511 */ 183 #define DAC_TRIANGLE_AMPLITUDE_1023 DAC_WAVE_BIT_WIDTH_10 /*!< triangle amplitude is 1023 */ 184 #define DAC_TRIANGLE_AMPLITUDE_2047 DAC_WAVE_BIT_WIDTH_11 /*!< triangle amplitude is 2047 */ 185 #define DAC_TRIANGLE_AMPLITUDE_4095 DAC_WAVE_BIT_WIDTH_12 /*!< triangle amplitude is 4095 */ 186 187 /* function declarations */ 188 /* initialization functions */ 189 /* deinitialize DAC */ 190 void dac_deinit(void); 191 /* enable DAC */ 192 void dac_enable(uint32_t dac_periph); 193 /* disable DAC */ 194 void dac_disable(uint32_t dac_periph); 195 /* enable DAC DMA */ 196 void dac_dma_enable(uint32_t dac_periph); 197 /* disable DAC DMA */ 198 void dac_dma_disable(uint32_t dac_periph); 199 /* enable DAC output buffer */ 200 void dac_output_buffer_enable(uint32_t dac_periph); 201 /* disable DAC output buffer */ 202 void dac_output_buffer_disable(uint32_t dac_periph); 203 /* get the last data output value */ 204 uint16_t dac_output_value_get(uint32_t dac_periph); 205 /* set DAC data holding register value */ 206 void dac_data_set(uint32_t dac_periph, uint32_t dac_align, uint16_t data); 207 208 /* DAC trigger configuration */ 209 /* enable DAC trigger */ 210 void dac_trigger_enable(uint32_t dac_periph); 211 /* disable DAC trigger */ 212 void dac_trigger_disable(uint32_t dac_periph); 213 /* configure DAC trigger source */ 214 void dac_trigger_source_config(uint32_t dac_periph, uint32_t triggersource); 215 /* enable DAC software trigger */ 216 void dac_software_trigger_enable(uint32_t dac_periph); 217 /* disable DAC software trigger */ 218 void dac_software_trigger_disable(uint32_t dac_periph); 219 220 /* DAC wave mode configuration */ 221 /* configure DAC wave mode */ 222 void dac_wave_mode_config(uint32_t dac_periph, uint32_t wave_mode); 223 /* configure DAC wave bit width */ 224 void dac_wave_bit_width_config(uint32_t dac_periph, uint32_t bit_width); 225 /* configure DAC LFSR noise mode */ 226 void dac_lfsr_noise_config(uint32_t dac_periph, uint32_t unmask_bits); 227 /* configure DAC triangle noise mode */ 228 void dac_triangle_noise_config(uint32_t dac_periph, uint32_t amplitude); 229 230 /* DAC concurrent mode configuration */ 231 /* enable DAC concurrent mode */ 232 void dac_concurrent_enable(void); 233 /* disable DAC concurrent mode */ 234 void dac_concurrent_disable(void); 235 /* enable DAC concurrent software trigger */ 236 void dac_concurrent_software_trigger_enable(void); 237 /* disable DAC concurrent software trigger */ 238 void dac_concurrent_software_trigger_disable(void); 239 /* enable DAC concurrent buffer function */ 240 void dac_concurrent_output_buffer_enable(void); 241 /* disable DAC concurrent buffer function */ 242 void dac_concurrent_output_buffer_disable(void); 243 /* set DAC concurrent mode data holding register value */ 244 void dac_concurrent_data_set(uint32_t dac_align, uint16_t data0, uint16_t data1); 245 246 #endif /* GD32E10X_DAC_H */ 247
