1 /*!
2 \file gd32e10x_adc.c
3 \brief ADC driver
4
5 \version 2017-12-26, V1.0.0, firmware for GD32E10x
6 \version 2020-09-30, V1.1.0, firmware for GD32E10x
7 \version 2020-12-31, V1.2.0, firmware for GD32E10x
8 \version 2022-06-30, V1.3.0, firmware for GD32E10x
9 */
10
11 /*
12 Copyright (c) 2022, GigaDevice Semiconductor Inc.
13
14 Redistribution and use in source and binary forms, with or without modification,
15 are permitted provided that the following conditions are met:
16
17 1. Redistributions of source code must retain the above copyright notice, this
18 list of conditions and the following disclaimer.
19 2. Redistributions in binary form must reproduce the above copyright notice,
20 this list of conditions and the following disclaimer in the documentation
21 and/or other materials provided with the distribution.
22 3. Neither the name of the copyright holder nor the names of its contributors
23 may be used to endorse or promote products derived from this software without
24 specific prior written permission.
25
26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
35 OF SUCH DAMAGE.
36 */
37
38 #include "gd32e10x_adc.h"
39
40 /* discontinuous mode macro*/
41 #define ADC_CHANNEL_LENGTH_SUBTRACT_ONE ((uint8_t)1U)
42
43 /* ADC regular channel macro */
44 #define ADC_REGULAR_CHANNEL_RANK_SIX ((uint8_t)6U)
45 #define ADC_REGULAR_CHANNEL_RANK_TWELVE ((uint8_t)12U)
46 #define ADC_REGULAR_CHANNEL_RANK_SIXTEEN ((uint8_t)16U)
47 #define ADC_REGULAR_CHANNEL_RANK_LENGTH ((uint8_t)5U)
48
49 /* ADC sampling time macro */
50 #define ADC_CHANNEL_SAMPLE_TEN ((uint8_t)10U)
51 #define ADC_CHANNEL_SAMPLE_EIGHTEEN ((uint8_t)18U)
52 #define ADC_CHANNEL_SAMPLE_LENGTH ((uint8_t)3U)
53
54 /* ADC inserted channel macro */
55 #define ADC_INSERTED_CHANNEL_RANK_LENGTH ((uint8_t)5U)
56 #define ADC_INSERTED_CHANNEL_SHIFT_LENGTH ((uint8_t)15U)
57
58 /* ADC inserted channel offset macro */
59 #define ADC_OFFSET_LENGTH ((uint8_t)3U)
60 #define ADC_OFFSET_SHIFT_LENGTH ((uint8_t)4U)
61
62 /*!
63 \brief reset ADC
64 \param[in] adc_periph: ADCx,x=0,1
65 \param[out] none
66 \retval none
67 */
adc_deinit(uint32_t adc_periph)68 void adc_deinit(uint32_t adc_periph)
69 {
70 switch(adc_periph){
71 case ADC0:
72 /* reset ADC0 */
73 rcu_periph_reset_enable(RCU_ADC0RST);
74 rcu_periph_reset_disable(RCU_ADC0RST);
75 break;
76 case ADC1:
77 /* reset ADC1 */
78 rcu_periph_reset_enable(RCU_ADC1RST);
79 rcu_periph_reset_disable(RCU_ADC1RST);
80 break;
81 default:
82 break;
83 }
84 }
85
86 /*!
87 \brief configure the ADC sync mode
88 \param[in] mode: ADC mode
89 only one parameter can be selected which is shown as below:
90 \arg ADC_MODE_FREE: all the ADCs work independently
91 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL: ADC0 and ADC1 work in combined regular parallel + inserted parallel mode
92 \arg ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION: ADC0 and ADC1 work in combined regular parallel + trigger rotation mode
93 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode
94 \arg ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode
95 \arg ADC_DAUL_INSERTED_PARALLEL: ADC0 and ADC1 work in inserted parallel mode only
96 \arg ADC_DAUL_REGULAL_PARALLEL: ADC0 and ADC1 work in regular parallel mode only
97 \arg ADC_DAUL_REGULAL_FOLLOWUP_FAST: ADC0 and ADC1 work in follow-up fast mode only
98 \arg ADC_DAUL_REGULAL_FOLLOWUP_SLOW: ADC0 and ADC1 work in follow-up slow mode only
99 \arg ADC_DAUL_INSERTED_TRIGGER_ROTATION: ADC0 and ADC1 work in trigger rotation mode only
100 \param[out] none
101 \retval none
102 */
adc_mode_config(uint32_t mode)103 void adc_mode_config(uint32_t mode)
104 {
105 ADC_CTL0(ADC0) &= ~(ADC_CTL0_SYNCM);
106 ADC_CTL0(ADC0) |= mode;
107 }
108
109 /*!
110 \brief enable or disable ADC special function
111 \param[in] adc_periph: ADCx,x=0,1
112 \param[in] function: the function to config
113 only one parameter can be selected which is shown as below:
114 \arg ADC_SCAN_MODE: scan mode select
115 \arg ADC_INSERTED_CHANNEL_AUTO: inserted channel group convert automatically
116 \arg ADC_CONTINUOUS_MODE: continuous mode select
117 \param[in] newvalue: ENABLE or DISABLE
118 \param[out] none
119 \retval none
120 */
adc_special_function_config(uint32_t adc_periph,uint32_t function,ControlStatus newvalue)121 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue)
122 {
123 if(newvalue){
124 if(0U != (function & ADC_SCAN_MODE)){
125 /* enable scan mode */
126 ADC_CTL0(adc_periph) |= ADC_SCAN_MODE;
127 }
128 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
129 /* enable inserted channel group convert automatically */
130 ADC_CTL0(adc_periph) |= ADC_INSERTED_CHANNEL_AUTO;
131 }
132 if(0U != (function & ADC_CONTINUOUS_MODE)){
133 /* enable continuous mode */
134 ADC_CTL1(adc_periph) |= ADC_CONTINUOUS_MODE;
135 }
136 }else{
137 if(0U != (function & ADC_SCAN_MODE)){
138 /* disable scan mode */
139 ADC_CTL0(adc_periph) &= ~ADC_SCAN_MODE;
140 }
141 if(0U != (function & ADC_INSERTED_CHANNEL_AUTO)){
142 /* disable inserted channel group convert automatically */
143 ADC_CTL0(adc_periph) &= ~ADC_INSERTED_CHANNEL_AUTO;
144 }
145 if(0U != (function & ADC_CONTINUOUS_MODE)){
146 /* disable continuous mode */
147 ADC_CTL1(adc_periph) &= ~ADC_CONTINUOUS_MODE;
148 }
149 }
150 }
151
152 /*!
153 \brief configure ADC data alignment
154 \param[in] adc_periph: ADCx,x=0,1
155 \param[in] data_alignment: data alignment select
156 only one parameter can be selected which is shown as below:
157 \arg ADC_DATAALIGN_RIGHT: LSB alignment
158 \arg ADC_DATAALIGN_LEFT: MSB alignment
159 \param[out] none
160 \retval none
161 */
adc_data_alignment_config(uint32_t adc_periph,uint32_t data_alignment)162 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment)
163 {
164 if(ADC_DATAALIGN_RIGHT != data_alignment){
165 /* MSB alignment */
166 ADC_CTL1(adc_periph) |= ADC_CTL1_DAL;
167 }else{
168 /* LSB alignment */
169 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DAL);
170 }
171 }
172
173 /*!
174 \brief enable ADC interface
175 \param[in] adc_periph: ADCx,x=0,1
176 \param[out] none
177 \retval none
178 */
adc_enable(uint32_t adc_periph)179 void adc_enable(uint32_t adc_periph)
180 {
181 if(RESET == (ADC_CTL1(adc_periph) & ADC_CTL1_ADCON)){
182 /* enable ADC */
183 ADC_CTL1(adc_periph) |= (uint32_t)ADC_CTL1_ADCON;
184 }
185 }
186
187 /*!
188 \brief disable ADC interface
189 \param[in] adc_periph: ADCx,x=0,1
190 \param[out] none
191 \retval none
192 */
adc_disable(uint32_t adc_periph)193 void adc_disable(uint32_t adc_periph)
194 {
195 /* disable ADC */
196 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ADCON);
197 }
198
199 /*!
200 \brief ADC calibration and reset calibration
201 \param[in] adc_periph: ADCx,x=0,1
202 \param[out] none
203 \retval none
204 */
adc_calibration_enable(uint32_t adc_periph)205 void adc_calibration_enable(uint32_t adc_periph)
206 {
207 /* reset the selected ADC calibration registers */
208 ADC_CTL1(adc_periph) |= (uint32_t) ADC_CTL1_RSTCLB;
209 /* check the RSTCLB bit state */
210 while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_RSTCLB)){
211 }
212 /* enable ADC calibration process */
213 ADC_CTL1(adc_periph) |= ADC_CTL1_CLB;
214 /* check the CLB bit state */
215 while(RESET != (ADC_CTL1(adc_periph) & ADC_CTL1_CLB)){
216 }
217 }
218
219 /*!
220 \brief enable the temperature sensor and Vrefint channel
221 \param[in] none
222 \param[out] none
223 \retval none
224 */
adc_tempsensor_vrefint_enable(void)225 void adc_tempsensor_vrefint_enable(void)
226 {
227 /* enable the temperature sensor and Vrefint channel */
228 ADC_CTL1(ADC0) |= ADC_CTL1_TSVREN;
229 }
230
231 /*!
232 \brief disable the temperature sensor and Vrefint channel
233 \param[in] none
234 \param[out] none
235 \retval none
236 */
adc_tempsensor_vrefint_disable(void)237 void adc_tempsensor_vrefint_disable(void)
238 {
239 /* disable the temperature sensor and Vrefint channel */
240 ADC_CTL1(ADC0) &= ~ADC_CTL1_TSVREN;
241 }
242
243 /*!
244 \brief configure ADC resolution
245 \param[in] adc_periph: ADCx,x=0,1
246 \param[in] resolution: ADC resolution
247 only one parameter can be selected which is shown as below:
248 \arg ADC_RESOLUTION_12B: 12-bit ADC resolution
249 \arg ADC_RESOLUTION_10B: 10-bit ADC resolution
250 \arg ADC_RESOLUTION_8B: 8-bit ADC resolution
251 \arg ADC_RESOLUTION_6B: 6-bit ADC resolution
252 \param[out] none
253 \retval none
254 */
adc_resolution_config(uint32_t adc_periph,uint32_t resolution)255 void adc_resolution_config(uint32_t adc_periph , uint32_t resolution)
256 {
257 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_DRES);
258 ADC_OVSAMPCTL(adc_periph) |= (uint32_t)resolution;
259 }
260
261 /*!
262 \brief configure ADC oversample mode
263 \param[in] adc_periph: ADCx,x=0,1
264 \param[in] mode: ADC oversampling mode
265 only one parameter can be selected which is shown as below:
266 \arg ADC_OVERSAMPLING_ALL_CONVERT: all oversampled conversions for a channel are done consecutively after a trigger
267 \arg ADC_OVERSAMPLING_ONE_CONVERT: each oversampled conversion for a channel needs a trigger
268 \param[in] shift: ADC oversampling shift
269 only one parameter can be selected which is shown as below:
270 \arg ADC_OVERSAMPLING_SHIFT_NONE: no oversampling shift
271 \arg ADC_OVERSAMPLING_SHIFT_1B: 1-bit oversampling shift
272 \arg ADC_OVERSAMPLING_SHIFT_2B: 2-bit oversampling shift
273 \arg ADC_OVERSAMPLING_SHIFT_3B: 3-bit oversampling shift
274 \arg ADC_OVERSAMPLING_SHIFT_4B: 3-bit oversampling shift
275 \arg ADC_OVERSAMPLING_SHIFT_5B: 5-bit oversampling shift
276 \arg ADC_OVERSAMPLING_SHIFT_6B: 6-bit oversampling shift
277 \arg ADC_OVERSAMPLING_SHIFT_7B: 7-bit oversampling shift
278 \arg ADC_OVERSAMPLING_SHIFT_8B: 8-bit oversampling shift
279 \param[in] ratio: ADC oversampling ratio
280 only one parameter can be selected which is shown as below:
281 \arg ADC_OVERSAMPLING_RATIO_MUL2: oversampling ratio multiple 2
282 \arg ADC_OVERSAMPLING_RATIO_MUL4: oversampling ratio multiple 4
283 \arg ADC_OVERSAMPLING_RATIO_MUL8: oversampling ratio multiple 8
284 \arg ADC_OVERSAMPLING_RATIO_MUL16: oversampling ratio multiple 16
285 \arg ADC_OVERSAMPLING_RATIO_MUL32: oversampling ratio multiple 32
286 \arg ADC_OVERSAMPLING_RATIO_MUL64: oversampling ratio multiple 64
287 \arg ADC_OVERSAMPLING_RATIO_MUL128: oversampling ratio multiple 128
288 \arg ADC_OVERSAMPLING_RATIO_MUL256: oversampling ratio multiple 256
289 \param[out] none
290 \retval none
291 */
adc_oversample_mode_config(uint32_t adc_periph,uint32_t mode,uint16_t shift,uint8_t ratio)292 void adc_oversample_mode_config(uint32_t adc_periph, uint32_t mode, uint16_t shift, uint8_t ratio)
293 {
294 if(ADC_OVERSAMPLING_ONE_CONVERT == mode){
295 ADC_OVSAMPCTL(adc_periph) |= (uint32_t)ADC_OVSAMPCTL_TOVS;
296 }else{
297 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_TOVS);
298 }
299 /* config the shift and ratio */
300 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)(ADC_OVSAMPCTL_OVSR | ADC_OVSAMPCTL_OVSS));
301 ADC_OVSAMPCTL(adc_periph) |= ((uint32_t)shift | (uint32_t)ratio);
302 }
303
304 /*!
305 \brief enable ADC oversample mode
306 \param[in] adc_periph: ADCx,x=0,1
307 \param[out] none
308 \retval none
309 */
adc_oversample_mode_enable(uint32_t adc_periph)310 void adc_oversample_mode_enable(uint32_t adc_periph)
311 {
312 ADC_OVSAMPCTL(adc_periph) |= ADC_OVSAMPCTL_OVSEN;
313 }
314
315 /*!
316 \brief disable ADC oversample mode
317 \param[in] adc_periph: ADCx,x=0,1
318 \param[out] none
319 \retval none
320 */
adc_oversample_mode_disable(uint32_t adc_periph)321 void adc_oversample_mode_disable(uint32_t adc_periph)
322 {
323 ADC_OVSAMPCTL(adc_periph) &= ~((uint32_t)ADC_OVSAMPCTL_OVSEN);
324 }
325
326 /*!
327 \brief enable DMA request
328 \param[in] adc_periph: ADCx,x=0,1
329 \param[out] none
330 \retval none
331 */
adc_dma_mode_enable(uint32_t adc_periph)332 void adc_dma_mode_enable(uint32_t adc_periph)
333 {
334 /* enable DMA request */
335 ADC_CTL1(adc_periph) |= (uint32_t)(ADC_CTL1_DMA);
336 }
337
338 /*!
339 \brief disable DMA request
340 \param[in] adc_periph: ADCx,x=0,1
341 \param[out] none
342 \retval none
343 */
adc_dma_mode_disable(uint32_t adc_periph)344 void adc_dma_mode_disable(uint32_t adc_periph)
345 {
346 /* disable DMA request */
347 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_DMA);
348 }
349
350 /*!
351 \brief configure ADC discontinuous mode
352 \param[in] adc_periph: ADCx,x=0,1
353 \param[in] adc_channel_group: select the channel group
354 only one parameter can be selected which is shown as below:
355 \arg ADC_REGULAR_CHANNEL: regular channel group
356 \arg ADC_INSERTED_CHANNEL: inserted channel group
357 \arg ADC_CHANNEL_DISCON_DISABLE: disable discontinuous mode of regular & inserted channel
358 \param[in] length: number of conversions in discontinuous mode,the number can be 1..8
359 for regular channel ,the number has no effect for inserted channel
360 \param[out] none
361 \retval none
362 */
adc_discontinuous_mode_config(uint32_t adc_periph,uint8_t adc_channel_group,uint8_t length)363 void adc_discontinuous_mode_config(uint32_t adc_periph, uint8_t adc_channel_group, uint8_t length)
364 {
365 /* disable discontinuous mode of regular & inserted channel */
366 ADC_CTL0(adc_periph) &= ~((uint32_t)(ADC_CTL0_DISRC | ADC_CTL0_DISIC));
367 switch(adc_channel_group){
368 case ADC_REGULAR_CHANNEL:
369 /* config the number of conversions in discontinuous mode */
370 ADC_CTL0(adc_periph) &= ~((uint32_t)ADC_CTL0_DISNUM);
371 ADC_CTL0(adc_periph) |= CTL0_DISNUM(((uint32_t)length - ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
372 /* enable regular channel group discontinuous mode */
373 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISRC;
374 break;
375 case ADC_INSERTED_CHANNEL:
376 /* enable inserted channel group discontinuous mode */
377 ADC_CTL0(adc_periph) |= (uint32_t)ADC_CTL0_DISIC;
378 break;
379 case ADC_CHANNEL_DISCON_DISABLE:
380 /* disable discontinuous mode of regular & inserted channel */
381 default:
382 break;
383 }
384 }
385
386 /*!
387 \brief configure the length of regular channel group or inserted channel group
388 \param[in] adc_periph: ADCx,x=0,1
389 \param[in] adc_channel_group: select the channel group
390 only one parameter can be selected which is shown as below:
391 \arg ADC_REGULAR_CHANNEL: regular channel group
392 \arg ADC_INSERTED_CHANNEL: inserted channel group
393 \param[in] length: the length of the channel
394 regular channel 1-16
395 inserted channel 1-4
396 \param[out] none
397 \retval none
398 */
adc_channel_length_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t length)399 void adc_channel_length_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t length)
400 {
401 switch(adc_channel_group){
402 case ADC_REGULAR_CHANNEL:
403 /* configure the length of regular channel group */
404 ADC_RSQ0(adc_periph) &= ~((uint32_t)ADC_RSQ0_RL);
405 ADC_RSQ0(adc_periph) |= RSQ0_RL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
406 break;
407 case ADC_INSERTED_CHANNEL:
408 /* configure the length of inserted channel group */
409 ADC_ISQ(adc_periph) &= ~((uint32_t)ADC_ISQ_IL);
410 ADC_ISQ(adc_periph) |= ISQ_IL((uint32_t)(length-ADC_CHANNEL_LENGTH_SUBTRACT_ONE));
411 break;
412 default:
413 break;
414 }
415 }
416
417 /*!
418 \brief configure ADC regular channel
419 \param[in] adc_periph: ADCx,x=0,1
420 \param[in] rank: the regular group sequence rank,this parameter must be between 0 to 15
421 \param[in] adc_channel: the selected ADC channel
422 only one parameter can be selected which is shown as below:
423 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
424 \param[in] sample_time: the sample time value
425 only one parameter can be selected which is shown as below:
426 \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
427 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
428 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
429 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
430 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
431 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
432 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
433 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
434 \param[out] none
435 \retval none
436 */
adc_regular_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)437 void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
438 {
439 uint32_t rsq,sampt;
440
441 /* ADC regular sequence config */
442 if(rank < ADC_REGULAR_CHANNEL_RANK_SIX){
443 /* the regular group sequence rank is smaller than six */
444 rsq = ADC_RSQ2(adc_periph);
445 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank)));
446 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
447 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*rank));
448 ADC_RSQ2(adc_periph) = rsq;
449 }else if(rank < ADC_REGULAR_CHANNEL_RANK_TWELVE){
450 /* the regular group sequence rank is smaller than twelve */
451 rsq = ADC_RSQ1(adc_periph);
452 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX))));
453 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
454 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_SIX)));
455 ADC_RSQ1(adc_periph) = rsq;
456 }else if(rank < ADC_REGULAR_CHANNEL_RANK_SIXTEEN){
457 /* the regular group sequence rank is smaller than sixteen */
458 rsq = ADC_RSQ0(adc_periph);
459 rsq &= ~((uint32_t)(ADC_RSQX_RSQN << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE))));
460 /* the channel number is written to these bits to select a channel as the nth conversion in the regular channel group */
461 rsq |= ((uint32_t)adc_channel << (ADC_REGULAR_CHANNEL_RANK_LENGTH*(rank-ADC_REGULAR_CHANNEL_RANK_TWELVE)));
462 ADC_RSQ0(adc_periph) = rsq;
463 }else{
464 }
465
466 /* ADC sampling time config */
467 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
468 /* the regular group sequence rank is smaller than ten */
469 sampt = ADC_SAMPT1(adc_periph);
470 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
471 /* channel sample time set*/
472 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel));
473 ADC_SAMPT1(adc_periph) = sampt;
474 }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
475 /* the regular group sequence rank is smaller than eighteen */
476 sampt = ADC_SAMPT0(adc_periph);
477 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
478 /* channel sample time set*/
479 sampt |= (uint32_t)(sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
480 ADC_SAMPT0(adc_periph) = sampt;
481 }else{
482 }
483 }
484
485 /*!
486 \brief configure ADC inserted channel
487 \param[in] adc_periph: ADCx,x=0,1
488 \param[in] rank: the inserted group sequencer rank,this parameter must be between 0 to 3
489 \param[in] adc_channel: the selected ADC channel
490 only one parameter can be selected which is shown as below:
491 \arg ADC_CHANNEL_x(x=0..17)(x=16 and x=17 are only for ADC0): ADC Channelx
492 \param[in] sample_time: The sample time value
493 only one parameter can be selected which is shown as below:
494 \arg ADC_SAMPLETIME_1POINT5: 1.5 cycles
495 \arg ADC_SAMPLETIME_7POINT5: 7.5 cycles
496 \arg ADC_SAMPLETIME_13POINT5: 13.5 cycles
497 \arg ADC_SAMPLETIME_28POINT5: 28.5 cycles
498 \arg ADC_SAMPLETIME_41POINT5: 41.5 cycles
499 \arg ADC_SAMPLETIME_55POINT5: 55.5 cycles
500 \arg ADC_SAMPLETIME_71POINT5: 71.5 cycles
501 \arg ADC_SAMPLETIME_239POINT5: 239.5 cycles
502 \param[out] none
503 \retval none
504 */
adc_inserted_channel_config(uint32_t adc_periph,uint8_t rank,uint8_t adc_channel,uint32_t sample_time)505 void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time)
506 {
507 uint8_t inserted_length;
508 uint32_t isq,sampt;
509
510 /* get inserted channel group length */
511 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
512 /* the channel number is written to these bits to select a channel as the nth conversion in the inserted channel group */
513 isq = ADC_ISQ(adc_periph);
514 isq &= ~((uint32_t)(ADC_ISQ_ISQN << (5U * ((3 + rank) - inserted_length))));
515 isq |= ((uint32_t)adc_channel << (5U * ((3 + rank) - inserted_length)));
516 ADC_ISQ(adc_periph) = isq;
517
518 /* ADC sampling time config */
519 if(adc_channel < ADC_CHANNEL_SAMPLE_TEN){
520 /* the inserted group sequence rank is smaller than ten */
521 sampt = ADC_SAMPT1(adc_periph);
522 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel)));
523 /* channel sample time set*/
524 sampt |= (uint32_t) sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*adc_channel);
525 ADC_SAMPT1(adc_periph) = sampt;
526 }else if(adc_channel < ADC_CHANNEL_SAMPLE_EIGHTEEN){
527 /* the inserted group sequence rank is smaller than eighteen */
528 sampt = ADC_SAMPT0(adc_periph);
529 sampt &= ~((uint32_t)(ADC_SAMPTX_SPTN << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN))));
530 /* channel sample time set*/
531 sampt |= ((uint32_t)sample_time << (ADC_CHANNEL_SAMPLE_LENGTH*(adc_channel-ADC_CHANNEL_SAMPLE_TEN)));
532 ADC_SAMPT0(adc_periph) = sampt;
533 }else{
534 }
535 }
536
537 /*!
538 \brief configure ADC inserted channel offset
539 \param[in] adc_periph: ADCx,x=0,1
540 \param[in] inserted_channel : insert channel select
541 only one parameter can be selected which is shown as below:
542 \arg ADC_INSERTED_CHANNEL_0: inserted channel0
543 \arg ADC_INSERTED_CHANNEL_1: inserted channel1
544 \arg ADC_INSERTED_CHANNEL_2: inserted channel2
545 \arg ADC_INSERTED_CHANNEL_3: inserted channel3
546 \param[in] offset : the offset data
547 \param[out] none
548 \retval none
549 */
adc_inserted_channel_offset_config(uint32_t adc_periph,uint8_t inserted_channel,uint16_t offset)550 void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset)
551 {
552 uint8_t inserted_length;
553 uint32_t num = 0U;
554
555 inserted_length = (uint8_t)GET_BITS(ADC_ISQ(adc_periph) , 20U , 21U);
556 num = ((uint32_t)ADC_OFFSET_LENGTH - ((uint32_t)inserted_length - (uint32_t)inserted_channel));
557
558 if(num <= ADC_OFFSET_LENGTH){
559 /* calculate the offset of the register */
560 num = num * ADC_OFFSET_SHIFT_LENGTH;
561 /* config the offset of the selected channels */
562 REG32((adc_periph) + 0x14U + num) = IOFFX_IOFF((uint32_t)offset);
563 }
564 }
565
566 /*!
567 \brief configure ADC external trigger source
568 \param[in] adc_periph: ADCx,x=0,1
569 \param[in] adc_channel_group: select the channel group
570 only one parameter can be selected which is shown as below:
571 \arg ADC_REGULAR_CHANNEL: regular channel group
572 \arg ADC_INSERTED_CHANNEL: inserted channel group
573 \param[in] external_trigger_source: regular or inserted group trigger source
574 only one parameter can be selected which is shown as below:
575 for regular channel:
576 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH0: timer 0 CC0 event select
577 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH1: timer 0 CC1 event select
578 \arg ADC0_1_EXTTRIG_REGULAR_T0_CH2: timer 0 CC2 event select
579 \arg ADC0_1_EXTTRIG_REGULAR_T1_CH1: timer 1 CC1 event select
580 \arg ADC0_1_EXTTRIG_REGULAR_T2_TRGO: timer 2 TRGO event select
581 \arg ADC0_1_EXTTRIG_REGULAR_T3_CH3: timer 3 CC3 event select
582 \arg ADC0_1_EXTTRIG_REGULAR_T7_TRGO: timer 7 TRGO event select
583 \arg ADC0_1_EXTTRIG_REGULAR_EXTI_11 : external interrupt line 11
584 \arg ADC0_1_EXTTRIG_REGULAR_NONE: software trigger
585 for inserted channel:
586 \arg ADC0_1_EXTTRIG_INSERTED_T0_TRGO: timer 0 TRGO event select
587 \arg ADC0_1_EXTTRIG_INSERTED_T0_CH3: timer 0 CC3 event select
588 \arg ADC0_1_EXTTRIG_INSERTED_T1_TRGO: timer 1 TRGO event select
589 \arg ADC0_1_EXTTRIG_INSERTED_T1_CH0: timer 1 CC0 event select
590 \arg ADC0_1_EXTTRIG_INSERTED_T2_CH3: timer 2 CC3 event select
591 \arg ADC0_1_EXTTRIG_INSERTED_T3_TRGO: timer 3 TRGO event select
592 \arg ADC0_1_EXTTRIG_INSERTED_EXTI_15: external interrupt line 15
593 \arg ADC0_1_EXTTRIG_INSERTED_T7_CH3: timer 7 CC3 event select
594 \arg ADC0_1_EXTTRIG_INSERTED_NONE: software trigger
595 \param[out] none
596 \retval none
597 */
adc_external_trigger_source_config(uint32_t adc_periph,uint8_t adc_channel_group,uint32_t external_trigger_source)598 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source)
599 {
600 switch(adc_channel_group){
601 case ADC_REGULAR_CHANNEL:
602 /* configure ADC regular group external trigger source */
603 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSRC);
604 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
605 break;
606 case ADC_INSERTED_CHANNEL:
607 /* configure ADC inserted group external trigger source */
608 ADC_CTL1(adc_periph) &= ~((uint32_t)ADC_CTL1_ETSIC);
609 ADC_CTL1(adc_periph) |= (uint32_t)external_trigger_source;
610 break;
611 default:
612 break;
613 }
614 }
615
616 /*!
617 \brief enable ADC external trigger
618 \param[in] adc_periph: ADCx,x=0,1
619 \param[in] adc_channel_group: select the channel group
620 one or more parameters can be selected which are shown as below:
621 \arg ADC_REGULAR_CHANNEL: regular channel group
622 \arg ADC_INSERTED_CHANNEL: inserted channel group
623 \param[in] newvalue: ENABLE or DISABLE
624 \param[out] none
625 \retval none
626 */
adc_external_trigger_config(uint32_t adc_periph,uint8_t adc_channel_group,ControlStatus newvalue)627 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue)
628 {
629 if(newvalue){
630 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
631 /* enable ADC regular channel group external trigger */
632 ADC_CTL1(adc_periph) |= ADC_CTL1_ETERC;
633 }
634 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
635 /* enable ADC inserted channel group external trigger */
636 ADC_CTL1(adc_periph) |= ADC_CTL1_ETEIC;
637 }
638 }else{
639 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
640 /* disable ADC regular channel group external trigger */
641 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETERC;
642 }
643 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
644 /* disable ADC regular channel group external trigger */
645 ADC_CTL1(adc_periph) &= ~ADC_CTL1_ETEIC;
646 }
647 }
648 }
649
650 /*!
651 \brief enable ADC software trigger
652 \param[in] adc_periph: ADCx,x=0,1
653 \param[in] adc_channel_group: select the channel group
654 one or more parameters can be selected which are shown as below:
655 \arg ADC_REGULAR_CHANNEL: regular channel group
656 \arg ADC_INSERTED_CHANNEL: inserted channel group
657 \param[out] none
658 \retval none
659 */
adc_software_trigger_enable(uint32_t adc_periph,uint8_t adc_channel_group)660 void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group)
661 {
662 if(0U != (adc_channel_group & ADC_REGULAR_CHANNEL)){
663 /* enable ADC regular channel group software trigger */
664 ADC_CTL1(adc_periph) |= ADC_CTL1_SWRCST;
665 }
666 if(0U != (adc_channel_group & ADC_INSERTED_CHANNEL)){
667 /* enable ADC inserted channel group software trigger */
668 ADC_CTL1(adc_periph) |= ADC_CTL1_SWICST;
669 }
670 }
671
672 /*!
673 \brief read ADC regular group data register
674 \param[in] adc_periph: ADCx,x=0,1
675 \param[in] none
676 \param[out] none
677 \retval the conversion value
678 */
adc_regular_data_read(uint32_t adc_periph)679 uint16_t adc_regular_data_read(uint32_t adc_periph)
680 {
681 return (uint16_t)(ADC_RDATA(adc_periph));
682 }
683
684 /*!
685 \brief read ADC inserted group data register
686 \param[in] adc_periph: ADCx,x=0,1
687 \param[in] inserted_channel : insert channel select
688 only one parameter can be selected which is shown as below:
689 \arg ADC_INSERTED_CHANNEL_0: inserted Channel0
690 \arg ADC_INSERTED_CHANNEL_1: inserted channel1
691 \arg ADC_INSERTED_CHANNEL_2: inserted Channel2
692 \arg ADC_INSERTED_CHANNEL_3: inserted Channel3
693 \param[out] none
694 \retval the conversion value
695 */
adc_inserted_data_read(uint32_t adc_periph,uint8_t inserted_channel)696 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel)
697 {
698 uint32_t idata;
699 /* read the data of the selected channel */
700 switch(inserted_channel){
701 case ADC_INSERTED_CHANNEL_0:
702 /* read the data of channel 0 */
703 idata = ADC_IDATA0(adc_periph);
704 break;
705 case ADC_INSERTED_CHANNEL_1:
706 /* read the data of channel 1 */
707 idata = ADC_IDATA1(adc_periph);
708 break;
709 case ADC_INSERTED_CHANNEL_2:
710 /* read the data of channel 2 */
711 idata = ADC_IDATA2(adc_periph);
712 break;
713 case ADC_INSERTED_CHANNEL_3:
714 /* read the data of channel 3 */
715 idata = ADC_IDATA3(adc_periph);
716 break;
717 default:
718 idata = 0U;
719 break;
720 }
721 return (uint16_t)idata;
722 }
723
724 /*!
725 \brief read the last ADC0 and ADC1 conversion result data in sync mode
726 \param[in] none
727 \param[out] none
728 \retval the conversion value
729 */
adc_sync_mode_convert_value_read(void)730 uint32_t adc_sync_mode_convert_value_read(void)
731 {
732 /* return conversion value */
733 return ADC_RDATA(ADC0);
734 }
735
736 /*!
737 \brief configure ADC analog watchdog single channel
738 \param[in] adc_periph: ADCx,x=0,1
739 \param[in] adc_channel: the selected ADC channel
740 only one parameter can be selected which is shown as below:
741 \arg ADC_CHANNEL_x: ADC Channelx(x=0..17)(x=16 and x=17 are only for ADC0)
742 \param[out] none
743 \retval none
744 */
adc_watchdog_single_channel_enable(uint32_t adc_periph,uint8_t adc_channel)745 void adc_watchdog_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel)
746 {
747 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
748 /* analog watchdog channel select */
749 ADC_CTL0(adc_periph) |= (uint32_t)adc_channel;
750 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
751 }
752
753 /*!
754 \brief configure ADC analog watchdog group channel
755 \param[in] adc_periph: ADCx,x=0,1
756 \param[in] adc_channel_group: the channel group use analog watchdog
757 only one parameter can be selected which is shown as below:
758 \arg ADC_REGULAR_CHANNEL: regular channel group
759 \arg ADC_INSERTED_CHANNEL: inserted channel group
760 \arg ADC_REGULAR_INSERTED_CHANNEL: both regular and inserted group
761 \param[out] none
762 \retval none
763 */
adc_watchdog_group_channel_enable(uint32_t adc_periph,uint8_t adc_channel_group)764 void adc_watchdog_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group)
765 {
766 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC);
767 /* select the group */
768 switch(adc_channel_group){
769 case ADC_REGULAR_CHANNEL:
770 /* regular channel analog watchdog enable */
771 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_RWDEN;
772 break;
773 case ADC_INSERTED_CHANNEL:
774 /* inserted channel analog watchdog enable */
775 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_IWDEN;
776 break;
777 case ADC_REGULAR_INSERTED_CHANNEL:
778 /* regular and inserted channel analog watchdog enable */
779 ADC_CTL0(adc_periph) |= (uint32_t)(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN);
780 break;
781 default:
782 break;
783 }
784 }
785
786 /*!
787 \brief disable ADC analog watchdog
788 \param[in] adc_periph: ADCx,x=0,1
789 \param[out] none
790 \retval none
791 */
adc_watchdog_disable(uint32_t adc_periph)792 void adc_watchdog_disable(uint32_t adc_periph)
793 {
794 ADC_CTL0(adc_periph) &= (uint32_t)~(ADC_CTL0_RWDEN | ADC_CTL0_IWDEN | ADC_CTL0_WDSC | ADC_CTL0_WDCHSEL);
795 }
796
797 /*!
798 \brief configure ADC analog watchdog threshold
799 \param[in] adc_periph: ADCx,x=0,1
800 \param[in] low_threshold: analog watchdog low threshold,0..4095
801 \param[in] high_threshold: analog watchdog high threshold,0..4095
802 \param[out] none
803 \retval none
804 */
adc_watchdog_threshold_config(uint32_t adc_periph,uint16_t low_threshold,uint16_t high_threshold)805 void adc_watchdog_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold)
806 {
807 ADC_WDLT(adc_periph) = (uint32_t)WDLT_WDLT(low_threshold);
808 ADC_WDHT(adc_periph) = (uint32_t)WDHT_WDHT(high_threshold);
809 }
810
811 /*!
812 \brief get the ADC flag bits
813 \param[in] adc_periph: ADCx,x=0,1
814 \param[in] adc_flag: the adc flag bits
815 only one parameter can be selected which is shown as below:
816 \arg ADC_FLAG_WDE: analog watchdog event flag
817 \arg ADC_FLAG_EOC: end of group conversion flag
818 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
819 \arg ADC_FLAG_STIC: start flag of inserted channel group
820 \arg ADC_FLAG_STRC: start flag of regular channel group
821 \param[out] none
822 \retval FlagStatus: SET or RESET
823 */
adc_flag_get(uint32_t adc_periph,uint32_t adc_flag)824 FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t adc_flag)
825 {
826 FlagStatus reval = RESET;
827 if(ADC_STAT(adc_periph) & adc_flag){
828 reval = SET;
829 }
830 return reval;
831 }
832
833 /*!
834 \brief clear the ADC flag bits
835 \param[in] adc_periph: ADCx,x=0,1
836 \param[in] adc_flag: the adc flag bits
837 one or more parameters can be selected which are shown as below:
838 \arg ADC_FLAG_WDE: analog watchdog event flag
839 \arg ADC_FLAG_EOC: end of group conversion flag
840 \arg ADC_FLAG_EOIC: end of inserted group conversion flag
841 \arg ADC_FLAG_STIC: start flag of inserted channel group
842 \arg ADC_FLAG_STRC: start flag of regular channel group
843 \param[out] none
844 \retval none
845 */
adc_flag_clear(uint32_t adc_periph,uint32_t adc_flag)846 void adc_flag_clear(uint32_t adc_periph , uint32_t adc_flag)
847 {
848 ADC_STAT(adc_periph) &= ~((uint32_t)adc_flag);
849 }
850
851 /*!
852 \brief get the bit state of ADCx software start conversion
853 \param[in] adc_periph: ADCx, x=0,1, only one among these parameters can be selected
854 \param[in] none
855 \param[out] none
856 \retval FlagStatus: SET or RESET
857 */
adc_regular_software_startconv_flag_get(uint32_t adc_periph)858 FlagStatus adc_regular_software_startconv_flag_get(uint32_t adc_periph)
859 {
860 FlagStatus reval = RESET;
861 if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STRC)){
862 reval = SET;
863 }
864 return reval;
865 }
866
867 /*!
868 \brief get the bit state of ADCx software inserted channel start conversion
869 \param[in] adc_periph: ADCx, x=0,1 only one among these parameters can be selected
870 \param[in] none
871 \param[out] none
872 \retval FlagStatus: SET or RESET
873 */
adc_inserted_software_startconv_flag_get(uint32_t adc_periph)874 FlagStatus adc_inserted_software_startconv_flag_get(uint32_t adc_periph)
875 {
876 FlagStatus reval = RESET;
877 if((uint32_t)RESET != (ADC_STAT(adc_periph) & ADC_STAT_STIC)){
878 reval = SET;
879 }
880 return reval;
881 }
882
883 /*!
884 \brief get the ADC interrupt bits
885 \param[in] adc_periph: ADCx,x=0,1
886 \param[in] adc_interrupt: the adc interrupt bits
887 only one parameter can be selected which is shown as below:
888 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
889 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
890 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
891 \param[out] none
892 \retval FlagStatus: SET or RESET
893 */
adc_interrupt_flag_get(uint32_t adc_periph,uint32_t adc_interrupt)894 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t adc_interrupt)
895 {
896 FlagStatus interrupt_flag = RESET;
897 uint32_t state;
898 /* check the interrupt bits */
899 switch(adc_interrupt){
900 case ADC_INT_FLAG_WDE:
901 /* get the ADC analog watchdog interrupt bits */
902 state = ADC_STAT(adc_periph) & ADC_STAT_WDE;
903 if((ADC_CTL0(adc_periph) & ADC_CTL0_WDEIE) && state){
904 interrupt_flag = SET;
905 }
906 break;
907 case ADC_INT_FLAG_EOC:
908 /* get the ADC end of group conversion interrupt bits */
909 state = ADC_STAT(adc_periph) & ADC_STAT_EOC;
910 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOCIE) && state){
911 interrupt_flag = SET;
912 }
913 break;
914 case ADC_INT_FLAG_EOIC:
915 /* get the ADC end of inserted group conversion interrupt bits */
916 state = ADC_STAT(adc_periph) & ADC_STAT_EOIC;
917 if((ADC_CTL0(adc_periph) & ADC_CTL0_EOICIE) && state){
918 interrupt_flag = SET;
919 }
920 break;
921 default:
922 break;
923 }
924 return interrupt_flag;
925 }
926
927 /*!
928 \brief clear the ADC flag
929 \param[in] adc_periph: ADCx,x=0,1
930 \param[in] adc_interrupt: the adc status flag
931 one or more parameters can be selected which are shown as below:
932 \arg ADC_INT_FLAG_WDE: analog watchdog interrupt
933 \arg ADC_INT_FLAG_EOC: end of group conversion interrupt
934 \arg ADC_INT_FLAG_EOIC: end of inserted group conversion interrupt
935 \param[out] none
936 \retval none
937 */
adc_interrupt_flag_clear(uint32_t adc_periph,uint32_t adc_interrupt)938 void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t adc_interrupt)
939 {
940 ADC_STAT(adc_periph) &= ~((uint32_t)adc_interrupt);
941 }
942
943 /*!
944 \brief enable ADC interrupt
945 \param[in] adc_periph: ADCx,x=0,1
946 \param[in] adc_interrupt: the adc interrupt
947 one or more parameters can be selected which are shown as below:
948 \arg ADC_INT_WDE: analog watchdog interrupt flag
949 \arg ADC_INT_EOC: end of group conversion interrupt flag
950 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
951 \param[out] none
952 \retval none
953 */
adc_interrupt_enable(uint32_t adc_periph,uint32_t adc_interrupt)954 void adc_interrupt_enable(uint32_t adc_periph , uint32_t adc_interrupt)
955 {
956 /* enable ADC analog watchdog interrupt */
957 if(0U != (adc_interrupt & ADC_INT_WDE)){
958 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_WDEIE;
959 }
960 /* enable ADC end of group conversion interrupt */
961 if(0U != (adc_interrupt & ADC_INT_EOC)){
962 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOCIE;
963 }
964 /* enable ADC end of inserted group conversion interrupt */
965 if(0U != (adc_interrupt & ADC_INT_EOIC)){
966 ADC_CTL0(adc_periph) |= (uint32_t) ADC_CTL0_EOICIE;
967 }
968 }
969
970 /*!
971 \brief disable ADC interrupt
972 \param[in] adc_periph: ADCx,x=0,1
973 \param[in] adc_interrupt: the adc interrupt flag
974 one or more parameters can be selected which are shown as below:
975 \arg ADC_INT_WDE: analog watchdog interrupt flag
976 \arg ADC_INT_EOC: end of group conversion interrupt flag
977 \arg ADC_INT_EOIC: end of inserted group conversion interrupt flag
978 \param[out] none
979 \retval none
980 */
adc_interrupt_disable(uint32_t adc_periph,uint32_t adc_interrupt)981 void adc_interrupt_disable(uint32_t adc_periph, uint32_t adc_interrupt)
982 {
983 /* disable ADC analog watchdog interrupt */
984 if(0U != (adc_interrupt & ADC_INT_WDE)){
985 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_WDEIE;
986 }
987 /* disable ADC end of group conversion interrupt */
988 if(0U != (adc_interrupt & ADC_INT_EOC)){
989 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOCIE;
990 }
991 /* disable ADC end of inserted group conversion interrupt */
992 if(0U != (adc_interrupt & ADC_INT_EOIC)){
993 ADC_CTL0(adc_periph) &= ~(uint32_t) ADC_CTL0_EOICIE;
994 }
995 }
996
