1 /* 2 * Copyright (c) 2021 YuLong Yao <feilongphone@gmail.com> 3 * SPDX-License-Identifier: Apache-2.0 4 */ 5 6 #ifndef GD32E103XX_AFIO_H_ 7 #define GD32E103XX_AFIO_H_ 8 9 #include "gd32-afio.h" 10 11 /** SPI0 (no remap) */ 12 #define GD32_SPI0_NORMP GD32_REMAP(0U, 0U, 0x1U, 0U) 13 /** SPI0 (remap) */ 14 #define GD32_SPI0_RMP GD32_REMAP(0U, 0U, 0x1U, 1U) 15 16 /** I2C0 (no remap) */ 17 #define GD32_I2C0_NORMP GD32_REMAP(0U, 1U, 0x1U, 0U) 18 /** I2C0 (remap) */ 19 #define GD32_I2C0_RMP GD32_REMAP(0U, 1U, 0x1U, 1U) 20 21 /** USART0 (no remap) */ 22 #define GD32_USART0_NORMP GD32_REMAP(0U, 2U, 0x1U, 0U) 23 /** USART0 (remap) */ 24 #define GD32_USART0_RMP GD32_REMAP(0U, 2U, 0x1U, 1U) 25 26 /** USART1 (no remap) */ 27 #define GD32_USART1_NORMP GD32_REMAP(0U, 3U, 0x1U, 0U) 28 /** USART1 (remap) */ 29 #define GD32_USART1_RMP GD32_REMAP(0U, 3U, 0x1U, 1U) 30 31 /** USART2 (no remap) */ 32 #define GD32_USART2_NORMP GD32_REMAP(0U, 4U, 0x3U, 0U) 33 /** USART2 (partial remap) */ 34 #define GD32_USART2_PRMP GD32_REMAP(0U, 4U, 0x3U, 1U) 35 /** USART2 (full remap) */ 36 #define GD32_USART2_FRMP GD32_REMAP(0U, 4U, 0x3U, 3U) 37 38 /** TIMER0 (no remap) */ 39 #define GD32_TIMER0_NORMP GD32_REMAP(0U, 6U, 0x3U, 0U) 40 /** TIMER0 (partial remap) */ 41 #define GD32_TIMER0_PRMP GD32_REMAP(0U, 6U, 0x3U, 1U) 42 /** TIMER0 (full remap) */ 43 #define GD32_TIMER0_FRMP GD32_REMAP(0U, 6U, 0x3U, 3U) 44 45 /** TIMER1 (no remap) */ 46 #define GD32_TIMER1_NORMP GD32_REMAP(0U, 8U, 0x3U, 0U) 47 /** TIMER1 (partial remap 1) */ 48 #define GD32_TIMER1_PRMP1 GD32_REMAP(0U, 8U, 0x3U, 1U) 49 /** TIMER1 (partial remap 2) */ 50 #define GD32_TIMER1_PRMP2 GD32_REMAP(0U, 8U, 0x3U, 2U) 51 /** TIMER1 (full remap) */ 52 #define GD32_TIMER1_FRMP GD32_REMAP(0U, 8U, 0x3U, 3U) 53 54 /** TIMER2 (no remap) */ 55 #define GD32_TIMER2_NORMP GD32_REMAP(0U, 10U, 0x3U, 0U) 56 /** TIMER2 (partial remap) */ 57 #define GD32_TIMER2_PRMP GD32_REMAP(0U, 10U, 0x3U, 2U) 58 /** TIMER2 (full remap) */ 59 #define GD32_TIMER2_FRMP GD32_REMAP(0U, 10U, 0x3U, 3U) 60 61 /** TIMER3 (no remap) */ 62 #define GD32_TIMER3_NORMP GD32_REMAP(0U, 12U, 0x1U, 0U) 63 /** TIMER3 (remap) */ 64 #define GD32_TIMER3_RMP GD32_REMAP(0U, 12U, 0x1U, 1U) 65 66 /** TIMER4CH3 (no remap) */ 67 #define GD32_TIMER4CH3_NORMP GD32_REMAP(0U, 16U, 0x1U, 0U) 68 /** TIMER4CH3 (remap) */ 69 #define GD32_TIMER4CH3_RMP GD32_REMAP(0U, 16U, 0x1U, 1U) 70 71 /** SPI2 (no remap) */ 72 #define GD32_SPI2_NORMP GD32_REMAP(0U, 28U, 0x1U, 0U) 73 /** SPI2 (remap) */ 74 #define GD32_SPI2_RMP GD32_REMAP(0U, 28U, 0x1U, 1U) 75 76 /** TIMER1_ITR0 (no remap) */ 77 #define GD32_TIMER1ITR0_NORMP GD32_REMAP(0U, 29U, 0x1U, 0U) 78 /** TIMER1_ITR0 (remap) */ 79 #define GD32_TIMER1ITR0_RMP GD32_REMAP(0U, 29U, 0x1U, 1U) 80 81 /** TIMER8 (no remap) */ 82 #define GD32_TIMER8_NORMP GD32_REMAP(1U, 5U, 0x1U, 0U) 83 /** TIMER8 (remap) */ 84 #define GD32_TIMER8_RMP GD32_REMAP(1U, 5U, 0x1U, 1U) 85 86 /** CTC (no remap) */ 87 #define GD32_CTC_NORMP GD32_REMAP(1U, 11U, 0x3U, 0U) 88 /** CTC (remap) */ 89 #define GD32_CTC_PRMP GD32_REMAP(1U, 11U, 0x3U, 1U) 90 91 #endif /* GD32E103XX_AFIO_H_ */ 92
