1 /*! 2 \file gd32a50x_usart.h 3 \brief definitions for the USART 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_USART_H 36 #define GD32A50X_USART_H 37 38 #include "gd32a50x.h" 39 40 #define USART1 USART_BASE 41 #define USART2 (USART_BASE + 0x00000400U) 42 #define USART0 (USART_BASE + 0x0000F400U) 43 44 /* registers definitions */ 45 #define USART_CTL0(usartx) REG32((usartx) + 0x00000000U) /*!< USART control register 0 */ 46 #define USART_CTL1(usartx) REG32((usartx) + 0x00000004U) /*!< USART control register 1 */ 47 #define USART_CTL2(usartx) REG32((usartx) + 0x00000008U) /*!< USART control register 2 */ 48 #define USART_BAUD(usartx) REG32((usartx) + 0x0000000CU) /*!< USART baud rate register */ 49 #define USART_GP(usartx) REG32((usartx) + 0x00000010U) /*!< USART guard time and prescaler register */ 50 #define USART_RT(usartx) REG32((usartx) + 0x00000014U) /*!< USART receiver timeout register */ 51 #define USART_CMD(usartx) REG32((usartx) + 0x00000018U) /*!< USART command register */ 52 #define USART_STAT(usartx) REG32((usartx) + 0x0000001CU) /*!< USART status register */ 53 #define USART_INTC(usartx) REG32((usartx) + 0x00000020U) /*!< USART status clear register */ 54 #define USART_RDATA(usartx) REG32((usartx) + 0x00000024U) /*!< USART receive data register */ 55 #define USART_TDATA(usartx) REG32((usartx) + 0x00000028U) /*!< USART transmit data register */ 56 #define USART_CHC(usartx) REG32((usartx) + 0x000000C0U) /*!< USART coherence control register */ 57 #define USART_RFCS(usartx) REG32((usartx) + 0x000000D0U) /*!< USART receive FIFO control and status register */ 58 59 /* bits definitions */ 60 /* USARTx_CTL0 */ 61 #define USART_CTL0_UEN BIT(0) /*!< enable USART */ 62 #define USART_CTL0_UESM BIT(1) /*!< enable USART in deep-sleep mode */ 63 #define USART_CTL0_REN BIT(2) /*!< enable receiver */ 64 #define USART_CTL0_TEN BIT(3) /*!< enable transmitter */ 65 #define USART_CTL0_IDLEIE BIT(4) /*!< enable idle line detected interrupt */ 66 #define USART_CTL0_RBNEIE BIT(5) /*!< renable ead data buffer not empty interrupt and overrun error interrupt */ 67 #define USART_CTL0_TCIE BIT(6) /*!< enable transmission complete interrupt */ 68 #define USART_CTL0_TBEIE BIT(7) /*!< enable transmitter register empty interrupt */ 69 #define USART_CTL0_PERRIE BIT(8) /*!< enable parity error interrupt */ 70 #define USART_CTL0_PM BIT(9) /*!< parity mode */ 71 #define USART_CTL0_PCEN BIT(10) /*!< enable parity control */ 72 #define USART_CTL0_WM0 BIT(11) /*!< wakeup method in mute mode */ 73 #define USART_CTL0_WL BIT(12) /*!< word length */ 74 #define USART_CTL0_MEN BIT(13) /*!< enable mute mode */ 75 #define USART_CTL0_AMIE BIT(14) /*!< enable address match interrupt */ 76 #define USART_CTL0_OVSMOD BIT(15) /*!< oversample mode */ 77 #define USART_CTL0_DED BITS(16,20) /*!< enable driver deassertion time */ 78 #define USART_CTL0_DEA BITS(21,25) /*!< enable driver assertion time */ 79 #define USART_CTL0_RTIE BIT(26) /*!< enable receiver timeout interrupt */ 80 #define USART_CTL0_EBIE BIT(27) /*!< enable end of block interrupt */ 81 #define USART_CTL0_WM1 BIT(28) /*!< enable driver assertion time */ 82 83 /* USARTx_CTL1 */ 84 #define USART_CTL1_ADDM BIT(4) /*!< address detection mode */ 85 #define USART_CTL1_LBLEN BIT(5) /*!< LIN break frame length */ 86 #define USART_CTL1_LBDIE BIT(6) /*!< LIN break detection interrupt enable */ 87 #define USART_CTL1_CLEN BIT(8) /*!< last bit clock pulse */ 88 #define USART_CTL1_CPH BIT(9) /*!< clock phase */ 89 #define USART_CTL1_CPL BIT(10) /*!< clock polarity */ 90 #define USART_CTL1_CKEN BIT(11) /*!< ck pin enable */ 91 #define USART_CTL1_STB BITS(12,13) /*!< stop bits length */ 92 #define USART_CTL1_LMEN BIT(14) /*!< LIN mode enable */ 93 #define USART_CTL1_STRP BIT(15) /*!< swap TX/RX pins */ 94 #define USART_CTL1_RINV BIT(16) /*!< RX pin level inversion */ 95 #define USART_CTL1_TINV BIT(17) /*!< TX pin level inversion */ 96 #define USART_CTL1_DINV BIT(18) /*!< data bit level inversion */ 97 #define USART_CTL1_MSBF BIT(19) /*!< most significant bit first */ 98 #define USART_CTL1_RTEN BIT(23) /*!< receiver timeout enable */ 99 #define USART_CTL1_ADDR_DATA BITS(24,31) /*!< address of the USART terminal */ 100 101 /* USARTx_CTL2 */ 102 #define USART_CTL2_ERRIE BIT(0) /*!< enable error interrupt in multibuffer communication */ 103 #define USART_CTL2_IREN BIT(1) /*!< enable IrDA mode */ 104 #define USART_CTL2_IRLP BIT(2) /*!< IrDA low-power */ 105 #define USART_CTL2_HDEN BIT(3) /*!< enable half-duplex */ 106 #define USART_CTL2_NKEN BIT(4) /*!< enable NACK in smartcard mode */ 107 #define USART_CTL2_SCEN BIT(5) /*!< enable smartcard mode */ 108 #define USART_CTL2_DENR BIT(6) /*!< enable DMA for reception */ 109 #define USART_CTL2_DENT BIT(7) /*!< enable DMA for transmission */ 110 #define USART_CTL2_RTSEN BIT(8) /*!< enable RTS */ 111 #define USART_CTL2_CTSEN BIT(9) /*!< enable CTS */ 112 #define USART_CTL2_CTSIE BIT(10) /*!< enable CTS interrupt */ 113 #define USART_CTL2_OSB BIT(11) /*!< one sample bit mode */ 114 #define USART_CTL2_OVRD BIT(12) /*!< disable overrun */ 115 #define USART_CTL2_DDRE BIT(13) /*!< disable DMA on reception error */ 116 #define USART_CTL2_DEM BIT(14) /*!< enable driver mode */ 117 #define USART_CTL2_DEP BIT(15) /*!< enable driver polarity mode */ 118 #define USART_CTL2_SCRTNUM BITS(17,19) /*!< smartcard auto-retry number */ 119 #define USART_CTL2_WUM BITS(20,21) /*!< wakeup mode from deep-sleep mode */ 120 #define USART_CTL2_WUIE BIT(22) /*!< enable wakeup from deep-sleep mode interrupt */ 121 122 /* USARTx_BAUD */ 123 #define USART_BAUD_FRADIV BITS(0,3) /*!< fraction of baud-rate divider */ 124 #define USART_BAUD_INTDIV BITS(4,15) /*!< integer of baud-rate divider */ 125 126 /* USARTx_GP */ 127 #define USART_GP_PSC BITS(0,7) /*!< prescaler value for dividing the system clock */ 128 #define USART_GP_GUAT BITS(8,15) /*!< guard time value in smartcard mode */ 129 130 /* USARTx_RT */ 131 #define USART_RT_RT BITS(0,23) /*!< receiver timeout threshold */ 132 #define USART_RT_BL BITS(24,31) /*!< block length */ 133 134 /* USARTx_CMD */ 135 #define USART_CMD_SBKCMD BIT(1) /*!< send break command */ 136 #define USART_CMD_MMCMD BIT(2) /*!< mute mode command */ 137 #define USART_CMD_RXFCMD BIT(3) /*!< receive data flush command */ 138 #define USART_CMD_TXFCMD BIT(4) /*!< transmit data flush request */ 139 140 /* USARTx_STAT */ 141 #define USART_STAT_PERR BIT(0) /*!< parity error flag */ 142 #define USART_STAT_FERR BIT(1) /*!< frame error flag */ 143 #define USART_STAT_NERR BIT(2) /*!< noise error flag */ 144 #define USART_STAT_ORERR BIT(3) /*!< overrun error */ 145 #define USART_STAT_IDLEF BIT(4) /*!< idle line detected flag */ 146 #define USART_STAT_RBNE BIT(5) /*!< read data buffer not empty */ 147 #define USART_STAT_TC BIT(6) /*!< transmission completed */ 148 #define USART_STAT_TBE BIT(7) /*!< transmit data register empty */ 149 #define USART_STAT_LBDF BIT(8) /*!< LIN break detected flag */ 150 #define USART_STAT_CTSF BIT(9) /*!< CTS change flag */ 151 #define USART_STAT_CTS BIT(10) /*!< CTS level */ 152 #define USART_STAT_RTF BIT(11) /*!< receiver timeout flag */ 153 #define USART_STAT_EBF BIT(12) /*!< end of block flag */ 154 #define USART_STAT_BSY BIT(16) /*!< busy flag */ 155 #define USART_STAT_AMF BIT(17) /*!< address match flag */ 156 #define USART_STAT_SBF BIT(18) /*!< send break flag */ 157 #define USART_STAT_RWU BIT(19) /*!< receiver wakeup from mute mode */ 158 #define USART_STAT_WUF BIT(20) /*!< wakeup from deep-sleep mode flag */ 159 #define USART_STAT_TEA BIT(21) /*!< transmit enable acknowledge flag */ 160 #define USART_STAT_REA BIT(22) /*!< receive enable acknowledge flag */ 161 162 /* USARTx_INTC */ 163 #define USART_INTC_PEC BIT(0) /*!< clear parity error */ 164 #define USART_INTC_FEC BIT(1) /*!< clear frame error flag */ 165 #define USART_INTC_NEC BIT(2) /*!< clear noise detected */ 166 #define USART_INTC_OREC BIT(3) /*!< clear overrun error */ 167 #define USART_INTC_IDLEC BIT(4) /*!< clear idle line detected */ 168 #define USART_INTC_TCC BIT(6) /*!< clear transmission complete */ 169 #define USART_INTC_LBDC BIT(8) /*!< clear LIN break detected */ 170 #define USART_INTC_CTSC BIT(9) /*!< clear CTS change */ 171 #define USART_INTC_RTC BIT(11) /*!< clear receiver timeout */ 172 #define USART_INTC_EBC BIT(12) /*!< clear end of timeout */ 173 #define USART_INTC_AMC BIT(17) /*!< clear address match */ 174 #define USART_INTC_WUC BIT(20) /*!< clear wakeup from deep-sleep mode */ 175 176 /* USARTx_RDATA */ 177 #define USART_RDATA_RDATA BITS(0,8) /*!< receive data value */ 178 179 /* USARTx_TDATA */ 180 #define USART_TDATA_TDATA BITS(0,8) /*!< transmit data value */ 181 182 /* USARTx_CHC */ 183 #define USART_CHC_HCM BIT(0) /*!< hardware flow control coherence mode */ 184 #define USART_CHC_EPERR BIT(8) /*!< early parity error flag */ 185 186 /* USARTx_RFCS */ 187 #define USART_RFCS_ELNACK BIT(0) /*!< early NACK */ 188 #define USART_RFCS_RFEN BIT(8) /*!< enable receive FIFO */ 189 #define USART_RFCS_RFFIE BIT(9) /*!< enable receive FIFO full interrupt */ 190 #define USART_RFCS_RFE BIT(10) /*!< receive FIFO empty flag */ 191 #define USART_RFCS_RFF BIT(11) /*!< receive FIFO full flag */ 192 #define USART_RFCS_RFCNT BITS(12,14) /*!< receive FIFO counter number */ 193 #define USART_RFCS_RFFINT BIT(15) /*!< receive FIFO full interrupt flag */ 194 195 /* constants definitions */ 196 /* define the USART bit position and its register index offset */ 197 #define USART_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 198 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 199 #define USART_BIT_POS(val) ((uint32_t)(val) & 0x0000001FU) 200 #define USART_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 201 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 202 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) 203 #define USART_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 204 205 /* register offset */ 206 #define USART_CTL0_REG_OFFSET 0x00000000U /*!< CTL0 register offset */ 207 #define USART_CTL1_REG_OFFSET 0x00000004U /*!< CTL1 register offset */ 208 #define USART_CTL2_REG_OFFSET 0x00000008U /*!< CTL2 register offset */ 209 #define USART_STAT_REG_OFFSET 0x0000001CU /*!< STAT register offset */ 210 #define USART_CHC_REG_OFFSET 0x000000C0U /*!< CHC register offset */ 211 #define USART_RFCS_REG_OFFSET 0x000000D0U /*!< RFCS register offset */ 212 213 /* USART flags */ 214 typedef enum{ 215 /* flags in STAT register */ 216 USART_FLAG_REA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 22U), /*!< receive enable acknowledge flag */ 217 USART_FLAG_TEA = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 21U), /*!< transmit enable acknowledge flag */ 218 USART_FLAG_WU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode flag */ 219 USART_FLAG_RWU = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 19U), /*!< receiver wakeup from mute mode */ 220 USART_FLAG_SB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 18U), /*!< send break flag */ 221 USART_FLAG_AM = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 17U), /*!< ADDR match flag */ 222 USART_FLAG_BSY = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 16U), /*!< busy flag */ 223 USART_FLAG_EB = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 12U), /*!< end of block flag */ 224 USART_FLAG_RT = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout flag */ 225 USART_FLAG_CTS = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 10U), /*!< CTS level */ 226 USART_FLAG_CTSF = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 9U), /*!< CTS change flag */ 227 USART_FLAG_LBD = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected flag */ 228 USART_FLAG_TBE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 7U), /*!< transmit data buffer empty */ 229 USART_FLAG_TC = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 6U), /*!< transmission complete */ 230 USART_FLAG_RBNE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty */ 231 USART_FLAG_IDLE = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected flag */ 232 USART_FLAG_ORERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 3U), /*!< overrun error */ 233 USART_FLAG_NERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 2U), /*!< noise error flag */ 234 USART_FLAG_FERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 1U), /*!< frame error flag */ 235 USART_FLAG_PERR = USART_REGIDX_BIT(USART_STAT_REG_OFFSET, 0U), /*!< parity error flag */ 236 /* flags in CHC register */ 237 USART_FLAG_EPERR = USART_REGIDX_BIT(USART_CHC_REG_OFFSET, 8U), /*!< early parity error flag */ 238 /* flags in RFCS register */ 239 USART_FLAG_RFFINT = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt flag */ 240 USART_FLAG_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 11U), /*!< receive FIFO full flag */ 241 USART_FLAG_RFE = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 10U), /*!< receive FIFO empty flag */ 242 }usart_flag_enum; 243 244 /* USART interrupt flags */ 245 typedef enum 246 { 247 /* interrupt flags in CTL0 register */ 248 USART_INT_FLAG_EB = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 27U, USART_STAT_REG_OFFSET, 12U), /*!< end of block interrupt and flag */ 249 USART_INT_FLAG_RT = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 26U, USART_STAT_REG_OFFSET, 11U), /*!< receiver timeout interrupt and flag */ 250 USART_INT_FLAG_AM = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 14U, USART_STAT_REG_OFFSET, 17U), /*!< address match interrupt and flag */ 251 USART_INT_FLAG_PERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 8U, USART_STAT_REG_OFFSET, 0U), /*!< parity error interrupt and flag */ 252 USART_INT_FLAG_TBE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 7U, USART_STAT_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt and flag */ 253 USART_INT_FLAG_TC = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 6U), /*!< transmission complete interrupt and flag */ 254 USART_INT_FLAG_RBNE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and flag */ 255 USART_INT_FLAG_RBNE_ORERR = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 5U, USART_STAT_REG_OFFSET, 3U), /*!< read data buffer not empty interrupt and overrun error flag */ 256 USART_INT_FLAG_IDLE = USART_REGIDX_BIT2(USART_CTL0_REG_OFFSET, 4U, USART_STAT_REG_OFFSET, 4U), /*!< IDLE line detected interrupt and flag */ 257 /* interrupt flags in CTL1 register */ 258 USART_INT_FLAG_LBD = USART_REGIDX_BIT2(USART_CTL1_REG_OFFSET, 6U, USART_STAT_REG_OFFSET, 8U), /*!< LIN break detected interrupt and flag */ 259 /* interrupt flags in CTL2 register */ 260 USART_INT_FLAG_WU = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 22U, USART_STAT_REG_OFFSET, 20U), /*!< wakeup from deep-sleep mode interrupt and flag */ 261 USART_INT_FLAG_CTS = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 10U, USART_STAT_REG_OFFSET, 9U), /*!< CTS interrupt and flag */ 262 USART_INT_FLAG_ERR_NERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 2U), /*!< error interrupt and noise error flag */ 263 USART_INT_FLAG_ERR_ORERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 3U), /*!< error interrupt and overrun error */ 264 USART_INT_FLAG_ERR_FERR = USART_REGIDX_BIT2(USART_CTL2_REG_OFFSET, 0U, USART_STAT_REG_OFFSET, 1U), /*!< error interrupt and frame error flag */ 265 /* interrupt flags in RFCS register */ 266 USART_INT_FLAG_RFF = USART_REGIDX_BIT2(USART_RFCS_REG_OFFSET, 9U, USART_RFCS_REG_OFFSET, 15U), /*!< receive FIFO full interrupt and flag */ 267 }usart_interrupt_flag_enum; 268 269 /* enable or disable USART interrupt */ 270 typedef enum 271 { 272 /* interrupt in CTL0 register */ 273 USART_INT_EB = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 27U), /*!< end of block interrupt */ 274 USART_INT_RT = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 26U), /*!< receiver timeout interrupt */ 275 USART_INT_AM = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 14U), /*!< address match interrupt */ 276 USART_INT_PERR = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 8U), /*!< parity error interrupt */ 277 USART_INT_TBE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 7U), /*!< transmitter buffer empty interrupt */ 278 USART_INT_TC = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 6U), /*!< transmission complete interrupt */ 279 USART_INT_RBNE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 5U), /*!< read data buffer not empty interrupt and overrun error interrupt */ 280 USART_INT_IDLE = USART_REGIDX_BIT(USART_CTL0_REG_OFFSET, 4U), /*!< IDLE line detected interrupt */ 281 /* interrupt in CTL1 register */ 282 USART_INT_LBD = USART_REGIDX_BIT(USART_CTL1_REG_OFFSET, 6U), /*!< LIN break detected interrupt */ 283 /* interrupt in CTL2 register */ 284 USART_INT_WU = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 22U), /*!< wakeup from deep-sleep mode interrupt */ 285 USART_INT_CTS = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 10U), /*!< CTS interrupt */ 286 USART_INT_ERR = USART_REGIDX_BIT(USART_CTL2_REG_OFFSET, 0U), /*!< error interrupt */ 287 /* interrupt in RFCS register */ 288 USART_INT_RFF = USART_REGIDX_BIT(USART_RFCS_REG_OFFSET, 9U), /*!< receive FIFO full interrupt */ 289 }usart_interrupt_enum; 290 291 /* configure USART invert */ 292 typedef enum { 293 /* data bit level inversion */ 294 USART_DINV_ENABLE, /*!< data bit level inversion */ 295 USART_DINV_DISABLE, /*!< data bit level not inversion */ 296 /* TX pin level inversion */ 297 USART_TXPIN_ENABLE, /*!< TX pin level inversion */ 298 USART_TXPIN_DISABLE, /*!< TX pin level not inversion */ 299 /* RX pin level inversion */ 300 USART_RXPIN_ENABLE, /*!< RX pin level inversion */ 301 USART_RXPIN_DISABLE, /*!< RX pin level not inversion */ 302 /* swap TX/RX pins */ 303 USART_SWAP_ENABLE, /*!< swap TX/RX pins */ 304 USART_SWAP_DISABLE, /*!< not swap TX/RX pins */ 305 }usart_invert_enum; 306 307 /* configure USART receiver */ 308 #define CTL0_REN(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 309 #define USART_RECEIVE_ENABLE CTL0_REN(1) /*!< enable receiver */ 310 #define USART_RECEIVE_DISABLE CTL0_REN(0) /*!< disable receiver */ 311 312 /* configure USART transmitter */ 313 #define CTL0_TEN(regval) (BIT(3) & ((uint32_t)(regval) << 3)) 314 #define USART_TRANSMIT_ENABLE CTL0_TEN(1) /*!< enable transmitter */ 315 #define USART_TRANSMIT_DISABLE CTL0_TEN(0) /*!< disable transmitter */ 316 317 /* USART parity bits definitions */ 318 #define CTL0_PM(regval) (BITS(9,10) & ((uint32_t)(regval) << 9)) 319 #define USART_PM_NONE CTL0_PM(0) /*!< no parity */ 320 #define USART_PM_EVEN CTL0_PM(2) /*!< even parity */ 321 #define USART_PM_ODD CTL0_PM(3) /*!< odd parity */ 322 323 /* USART wakeup method in mute mode */ 324 #define CTL0_WM(regval1, regval2) ((BIT(11) & ((uint32_t)(regval1) << 11)) | (BIT(28) & ((uint32_t)(regval2) << 28))) 325 #define USART_WM_IDLE CTL0_WM(0, 0) /*!< idle line */ 326 #define USART_WM_ADDR CTL0_WM(1, 0) /*!< address match */ 327 #define USART_WM_DATA CTL0_WM(1, 1) /*!< data match */ 328 329 /* USART word length definitions */ 330 #define CTL0_WL(regval) (BIT(12) & ((uint32_t)(regval) << 12)) 331 #define USART_WL_8BIT CTL0_WL(0) /*!< 8 bits */ 332 #define USART_WL_9BIT CTL0_WL(1) /*!< 9 bits */ 333 334 /* USART oversample mode */ 335 #define CTL0_OVSMOD(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 336 #define USART_OVSMOD_8 CTL0_OVSMOD(1) /*!< oversampling by 8 */ 337 #define USART_OVSMOD_16 CTL0_OVSMOD(0) /*!< oversampling by 16 */ 338 339 /* USART address detection mode */ 340 #define CTL1_ADDM(regval) (BIT(4) & ((uint32_t)(regval) << 4)) 341 #define USART_ADDM_4BIT CTL1_ADDM(0) /*!< 4-bit address detection */ 342 #define USART_ADDM_FULLBIT CTL1_ADDM(1) /*!< full-bit address detection */ 343 344 /* USART LIN break frame length */ 345 #define CTL1_LBLEN(regval) (BIT(5) & ((uint32_t)(regval) << 5)) 346 #define USART_LBLEN_10B CTL1_LBLEN(0) /*!< 10 bits break detection */ 347 #define USART_LBLEN_11B CTL1_LBLEN(1) /*!< 11 bits break detection */ 348 349 /* USART last bit clock pulse */ 350 #define CTL1_CLEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 351 #define USART_CLEN_NONE CTL1_CLEN(0) /*!< clock pulse of the last data bit (MSB) is not output to the CK pin */ 352 #define USART_CLEN_EN CTL1_CLEN(1) /*!< clock pulse of the last data bit (MSB) is output to the CK pin */ 353 354 /* USART clock phase */ 355 #define CTL1_CPH(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 356 #define USART_CPH_1CK CTL1_CPH(0) /*!< first clock transition is the first data capture edge */ 357 #define USART_CPH_2CK CTL1_CPH(1) /*!< second clock transition is the first data capture edge */ 358 359 /* USART clock polarity */ 360 #define CTL1_CPL(regval) (BIT(10) & ((uint32_t)(regval) << 10)) 361 #define USART_CPL_LOW CTL1_CPL(0) /*!< steady low value on CK pin */ 362 #define USART_CPL_HIGH CTL1_CPL(1) /*!< steady high value on CK pin */ 363 364 /* USART stop bits definitions */ 365 #define CTL1_STB(regval) (BITS(12,13) & ((uint32_t)(regval) << 12)) 366 #define USART_STB_1BIT CTL1_STB(0) /*!< 1 bit */ 367 #define USART_STB_0_5BIT CTL1_STB(1) /*!< 0.5 bit */ 368 #define USART_STB_2BIT CTL1_STB(2) /*!< 2 bits */ 369 #define USART_STB_1_5BIT CTL1_STB(3) /*!< 1.5 bits */ 370 371 /* USART data is transmitted/received with the LSB/MSB first */ 372 #define CTL1_MSBF(regval) (BIT(19) & ((uint32_t)(regval) << 19)) 373 #define USART_MSBF_LSB CTL1_MSBF(0) /*!< LSB first */ 374 #define USART_MSBF_MSB CTL1_MSBF(1) /*!< MSB first */ 375 376 /* enable USART IrDA low-power */ 377 #define CTL2_IRLP(regval) (BIT(2) & ((uint32_t)(regval) << 2)) 378 #define USART_IRLP_LOW CTL2_IRLP(1) /*!< low-power */ 379 #define USART_IRLP_NORMAL CTL2_IRLP(0) /*!< normal */ 380 381 /* configure USART DMA */ 382 #define CTL2_RECEIVE_DMAEN(regval) (BIT(6) & ((uint32_t)(regval) << 6)) 383 #define CTL2_TRANSMIT_DMAEN(regval) (BIT(7) & ((uint32_t)(regval) << 7)) 384 #define USART_RECEIVE_DMA_ENABLE CTL2_RECEIVE_DMAEN(1) /*!< enable DMA request for reception */ 385 #define USART_RECEIVE_DMA_DISABLE CTL2_RECEIVE_DMAEN(0) /*!< disable DMA request for reception */ 386 #define USART_TRANSMIT_DMA_ENABLE CTL2_TRANSMIT_DMAEN(1) /*!< enable DMA request for transmission */ 387 #define USART_TRANSMIT_DMA_DISABLE CTL2_TRANSMIT_DMAEN(0) /*!< disable DMA request for transmission */ 388 389 /* configure USART RTS hardware flow control */ 390 #define CTL2_RTSEN(regval) (BIT(8) & ((uint32_t)(regval) << 8)) 391 #define USART_RTS_ENABLE CTL2_RTSEN(1) /*!< enable RTS hardware flow control */ 392 #define USART_RTS_DISABLE CTL2_RTSEN(0) /*!< disable RTS hardware flow control */ 393 394 /* configure USART CTS hardware flow control */ 395 #define CTL2_CTSEN(regval) (BIT(9) & ((uint32_t)(regval) << 9)) 396 #define USART_CTS_ENABLE CTL2_CTSEN(1) /*!< enable CTS hardware flow control */ 397 #define USART_CTS_DISABLE CTL2_CTSEN(0) /*!< disable CTS hardware flow control */ 398 399 /* configure USART one sample bit method */ 400 #define CTL2_OSB(regval) (BIT(11) & ((uint32_t)(regval) << 11)) 401 #define USART_OSB_1BIT CTL2_OSB(1) /*!< 1 sample bit */ 402 #define USART_OSB_3BIT CTL2_OSB(0) /*!< 3 sample bits */ 403 404 /* USART driver enable polarity mode */ 405 #define CTL2_DEP(regval) (BIT(15) & ((uint32_t)(regval) << 15)) 406 #define USART_DEP_HIGH CTL2_DEP(0) /*!< DE signal is active high */ 407 #define USART_DEP_LOW CTL2_DEP(1) /*!< DE signal is active low */ 408 409 /* USART wakeup mode from deep-sleep mode */ 410 #define CTL2_WUM(regval) (BITS(20,21) & ((uint32_t)(regval) << 20)) 411 #define USART_WUM_ADDR CTL2_WUM(0) /*!< WUF active on address match */ 412 #define USART_WUM_STARTB CTL2_WUM(2) /*!< WUF active on start bit */ 413 #define USART_WUM_RBNE CTL2_WUM(3) /*!< WUF active on RBNE */ 414 415 /* USART hardware flow control coherence mode */ 416 #define CHC_HCM(regval) (BIT(0) & ((uint32_t)(regval) << 0)) 417 #define USART_HCM_NONE CHC_HCM(0) /*!< nRTS signal equals to the rxne status register */ 418 #define USART_HCM_EN CHC_HCM(1) /*!< nRTS signal is set when the last data bit has been sampled */ 419 420 /* function declarations */ 421 /* initialization functions */ 422 /* reset USART */ 423 void usart_deinit(uint32_t usart_periph); 424 /* configure USART baud rate value */ 425 void usart_baudrate_set(uint32_t usart_periph, uint32_t baudval); 426 /* configure USART parity function */ 427 void usart_parity_config(uint32_t usart_periph, uint32_t paritycfg); 428 /* configure USART word length */ 429 void usart_word_length_set(uint32_t usart_periph, uint32_t wlen); 430 /* configure USART stop bit length */ 431 void usart_stop_bit_set(uint32_t usart_periph, uint32_t stblen); 432 /* enable USART */ 433 void usart_enable(uint32_t usart_periph); 434 /* disable USART */ 435 void usart_disable(uint32_t usart_periph); 436 /* configure USART transmitter */ 437 void usart_transmit_config(uint32_t usart_periph, uint32_t txconfig); 438 /* configure USART receiver */ 439 void usart_receive_config(uint32_t usart_periph, uint32_t rxconfig); 440 441 /* USART normal mode communication */ 442 /* data is transmitted/received with the LSB/MSB first */ 443 void usart_data_first_config(uint32_t usart_periph, uint32_t msbf); 444 /* configure USART inverted */ 445 void usart_invert_config(uint32_t usart_periph, usart_invert_enum invertpara); 446 /* enable the USART overrun function */ 447 void usart_overrun_enable(uint32_t usart_periph); 448 /* disable the USART overrun function */ 449 void usart_overrun_disable(uint32_t usart_periph); 450 /* configure the USART oversample mode */ 451 void usart_oversample_config(uint32_t usart_periph, uint32_t oversamp); 452 /* configure sample bit method */ 453 void usart_sample_bit_config(uint32_t usart_periph, uint32_t osb); 454 /* enable receiver timeout */ 455 void usart_receiver_timeout_enable(uint32_t usart_periph); 456 /* disable receiver timeout */ 457 void usart_receiver_timeout_disable(uint32_t usart_periph); 458 /* configure receiver timeout threshold */ 459 void usart_receiver_timeout_threshold_config(uint32_t usart_periph, uint32_t rtimeout); 460 /* USART transmit data function */ 461 void usart_data_transmit(uint32_t usart_periph, uint16_t data); 462 /* USART receive data function */ 463 uint16_t usart_data_receive(uint32_t usart_periph); 464 /* enable USART command */ 465 void usart_command_enable(uint32_t usart_periph, uint32_t cmdtype); 466 467 /* multi-processor communication */ 468 /* configure address of the USART */ 469 void usart_address_config(uint32_t usart_periph, uint8_t addr); 470 /* configure address detection mode */ 471 void usart_address_detection_mode_config(uint32_t usart_periph, uint32_t addmod); 472 /* enable mute mode */ 473 void usart_mute_mode_enable(uint32_t usart_periph); 474 /* disable mute mode */ 475 void usart_mute_mode_disable(uint32_t usart_periph); 476 /* configure wakeup method in mute mode */ 477 void usart_mute_mode_wakeup_config(uint32_t usart_periph, uint32_t wmethod); 478 479 /* LIN mode communication */ 480 /* enable LIN mode */ 481 void usart_lin_mode_enable(uint32_t usart_periph); 482 /* disable LIN mode */ 483 void usart_lin_mode_disable(uint32_t usart_periph); 484 /* LIN break detection length */ 485 void usart_lin_break_detection_length_config(uint32_t usart_periph, uint32_t lblen); 486 487 /* half-duplex communication */ 488 /* enable half-duplex mode */ 489 void usart_halfduplex_enable(uint32_t usart_periph); 490 /* disable half-duplex mode */ 491 void usart_halfduplex_disable(uint32_t usart_periph); 492 493 /* synchronous communication */ 494 /* enable clock */ 495 void usart_clock_enable(uint32_t usart_periph); 496 /* disable clock */ 497 void usart_clock_disable(uint32_t usart_periph); 498 /* configure USART synchronous mode parameters */ 499 void usart_synchronous_clock_config(uint32_t usart_periph, uint32_t clen, uint32_t cph, uint32_t cpl); 500 501 /* smartcard communication */ 502 /* configure guard time value in smartcard mode */ 503 void usart_guard_time_config(uint32_t usart_periph, uint32_t guat); 504 /* enable smartcard mode */ 505 void usart_smartcard_mode_enable(uint32_t usart_periph); 506 /* disable smartcard mode */ 507 void usart_smartcard_mode_disable(uint32_t usart_periph); 508 /* enable NACK in smartcard mode */ 509 void usart_smartcard_mode_nack_enable(uint32_t usart_periph); 510 /* disable NACK in smartcard mode */ 511 void usart_smartcard_mode_nack_disable(uint32_t usart_periph); 512 /* enable early NACK in smartcard mode */ 513 void usart_smartcard_mode_early_nack_enable(uint32_t usart_periph); 514 /* disable early NACK in smartcard mode */ 515 void usart_smartcard_mode_early_nack_disable(uint32_t usart_periph); 516 /* configure smartcard auto-retry number */ 517 void usart_smartcard_autoretry_config(uint32_t usart_periph, uint32_t scrtnum); 518 /* configure block length */ 519 void usart_block_length_config(uint32_t usart_periph, uint32_t bl); 520 521 /* IrDA communication */ 522 /* enable IrDA mode */ 523 void usart_irda_mode_enable(uint32_t usart_periph); 524 /* disable IrDA mode */ 525 void usart_irda_mode_disable(uint32_t usart_periph); 526 /* configure the peripheral clock prescaler in USART IrDA low-power or smartcard mode */ 527 void usart_prescaler_config(uint32_t usart_periph, uint32_t psc); 528 /* configure IrDA low-power */ 529 void usart_irda_lowpower_config(uint32_t usart_periph, uint32_t irlp); 530 531 /* hardware flow communication */ 532 /* configure hardware flow control RTS */ 533 void usart_hardware_flow_rts_config(uint32_t usart_periph, uint32_t rtsconfig); 534 /* configure hardware flow control CTS */ 535 void usart_hardware_flow_cts_config(uint32_t usart_periph, uint32_t ctsconfig); 536 537 /* coherence control */ 538 /* configure hardware flow control coherence mode */ 539 void usart_hardware_flow_coherence_config(uint32_t usart_periph, uint32_t hcm); 540 541 /* enable RS485 driver */ 542 void usart_rs485_driver_enable(uint32_t usart_periph); 543 /* disable RS485 driver */ 544 void usart_rs485_driver_disable(uint32_t usart_periph); 545 /* configure driver enable assertion time */ 546 void usart_driver_assertime_config(uint32_t usart_periph, uint32_t deatime); 547 /* configure driver enable de-assertion time */ 548 void usart_driver_deassertime_config(uint32_t usart_periph, uint32_t dedtime); 549 /* configure driver enable polarity mode */ 550 void usart_depolarity_config(uint32_t usart_periph, uint32_t dep); 551 552 /* USART DMA */ 553 /* configure USART DMA reception */ 554 void usart_dma_receive_config(uint32_t usart_periph, uint8_t dmaconfig); 555 /* configure USART DMA transmission */ 556 void usart_dma_transmit_config(uint32_t usart_periph, uint8_t dmaconfig); 557 /* disable DMA on reception error */ 558 void usart_reception_error_dma_disable(uint32_t usart_periph); 559 /* enable DMA on reception error */ 560 void usart_reception_error_dma_enable(uint32_t usart_periph); 561 562 /* enable USART to wakeup the MCU from deep-sleep mode */ 563 void usart_wakeup_enable(uint32_t usart_periph); 564 /* disable USART to wakeup the MCU from deep-sleep mode */ 565 void usart_wakeup_disable(uint32_t usart_periph); 566 /* configure the USART wakeup mode from deep-sleep mode */ 567 void usart_wakeup_mode_config(uint32_t usart_periph, uint32_t wum); 568 569 /* USART receive FIFO */ 570 /* enable receive FIFO */ 571 void usart_receive_fifo_enable(uint32_t usart_periph); 572 /* disable receive FIFO */ 573 void usart_receive_fifo_disable(uint32_t usart_periph); 574 /* read receive FIFO counter number */ 575 uint8_t usart_receive_fifo_counter_number(uint32_t usart_periph); 576 577 /* flag & interrupt functions */ 578 /* get USART status */ 579 FlagStatus usart_flag_get(uint32_t usart_periph, usart_flag_enum flag); 580 /* clear USART status */ 581 void usart_flag_clear(uint32_t usart_periph, usart_flag_enum flag); 582 /* enable USART interrupt */ 583 void usart_interrupt_enable(uint32_t usart_periph, usart_interrupt_enum interrupt); 584 /* disable USART interrupt */ 585 void usart_interrupt_disable(uint32_t usart_periph, usart_interrupt_enum interrupt); 586 587 /* get USART interrupt and flag status */ 588 FlagStatus usart_interrupt_flag_get(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 589 /* clear USART interrupt flag */ 590 void usart_interrupt_flag_clear(uint32_t usart_periph, usart_interrupt_flag_enum int_flag); 591 592 593 #endif /* GD32A50X_USART_H */ 594
