1 /*!
2 \file gd32a50x_dma.c
3 \brief DMA driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_dma.h"
36 #include <stdlib.h>
37
38 #define DMA_WRONG_HANDLE while(1){}
39
40 /* DMA functions */
41 /*!
42 \brief deinitialize DMA channel registers
43 \param[in] dma_periph: DMAx(x=0,1)
44 \param[in] channelx: specify which DMA channel is deinitialized
45 only one parameter can be selected which is shown as below:
46 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
47 \param[out] none
48 \retval none
49 */
dma_deinit(uint32_t dma_periph,dma_channel_enum channelx)50 void dma_deinit(uint32_t dma_periph, dma_channel_enum channelx)
51 {
52 /* disable DMA a channel */
53 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
54 /* reset DMA channel registers */
55 DMA_CHCTL(dma_periph, channelx) = DMA_CHCTL_RESET_VALUE;
56 DMA_CHCNT(dma_periph, channelx) = DMA_CHCNT_RESET_VALUE;
57 DMA_CHPADDR(dma_periph, channelx) = DMA_CHPADDR_RESET_VALUE;
58 DMA_CHMADDR(dma_periph, channelx) = DMA_CHMADDR_RESET_VALUE;
59 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(DMA_CHINTF_RESET_VALUE, channelx);
60 }
61
62 /*!
63 \brief initialize the parameters of DMA struct with the default values
64 \param[in] init_struct: the initialization data needed to initialize DMA channel
65 \param[out] none
66 \retval none
67 */
dma_struct_para_init(dma_parameter_struct * init_struct)68 void dma_struct_para_init(dma_parameter_struct* init_struct)
69 {
70 if(NULL == init_struct) {
71 DMA_WRONG_HANDLE
72 }
73
74 /* set the DMA struct with the default values */
75 init_struct->periph_addr = 0U;
76 init_struct->periph_width = 0U;
77 init_struct->periph_inc = (uint8_t)DMA_PERIPH_INCREASE_DISABLE;
78 init_struct->memory_addr = 0U;
79 init_struct->memory_width = 0U;
80 init_struct->memory_inc = (uint8_t)DMA_MEMORY_INCREASE_DISABLE;
81 init_struct->number = 0U;
82 init_struct->direction = (uint8_t)DMA_PERIPHERAL_TO_MEMORY;
83 init_struct->priority = (uint32_t)DMA_PRIORITY_LOW;
84 init_struct->request = DMA_REQUEST_M2M;
85 }
86
87 /*!
88 \brief initialize DMA channel
89 \param[in] dma_periph: DMAx(x=0,1)
90 \param[in] channelx: specify which DMA channel is initialized
91 only one parameter can be selected which is shown as below:
92 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
93 \param[in] init_struct: the data needed to initialize DMA channel
94 periph_addr: peripheral base address
95 periph_width: DMA_PERIPHERAL_WIDTH_8BIT,DMA_PERIPHERAL_WIDTH_16BIT,DMA_PERIPHERAL_WIDTH_32BIT
96 periph_inc: DMA_PERIPH_INCREASE_ENABLE,DMA_PERIPH_INCREASE_DISABLE
97 memory_addr: memory base address
98 memory_width: DMA_MEMORY_WIDTH_8BIT,DMA_MEMORY_WIDTH_16BIT,DMA_MEMORY_WIDTH_32BIT
99 memory_inc: DMA_MEMORY_INCREASE_ENABLE,DMA_MEMORY_INCREASE_DISABLE
100 direction: DMA_PERIPHERAL_TO_MEMORY,DMA_MEMORY_TO_PERIPHERAL
101 number: the number of remaining data to be transferred by the DMA
102 priority: DMA_PRIORITY_LOW,DMA_PRIORITY_MEDIUM,DMA_PRIORITY_HIGH,DMA_PRIORITY_ULTRA_HIGH
103 request: DMA_REQUEST_M2M, DMA_REQUEST_GENERATOR0, DMA_REQUEST_GENERATOR1, DMA_REQUEST_GENERATOR2
104 DMA_REQUEST_GENERATOR3, DMA_REQUEST_ADC, DMA_REQUEST_DAC_CH0, DMA_REQUEST_I2C1_RX
105 DMA_REQUEST_I2C1_TX, DMA_REQUEST_I2C0_RX, DMA_REQUEST_I2C0_TX, DMA_REQUESR_SSTAT0
106 DMA_REQUESR_SSTAT1, DMA_REQUESR_SSTAT2, DMA_REQUESR_SSTAT3, DMA_REQUEST_SPI0_RX
107 DMA_REQUEST_SPI0_TX, DMA_REQUEST_SPI1_RX, DMA_REQUEST_SPI1_TX, DMA_REQUEST_TIMER0_CH0
108 DMA_REQUEST_TIMER0_CH1, DMA_REQUEST_TIMER0_CH2, DMA_REQUEST_TIMER0_CH3, DMA_REQUEST_TIMER0_TI
109 DMA_REQUEST_TIMER0_UP, DMA_REQUEST_TIMER0_CO, DMA_REQUEST_TIMER0_MCH0, DMA_REQUEST_TIMER0_MCH1
110 DMA_REQUEST_TIMER0_MCH2, DMA_REQUEST_TIMER0_MCH3, DMA_REQUEST_TIMER1_CH0, DMA_REQUEST_TIMER1_CH1
111 DMA_REQUEST_TIMER1_CH2, DMA_REQUEST_TIMER1_CH3, DMA_REQUEST_TIMER1_TI, DMA_REQUEST_TIMER1_UP
112 DMA_REQUEST_TIMER7_CH0, DMA_REQUEST_TIMER7_CH1, DMA_REQUEST_TIMER7_CH2, DMA_REQUEST_TIMER7_CH3
113 DMA_REQUEST_TIMER7_TI, DMA_REQUEST_TIMER7_UP, DMA_REQUEST_TIMER7_CO, DMA_REQUEST_TIMER7_MCH0
114 DMA_REQUEST_TIMER7_MCH1, DMA_REQUEST_TIMER7_MCH2, DMA_REQUEST_TIMER7_MCH3, DMA_REQUEST_CAN1
115 DMA_REQUEST_CAN0, DMA_REQUEST_USART0_RX, DMA_REQUEST_USART0_TX, DMA_REQUEST_USART1_RX
116 DMA_REQUEST_USART1_TX, DMA_REQUEST_USART2_RX, DMA_REQUEST_USART2_TX, DMA_REQUEST_TIMER5_UP
117 DMA_REQUEST_TIMER6_UP, DMA_REQUEST_TIMER19_CH0, DMA_REQUEST_TIMER19_CH1, DMA_REQUEST_TIMER19_CH2
118 DMA_REQUEST_TIMER19_CH3, DMA_REQUEST_TIMER19_TI, DMA_REQUEST_TIMER19_UP, DMA_REQUEST_TIMER19_CO
119 DMA_REQUEST_TIMER19_MCH0, DMA_REQUEST_TIMER19_MCH1, DMA_REQUEST_TIMER19_MCH2, DMA_REQUEST_TIMER19_MCH3
120 DMA_REQUEST_TIMER20_CH0, DMA_REQUEST_TIMER20_CH1, DMA_REQUEST_TIMER20_CH2, DMA_REQUEST_TIMER20_CH3
121 DMA_REQUEST_TIMER20_TI, DMA_REQUEST_TIMER20_UP, DMA_REQUEST_TIMER20_CO, DMA_REQUEST_TIMER20_MCH0
122 DMA_REQUEST_TIMER20_MCH1, DMA_REQUEST_TIMER20_MCH2, DMA_REQUEST_TIMER20_MCH3
123 \param[out] none
124 \retval none
125 */
dma_init(uint32_t dma_periph,dma_channel_enum channelx,dma_parameter_struct * init_struct)126 void dma_init(uint32_t dma_periph, dma_channel_enum channelx, dma_parameter_struct* init_struct)
127 {
128 uint32_t ctl;
129
130 if(NULL == init_struct) {
131 DMA_WRONG_HANDLE
132 }
133
134 dma_channel_disable(dma_periph, channelx);
135
136 /* configure peripheral base address */
137 DMA_CHPADDR(dma_periph, channelx) = init_struct->periph_addr;
138
139 /* configure memory base address */
140 DMA_CHMADDR(dma_periph, channelx) = init_struct->memory_addr;
141
142 /* configure the number of remaining data to be transferred */
143 DMA_CHCNT(dma_periph, channelx) = (init_struct->number & DMA_CHANNEL_CNT_MASK);
144
145 /* configure peripheral transfer width, memory transfer width, channel priotity */
146 ctl = DMA_CHCTL(dma_periph, channelx);
147 ctl &= ~(DMA_CHXCTL_PWIDTH | DMA_CHXCTL_MWIDTH | DMA_CHXCTL_PRIO);
148 ctl |= (init_struct->periph_width | init_struct->memory_width | init_struct->priority);
149 DMA_CHCTL(dma_periph, channelx) = ctl;
150
151 /* configure peripheral increasing mode */
152 if(DMA_PERIPH_INCREASE_ENABLE == init_struct->periph_inc) {
153 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
154 } else {
155 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
156 }
157
158 /* configure memory increasing mode */
159 if(DMA_MEMORY_INCREASE_ENABLE == init_struct->memory_inc) {
160 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
161 } else {
162 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
163 }
164
165 /* configure the direction of data transfer */
166 if(DMA_PERIPHERAL_TO_MEMORY == init_struct->direction) {
167 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
168 } else {
169 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
170 }
171
172 if(DMA0 == dma_periph) {
173 DMAMUX_RM_CHXCFG((uint32_t)channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
174 DMAMUX_RM_CHXCFG((uint32_t)channelx) |= init_struct->request;
175 } else {
176 DMAMUX_RM_CHXCFG((uint32_t)channelx + 7U ) &= ~DMAMUX_RM_CHXCFG_MUXID;
177 DMAMUX_RM_CHXCFG((uint32_t)channelx + 7U ) |= init_struct->request;
178 }
179 }
180
181 /*!
182 \brief enable DMA circulation mode
183 \param[in] dma_periph: DMAx(x=0,1)
184 \param[in] channelx: specify which DMA channel to set
185 only one parameter can be selected which is shown as below:
186 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
187 \param[out] none
188 \retval none
189 */
dma_circulation_enable(uint32_t dma_periph,dma_channel_enum channelx)190 void dma_circulation_enable(uint32_t dma_periph, dma_channel_enum channelx)
191 {
192 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CMEN;
193 }
194
195 /*!
196 \brief disable DMA circulation mode
197 \param[in] dma_periph: DMAx(x=0,1)
198 \param[in] channelx: specify which DMA channel to set
199 only one parameter can be selected which is shown as below:
200 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
201 \param[out] none
202 \retval none
203 */
dma_circulation_disable(uint32_t dma_periph,dma_channel_enum channelx)204 void dma_circulation_disable(uint32_t dma_periph, dma_channel_enum channelx)
205 {
206 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CMEN;
207 }
208
209 /*!
210 \brief enable memory to memory mode
211 \param[in] dma_periph: DMAx(x=0,1)
212 \param[in] channelx: specify which DMA channel to set
213 only one parameter can be selected which is shown as below:
214 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
215 \param[out] none
216 \retval none
217 */
dma_memory_to_memory_enable(uint32_t dma_periph,dma_channel_enum channelx)218 void dma_memory_to_memory_enable(uint32_t dma_periph, dma_channel_enum channelx)
219 {
220 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_M2M;
221 }
222
223 /*!
224 \brief disable memory to memory mode
225 \param[in] dma_periph: DMAx(x=0,1)
226 \param[in] channelx: specify which DMA channel to set
227 only one parameter can be selected which is shown as below:
228 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
229 \param[out] none
230 \retval none
231 */
dma_memory_to_memory_disable(uint32_t dma_periph,dma_channel_enum channelx)232 void dma_memory_to_memory_disable(uint32_t dma_periph, dma_channel_enum channelx)
233 {
234 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_M2M;
235 }
236
237 /*!
238 \brief enable DMA channel
239 \param[in] dma_periph: DMAx(x=0,1)
240 \param[in] channelx: specify which DMA channel to set
241 only one parameter can be selected which is shown as below:
242 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
243 \param[out] none
244 \retval none
245 */
dma_channel_enable(uint32_t dma_periph,dma_channel_enum channelx)246 void dma_channel_enable(uint32_t dma_periph, dma_channel_enum channelx)
247 {
248 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_CHEN;
249 }
250
251 /*!
252 \brief disable DMA channel
253 \param[in] dma_periph: DMAx(x=0,1)
254 \param[in] channelx: specify which DMA channel to set
255 only one parameter can be selected which is shown as below:
256 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
257 \param[out] none
258 \retval none
259 */
dma_channel_disable(uint32_t dma_periph,dma_channel_enum channelx)260 void dma_channel_disable(uint32_t dma_periph, dma_channel_enum channelx)
261 {
262 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_CHEN;
263 }
264
265 /*!
266 \brief set DMA peripheral base address
267 \param[in] dma_periph: DMAx(x=0,1)
268 \param[in] channelx: specify which DMA channel to set peripheral base address
269 only one parameter can be selected which is shown as below:
270 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
271 \param[in] address: peripheral base address
272 \param[out] none
273 \retval none
274 */
dma_periph_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address)275 void dma_periph_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
276 {
277 DMA_CHPADDR(dma_periph, channelx) = address;
278 }
279
280 /*!
281 \brief set DMA memory base address
282 \param[in] dma_periph: DMAx(x=0,1)
283 \param[in] channelx: specify which DMA channel to set memory base address
284 only one parameter can be selected which is shown as below:
285 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
286 \param[in] address: memory base address
287 \param[out] none
288 \retval none
289 */
dma_memory_address_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t address)290 void dma_memory_address_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t address)
291 {
292 DMA_CHMADDR(dma_periph, channelx) = address;
293 }
294
295 /*!
296 \brief set the number of remaining data to be transferred by the DMA
297 \param[in] dma_periph: DMAx(x=0,1)
298 \param[in] channelx: specify which DMA channel to set number
299 only one parameter can be selected which is shown as below:
300 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
301 \param[in] number: the number of remaining data to be transferred by the DMA
302 \param[out] none
303 \retval none
304 */
dma_transfer_number_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t number)305 void dma_transfer_number_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t number)
306 {
307 DMA_CHCNT(dma_periph, channelx) = (number & DMA_CHANNEL_CNT_MASK);
308 }
309
310 /*!
311 \brief get the number of remaining data to be transferred by the DMA
312 \param[in] dma_periph: DMAx(x=0,1)
313 \param[in] channelx: specify which DMA channel to set number
314 only one parameter can be selected which is shown as below:
315 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
316 \param[out] none
317 \retval the number of remaining data to be transferred by the DMA
318 */
dma_transfer_number_get(uint32_t dma_periph,dma_channel_enum channelx)319 uint32_t dma_transfer_number_get(uint32_t dma_periph, dma_channel_enum channelx)
320 {
321 return (uint32_t)DMA_CHCNT(dma_periph, channelx);
322 }
323
324 /*!
325 \brief configure priority level of DMA channel
326 \param[in] dma_periph: DMAx(x=0,1)
327 \param[in] channelx: specify which DMA channel to set
328 only one parameter can be selected which is shown as below:
329 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
330 \param[in] priority: priority level of this channel
331 only one parameter can be selected which is shown as below:
332 \arg DMA_PRIORITY_LOW: low priority
333 \arg DMA_PRIORITY_MEDIUM: medium priority
334 \arg DMA_PRIORITY_HIGH: high priority
335 \arg DMA_PRIORITY_ULTRA_HIGH: ultra high priority
336 \param[out] none
337 \retval none
338 */
dma_priority_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t priority)339 void dma_priority_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t priority)
340 {
341 uint32_t ctl;
342
343 /* acquire DMA_CHxCTL register */
344 ctl = DMA_CHCTL(dma_periph, channelx);
345 /* assign regiser */
346 ctl &= ~DMA_CHXCTL_PRIO;
347 ctl |= priority;
348 DMA_CHCTL(dma_periph, channelx) = ctl;
349 }
350
351 /*!
352 \brief configure transfer data width of memory
353 \param[in] dma_periph: DMAx(x=0,1)
354 \param[in] channelx: specify which DMA channel to set
355 only one parameter can be selected which is shown as below:
356 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
357 \param[in] mwidth: transfer data width of memory
358 only one parameter can be selected which is shown as below:
359 \arg DMA_MEMORY_WIDTH_8BIT: transfer data width of memory is 8-bit
360 \arg DMA_MEMORY_WIDTH_16BIT: transfer data width of memory is 16-bit
361 \arg DMA_MEMORY_WIDTH_32BIT: transfer data width of memory is 32-bit
362 \param[out] none
363 \retval none
364 */
dma_memory_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t mwidth)365 void dma_memory_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t mwidth)
366 {
367 uint32_t ctl;
368
369 /* acquire DMA_CHxCTL register */
370 ctl = DMA_CHCTL(dma_periph, channelx);
371 /* assign regiser */
372 ctl &= ~DMA_CHXCTL_MWIDTH;
373 ctl |= mwidth;
374 DMA_CHCTL(dma_periph, channelx) = ctl;
375 }
376
377 /*!
378 \brief configure transfer data width of peripheral
379 \param[in] dma_periph: DMAx(x=0,1)
380 \param[in] channelx: specify which DMA channel to set
381 only one parameter can be selected which is shown as below:
382 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
383 \param[in] pwidth: transfer data width of peripheral
384 only one parameter can be selected which is shown as below:
385 \arg DMA_PERIPHERAL_WIDTH_8BIT: transfer data width of peripheral is 8-bit
386 \arg DMA_PERIPHERAL_WIDTH_16BIT: transfer data width of peripheral is 16-bit
387 \arg DMA_PERIPHERAL_WIDTH_32BIT: transfer data width of peripheral is 32-bit
388 \param[out] none
389 \retval none
390 */
dma_periph_width_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t pwidth)391 void dma_periph_width_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t pwidth)
392 {
393 uint32_t ctl;
394
395 /* acquire DMA_CHxCTL register */
396 ctl = DMA_CHCTL(dma_periph, channelx);
397 /* assign regiser */
398 ctl &= ~DMA_CHXCTL_PWIDTH;
399 ctl |= pwidth;
400 DMA_CHCTL(dma_periph, channelx) = ctl;
401 }
402
403 /*!
404 \brief enable next address increasement algorithm of memory
405 \param[in] dma_periph: DMAx(x=0,1)
406 \param[in] channelx: specify which DMA channel to set
407 only one parameter can be selected which is shown as below:
408 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
409 \param[out] none
410 \retval none
411 */
dma_memory_increase_enable(uint32_t dma_periph,dma_channel_enum channelx)412 void dma_memory_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
413 {
414 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_MNAGA;
415 }
416
417 /*!
418 \brief disable next address increasement algorithm of memory
419 \param[in] dma_periph: DMAx(x=0,1)
420 \param[in] channelx: specify which DMA channel to set
421 only one parameter can be selected which is shown as below:
422 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
423 \param[out] none
424 \retval none
425 */
dma_memory_increase_disable(uint32_t dma_periph,dma_channel_enum channelx)426 void dma_memory_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
427 {
428 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_MNAGA;
429 }
430
431 /*!
432 \brief enable next address increasement algorithm of peripheral
433 \param[in] dma_periph: DMAx(x=0,1)
434 \param[in] channelx: specify which DMA channel to set
435 only one parameter can be selected which is shown as below:
436 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
437 \param[out] none
438 \retval none
439 */
dma_periph_increase_enable(uint32_t dma_periph,dma_channel_enum channelx)440 void dma_periph_increase_enable(uint32_t dma_periph, dma_channel_enum channelx)
441 {
442 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_PNAGA;
443 }
444
445 /*!
446 \brief disable next address increasement algorithm of peripheral
447 \param[in] dma_periph: DMAx(x=0,1)
448 \param[in] channelx: specify which DMA channel to set
449 only one parameter can be selected which is shown as below:
450 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
451 \param[out] none
452 \retval none
453 */
dma_periph_increase_disable(uint32_t dma_periph,dma_channel_enum channelx)454 void dma_periph_increase_disable(uint32_t dma_periph, dma_channel_enum channelx)
455 {
456 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_PNAGA;
457 }
458
459 /*!
460 \brief configure the direction of data transfer on the channel
461 \param[in] dma_periph: DMAx(x=0,1)
462 \param[in] channelx: specify which DMA channel to set
463 only one parameter can be selected which is shown as below:
464 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
465 \param[in] direction: specify the direction of data transfer
466 only one parameter can be selected which is shown as below:
467 \arg DMA_PERIPHERAL_TO_MEMORY: read from peripheral and write to memory
468 \arg DMA_MEMORY_TO_PERIPHERAL: read from memory and write to peripheral
469 \param[out] none
470 \retval none
471 */
dma_transfer_direction_config(uint32_t dma_periph,dma_channel_enum channelx,uint32_t direction)472 void dma_transfer_direction_config(uint32_t dma_periph, dma_channel_enum channelx, uint32_t direction)
473 {
474 if(DMA_PERIPHERAL_TO_MEMORY == direction) {
475 DMA_CHCTL(dma_periph, channelx) &= ~DMA_CHXCTL_DIR;
476 } else {
477 DMA_CHCTL(dma_periph, channelx) |= DMA_CHXCTL_DIR;
478 }
479 }
480
481 /*!
482 \brief check DMA flag is set or not
483 \param[in] dma_periph: DMAx(x=0,1)
484 \param[in] channelx: specify which DMA channel to get flag
485 only one parameter can be selected which is shown as below:
486 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
487 \param[in] flag: specify get which flag
488 only one parameter can be selected which is shown as below:
489 \arg DMA_FLAG_G: global interrupt flag of channel
490 \arg DMA_FLAG_FTF: full transfer finish flag of channel
491 \arg DMA_FLAG_HTF: half transfer finish flag of channel
492 \arg DMA_FLAG_ERR: error flag of channel
493 \param[out] none
494 \retval FlagStatus: SET or RESET
495 */
dma_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag)496 FlagStatus dma_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
497 {
498 FlagStatus reval;
499
500 if(0U != (DMA_INTF(dma_periph) & DMA_FLAG_ADD(flag, channelx))) {
501 reval = SET;
502 } else {
503 reval = RESET;
504 }
505
506 return reval;
507 }
508
509 /*!
510 \brief clear a DMA channel flag
511 \param[in] dma_periph: DMAx(x=0,1)
512 \param[in] channelx: specify which DMA channel to clear flag
513 only one parameter can be selected which is shown as below:
514 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
515 \param[in] flag: specify get which flag
516 only one parameter can be selected which is shown as below:
517 \arg DMA_FLAG_G: global interrupt flag of channel
518 \arg DMA_FLAG_FTF: full transfer finish flag of channel
519 \arg DMA_FLAG_HTF: half transfer finish flag of channel
520 \arg DMA_FLAG_ERR: error flag of channel
521 \param[out] none
522 \retval none
523 */
dma_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t flag)524 void dma_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t flag)
525 {
526 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(flag, channelx);
527 }
528
529 /*!
530 \brief enable DMA interrupt
531 \param[in] dma_periph: DMAx(x=0,1)
532 \param[in] channelx: specify which DMA channel to set
533 only one parameter can be selected which is shown as below:
534 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
535 \param[in] source: specify which interrupt to enable
536 only one parameter can be selected which is shown as below:
537 \arg DMA_INT_ERR: channel error interrupt
538 \arg DMA_INT_HTF: channel half transfer finish interrupt
539 \arg DMA_INT_FTF: channel full transfer finish interrupt
540 \param[out] none
541 \retval none
542 */
dma_interrupt_enable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source)543 void dma_interrupt_enable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
544 {
545 DMA_CHCTL(dma_periph, channelx) |= source;
546 }
547
548 /*!
549 \brief disable DMA interrupt
550 \param[in] dma_periph: DMAx(x=0,1)
551 \param[in] channelx: specify which DMA channel to set
552 only one parameter can be selected which is shown as below:
553 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
554 \param[in] source: specify which interrupt to disable
555 only one parameter can be selected which is shown as below:
556 \arg DMA_INT_ERR: channel error interrupt
557 \arg DMA_INT_HTF: channel half transfer finish interrupt
558 \arg DMA_INT_FTF: channel full transfer finish interrupt
559 \param[out] none
560 \retval none
561 */
dma_interrupt_disable(uint32_t dma_periph,dma_channel_enum channelx,uint32_t source)562 void dma_interrupt_disable(uint32_t dma_periph, dma_channel_enum channelx, uint32_t source)
563 {
564 DMA_CHCTL(dma_periph, channelx) &= ~source;
565 }
566
567 /*!
568 \brief check DMA flag and interrupt enable bit is set or not
569 \param[in] dma_periph: DMAx(x=0,1)
570 \param[in] channelx: specify which DMA channel to get flag
571 only one parameter can be selected which is shown as below:
572 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
573 \param[in] flag: specify get which flag
574 only one parameter can be selected which is shown as below:
575 \arg DMA_INT_FLAG_FTF: transfer finish flag of channel
576 \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel
577 \arg DMA_INT_FLAG_ERR: error flag of channel
578 \param[out] none
579 \retval FlagStatus: SET or RESET
580 */
dma_interrupt_flag_get(uint32_t dma_periph,dma_channel_enum channelx,uint32_t int_flag)581 FlagStatus dma_interrupt_flag_get(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag)
582 {
583 uint32_t interrupt_enable = 0U, interrupt_flag = 0U;
584
585 switch(int_flag) {
586 case DMA_INT_FLAG_FTF:
587 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
588 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_FTFIE;
589 break;
590 case DMA_INT_FLAG_HTF:
591 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
592 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_HTFIE;
593 break;
594 case DMA_INT_FLAG_ERR:
595 interrupt_flag = DMA_INTF(dma_periph) & DMA_FLAG_ADD(int_flag, channelx);
596 interrupt_enable = DMA_CHCTL(dma_periph, channelx) & DMA_CHXCTL_ERRIE;
597 break;
598 default:
599 break;
600 }
601
602 if(interrupt_flag && interrupt_enable) {
603 return SET;
604 } else {
605 return RESET;
606 }
607 }
608
609 /*!
610 \brief clear a DMA channel interrupt flag
611 \param[in] dma_periph: DMAx(x=0,1)
612 \param[in] channelx: specify which DMA channel to clear flag
613 only one parameter can be selected which is shown as below:
614 \arg DMA_CHx(x=0..6 for DMA0, x = 0..4 for DMA1)
615 \param[in] flag: specify get which flag
616 only one parameter can be selected which is shown as below:
617 \arg DMA_INT_FLAG_G: global interrupt flag of channel
618 \arg DMA_INT_FLAG_FTF: transfer finish flag of channel
619 \arg DMA_INT_FLAG_HTF: half transfer finish flag of channel
620 \arg DMA_INT_FLAG_ERR: error flag of channel
621 \param[out] none
622 \retval none
623 */
dma_interrupt_flag_clear(uint32_t dma_periph,dma_channel_enum channelx,uint32_t int_flag)624 void dma_interrupt_flag_clear(uint32_t dma_periph, dma_channel_enum channelx, uint32_t int_flag)
625 {
626 DMA_INTC(dma_periph) |= DMA_FLAG_ADD(int_flag, channelx);
627 }
628
629 /* DMAMUX functions */
630 /*!
631 \brief initialize the parameters of DMAMUX synchronization mode structure with the default values
632 \param[in] none
633 \param[out] init_struct: the initialization data needed to initialize DMAMUX request multiplexer channel synchronization mode
634 \retval none
635 */
dmamux_sync_struct_para_init(dmamux_sync_parameter_struct * init_struct)636 void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct)
637 {
638 if(NULL == init_struct) {
639 DMA_WRONG_HANDLE
640 }
641
642 /* set the DMAMUX synchronization struct with the default values */
643 init_struct->sync_id = DMAMUX_SYNC_EVTX_OUT0;
644 init_struct->sync_polarity = DMAMUX_SYNC_RISING;
645 init_struct->request_number = 1U;
646 }
647
648 /*!
649 \brief initialize DMAMUX request multiplexer channel synchronization mode
650 \param[in] channelx: specify which DMAMUX request multiplexer channel is initialized
651 only one parameter can be selected which is shown as below:
652 \arg DMAMUX_MULTIPLEXER_CHx(x=0..11)
653 \param[in] init_struct: the data needed to initialize DMAMUX request multiplexer channel
654 sync_id: DMAMUX_SYNC_EXTI0, DMAMUX_SYNC_EXTI1, DMAMUX_SYNC_EXTI2, DMAMUX_SYNC_EXTI3,
655 DMAMUX_SYNC_EXTI4, DMAMUX_SYNC_EXTI5, DMAMUX_SYNC_EXTI6, DMAMUX_SYNC_EXTI7,
656 DMAMUX_SYNC_EXTI8, DMAMUX_SYNC_EXTI9, DMAMUX_SYNC_EXTI10, DMAMUX_SYNC_EXTI11,
657 DMAMUX_SYNC_EXTI12, DMAMUX_SYNC_EXTI13, DMAMUX_SYNC_EXTI14, DMAMUX_SYNC_EXTI15,
658 DMAMUX_SYNC_EVTX_OUT0, DMAMUX_SYNC_EVTX_OUT1, DMAMUX_SYNC_EVTX_OUT2, DMAMUX_SYNC_EVTX_OUT3,
659 DMAMUX_SYNC_TIMER20_CH0_O
660 sync_polarity: DMAMUX_SYNC_NO_EVENT, DMAMUX_SYNC_RISING, DMAMUX_SYNC_FALLING, DMAMUX_SYNC_RISING_FALLING
661 request_number: the number of DMA request that will be authorized after a sync event, from 1 to 32
662 \param[out] none
663 \retval none
664 */
dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx,dmamux_sync_parameter_struct * init_struct)665 void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamux_sync_parameter_struct *init_struct)
666 {
667 uint32_t cfg;
668
669 if(NULL == init_struct) {
670 DMA_WRONG_HANDLE
671 }
672
673 /* disable synchronization mode and event generation for DMA request forward number configuration */
674 DMAMUX_RM_CHXCFG(channelx) &= ~(DMAMUX_RM_CHXCFG_SYNCEN | DMAMUX_RM_CHXCFG_EVGEN);
675
676 /* configure synchronization input identification, synchronization input polarity, number of DMA requests to forward */
677 cfg = DMAMUX_RM_CHXCFG(channelx);
678 cfg &= ~(DMAMUX_RM_CHXCFG_SYNCID | DMAMUX_RM_CHXCFG_NBR | DMAMUX_RM_CHXCFG_SYNCP);
679 cfg |= (init_struct->sync_polarity | (init_struct->sync_id) | RM_CHXCFG_NBR(init_struct->request_number - 1U));
680 DMAMUX_RM_CHXCFG(channelx) = cfg;
681 }
682
683 /*!
684 \brief enable synchronization mode
685 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
686 only one parameter can be selected which is shown as below:
687 \arg DMAMUX_MULTIPLEXER_CHx(x=0..11)
688 \param[out] none
689 \retval none
690 */
dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx)691 void dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx)
692 {
693 DMAMUX_RM_CHXCFG(channelx) |= DMAMUX_RM_CHXCFG_SYNCEN;
694 }
695
696 /*!
697 \brief disable synchronization mode
698 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
699 only one parameter can be selected which is shown as below:
700 \arg DMAMUX_MULTIPLEXER_CHx(x=0..11)
701 \param[out] none
702 \retval none
703 */
dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx)704 void dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx)
705 {
706 DMAMUX_RM_CHXCFG(channelx) &= (~DMAMUX_RM_CHXCFG_SYNCEN);
707 }
708
709 /*!
710 \brief enable event generation
711 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
712 only one parameter can be selected which is shown as below:
713 \arg DMAMUX_MULTIPLEXER_CHx(x=0..11)
714 \param[out] none
715 \retval none
716 */
dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx)717 void dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx)
718 {
719 DMAMUX_RM_CHXCFG(channelx) |= DMAMUX_RM_CHXCFG_EVGEN;
720 }
721
722 /*!
723 \brief disable event generation
724 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
725 only one parameter can be selected which is shown as below:
726 \arg DMAMUX_MULTIPLEXER_CHx(x=0..11)
727 \param[out] none
728 \retval none
729 */
dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx)730 void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx)
731 {
732 DMAMUX_RM_CHXCFG(channelx) &= (~DMAMUX_RM_CHXCFG_EVGEN);
733 }
734
735 /*!
736 \brief initialize the parameters of DMAMUX request generator structure with the default values
737 \param[in] init_struct: the initialization data needed to initialize DMAMUX request generator channel
738 \param[out] none
739 \retval none
740 */
dmamux_gen_struct_para_init(dmamux_gen_parameter_struct * init_struct)741 void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct)
742 {
743 if(NULL == init_struct) {
744 DMA_WRONG_HANDLE
745 }
746
747 /* set the DMAMUX request generator structure with the default values */
748 init_struct->trigger_id = DMAMUX_TRIGGER_EVTX_OUT0;
749 init_struct->trigger_polarity = DMAMUX_GEN_RISING;
750 init_struct->request_number = 1U;
751 }
752
753 /*!
754 \brief initialize DMAMUX request generator channel
755 \param[in] channelx: specify which DMAMUX request generator channel is initialized
756 only one parameter can be selected which is shown as below:
757 \arg DMAMUX_GENCHx(x=0..3)
758 \param[in] init_struct: the data needed to initialize DMAMUX request generator channel
759 trigger_id: DMAMUX_TRIGGER_EXTI0, DMAMUX_TRIGGER_EXTI1, DMAMUX_TRIGGER_EXTI2, DMAMUX_TRIGGER_EXTI3,
760 DMAMUX_TRIGGER_EXTI4, DMAMUX_TRIGGER_EXTI5, DMAMUX_TRIGGER_EXTI6, DMAMUX_TRIGGER_EXTI7,
761 DMAMUX_TRIGGER_EXTI8, DMAMUX_TRIGGER_EXTI9, DMAMUX_TRIGGER_EXTI10, DMAMUX_TRIGGER_EXTI11,
762 DMAMUX_TRIGGER_EXTI12, DMAMUX_TRIGGER_EXTI13, DMAMUX_TRIGGER_EXTI14, DMAMUX_TRIGGER_EXTI15,
763 DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0, DMAMUX_TRIGGER_EVTX_OUT0,
764 DMAMUX_TRIGGER_TIMER20_CH0_O
765 trigger_polarity: DMAMUX_GEN_NO_EVENT, DMAMUX_GEN_RISING, DMAMUX_GEN_FALLING, DMAMUX_GEN_RISING_FALLING
766 request_number: the number of DMA request that will be generated after a signal event, from 1 to 32
767 \param[out] none
768 \retval none
769 */
dmamux_request_generator_init(dmamux_generator_channel_enum channelx,dmamux_gen_parameter_struct * init_struct)770 void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamux_gen_parameter_struct *init_struct)
771 {
772 uint32_t cfg;
773
774 if(NULL == init_struct) {
775 DMA_WRONG_HANDLE
776 }
777
778 /* disable DMAMUX request generator channel for DMA request generation number configuration */
779 DMAMUX_RG_CHXCFG(channelx) &= ~(DMAMUX_RG_CHXCFG_RGEN);
780
781 /* configure trigger input identification, trigger polarity, number of DMA requests to be generated */
782 cfg = DMAMUX_RG_CHXCFG(channelx);
783 cfg &= ~(DMAMUX_RG_CHXCFG_TID | DMAMUX_RG_CHXCFG_NBRG | DMAMUX_RG_CHXCFG_RGTP);
784 cfg |= (RG_CHXCFG_NBRG(init_struct->request_number - 1U) | init_struct->trigger_id | init_struct->trigger_polarity);
785 DMAMUX_RG_CHXCFG(channelx) = cfg;
786 }
787
788 /*!
789 \brief enable DMAMUX request generator channel
790 \param[in] channelx: specify which DMAMUX request generator channel is configured
791 only one parameter can be selected which is shown as below:
792 \arg DMAMUX_GENCHx(x=0..3)
793 \param[out] none
794 \retval none
795 */
dmamux_request_generator_channel_enable(dmamux_generator_channel_enum channelx)796 void dmamux_request_generator_channel_enable(dmamux_generator_channel_enum channelx)
797 {
798 DMAMUX_RG_CHXCFG(channelx) |= DMAMUX_RG_CHXCFG_RGEN;
799 }
800
801 /*!
802 \brief disable DMAMUX request generator channel
803 \param[in] channelx: specify which DMAMUX request generator channel is configured
804 only one parameter can be selected which is shown as below:
805 \arg DMAMUX_GENCHx(x=0..3)
806 \param[out] none
807 \retval none
808 */
dmamux_request_generator_channel_disable(dmamux_generator_channel_enum channelx)809 void dmamux_request_generator_channel_disable(dmamux_generator_channel_enum channelx)
810 {
811 DMAMUX_RG_CHXCFG(channelx) &= (~DMAMUX_RG_CHXCFG_RGEN);
812 }
813
814 /*!
815 \brief configure synchronization input polarity
816 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
817 only one parameter can be selected which is shown as below:
818 \arg DMAMUX_MUXCHx(x=0..11)
819 \param[in] polarity: synchronization input polarity
820 only one parameter can be selected which is shown as below:
821 \arg DMAMUX_SYNC_NO_EVENT: no event detection
822 \arg DMAMUX_SYNC_RISING: rising edge
823 \arg DMAMUX_SYNC_FALLING: falling edge
824 \arg DMAMUX_SYNC_RISING_FALLING: rising and falling edges
825 \param[out] none
826 \retval none
827 */
dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx,uint32_t polarity)828 void dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx, uint32_t polarity)
829 {
830 DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_SYNCP;
831 DMAMUX_RM_CHXCFG(channelx) |= polarity;
832 }
833
834 /*!
835 \brief configure number of DMA requests to forward
836 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
837 only one parameter can be selected which is shown as below:
838 \arg DMAMUX_MUXCHx(x=0..6)
839 \param[in] number: DMA requests number to forward
840 only one parameter can be selected which is shown as below:
841 \arg 1 - 32
842 \param[out] none
843 \retval none
844 */
dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx,uint32_t number)845 void dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx, uint32_t number)
846 {
847 DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_NBR;
848 DMAMUX_RM_CHXCFG(channelx) |= RM_CHXCFG_NBR(number - 1U);
849 }
850
851 /*!
852 \brief configure synchronization input identification
853 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
854 only one parameter can be selected which is shown as below:
855 \arg DMAMUX_MUXCHx(x=0..11)
856 \param[in] id: synchronization input identification
857 only one parameter can be selected which is shown as below:
858 \arg DMAMUX_SYNC_EXTI0: synchronization input is EXTI0
859 \arg DMAMUX_SYNC_EXTI1: synchronization input is EXTI1
860 \arg DMAMUX_SYNC_EXTI2: synchronization input is EXTI2
861 \arg DMAMUX_SYNC_EXTI3: synchronization input is EXTI3
862 \arg DMAMUX_SYNC_EXTI4: synchronization input is EXTI4
863 \arg DMAMUX_SYNC_EXTI5: synchronization input is EXTI5
864 \arg DMAMUX_SYNC_EXTI6: synchronization input is EXTI6
865 \arg DMAMUX_SYNC_EXTI7: synchronization input is EXTI7
866 \arg DMAMUX_SYNC_EXTI8: synchronization input is EXTI8
867 \arg DMAMUX_SYNC_EXTI9: synchronization input is EXTI9
868 \arg DMAMUX_SYNC_EXTI10: synchronization input is EXTI10
869 \arg DMAMUX_SYNC_EXTI11: synchronization input is EXTI11
870 \arg DMAMUX_SYNC_EXTI12: synchronization input is EXTI12
871 \arg DMAMUX_SYNC_EXTI13: synchronization input is EXTI13
872 \arg DMAMUX_SYNC_EXTI14: synchronization input is EXTI14
873 \arg DMAMUX_SYNC_EXTI15: synchronization input is EXTI15
874 \arg DMAMUX_SYNC_EVTX_OUT0: synchronization input is Evtx_out0
875 \arg DMAMUX_SYNC_EVTX_OUT1: synchronization input is Evtx_out1
876 \arg DMAMUX_SYNC_EVTX_OUT2: synchronization input is Evtx_out2
877 \arg DMAMUX_SYNC_EVTX_OUT3: synchronization input is Evtx_out3
878 \arg DMAMUX_SYNC_TIMER20_CH0_O: synchronization input is TIMER20_CH0_O
879 \param[out] none
880 \retval none
881 */
dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx,uint32_t id)882 void dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id)
883 {
884 DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_SYNCID;
885 DMAMUX_RM_CHXCFG(channelx) |= id;
886 }
887
888 /*!
889 \brief configure multiplexer input identification
890 \param[in] channelx: specify which DMAMUX request multiplexer channel is configured
891 only one parameter can be selected which is shown as below:
892 \arg DMAMUX_MUXCHx(x=0..11)
893 \param[in] id: input DMA request identification
894 only one parameter can be selected which is shown as below:
895 \arg DMA_REQUEST_M2M: memory to memory transfer
896 \arg DMA_REQUEST_GENERATOR0: DMAMUX request generator 0
897 \arg DMA_REQUEST_GENERATOR1: DMAMUX request generator 1
898 \arg DMA_REQUEST_GENERATOR2: DMAMUX request generator 2
899 \arg DMA_REQUEST_GENERATOR3: DMAMUX request generator 3
900 \arg DMA_REQUEST_ADC: DMAMUX ADC request
901 \arg DMA_REQUEST_DAC_CH0: DMAMUX DAC_CH0 request
902 \arg DMA_REQUEST_I2C1_RX: DMAMUX I2C1 RX request
903 \arg DMA_REQUEST_I2C1_TX: DMAMUX I2C1 TX request
904 \arg DMA_REQUEST_I2C0_RX: DMAMUX I2C0 RX request
905 \arg DMA_REQUEST_I2C0_TX: DMAMUX I2C0 TX request
906 \arg DMA_REQUESR_SSTAT0: DMAMUX SSTAT0 request
907 \arg DMA_REQUESR_SSTAT1: DMAMUX SSTAT1 request
908 \arg DMA_REQUESR_SSTAT2: DMAMUX SSTAT2 request
909 \arg DMA_REQUESR_SSTAT3: DMAMUX SSTAT3 request
910 \arg DMA_REQUEST_SPI0_RX DMAMUX SPI0 RX request
911 \arg DMA_REQUEST_SPI0_TX: DMAMUX SPI0 TX request
912 \arg DMA_REQUEST_SPI1_RX: DMAMUX SPI1 RX request
913 \arg DMA_REQUEST_SPI1_TX: DMAMUX SPI1 TX request
914 \arg DMA_REQUEST_TIMER0_CH0: DMAMUX TIMER0 CH0 request
915 \arg DMA_REQUEST_TIMER0_CH1: DMAMUX TIMER0 CH1 request
916 \arg DMA_REQUEST_TIMER0_CH2: DMAMUX TIMER0 CH2 request
917 \arg DMA_REQUEST_TIMER0_CH3: DMAMUX TIMER0 CH3 request
918 \arg DMA_REQUEST_TIMER0_TI: DMAMUX TIMER0 TI request
919 \arg DMA_REQUEST_TIMER0_UP: DMAMUX TIMER0 UP request
920 \arg DMA_REQUEST_TIMER0_CO: DMAMUX TIMER0 CO request
921 \arg DMA_REQUEST_TIMER0_MCH0: DMAMUX TIMER0 MCH0 request
922 \arg DMA_REQUEST_TIMER0_MCH1: DMAMUX TIMER0 MCH1 request
923 \arg DMA_REQUEST_TIMER0_MCH2: DMAMUX TIMER0 MCH2 request
924 \arg DMA_REQUEST_TIMER0_MCH3: DMAMUX TIMER0 MCH3 request
925 \arg DMA_REQUEST_TIMER1_CH0: DMAMUX TIMER1 CH0 request
926 \arg DMA_REQUEST_TIMER1_CH1: DMAMUX TIMER1 CH1 request
927 \arg DMA_REQUEST_TIMER1_CH2: DMAMUX TIMER1 CH2 request
928 \arg DMA_REQUEST_TIMER1_CH3: DMAMUX TIMER1 CH3 request
929 \arg DMA_REQUEST_TIMER1_TI: DMAMUX TIMER1 TI request
930 \arg DMA_REQUEST_TIMER1_UP: DMAMUX TIMER1 UP request
931 \arg DMA_REQUEST_TIMER7_CH0: DMAMUX TIMER7 CH0 request
932 \arg DMA_REQUEST_TIMER7_CH1: DMAMUX TIMER7 CH1 request
933 \arg DMA_REQUEST_TIMER7_CH2: DMAMUX TIMER7 CH2 request
934 \arg DMA_REQUEST_TIMER7_CH3: DMAMUX TIMER7 CH3 request
935 \arg DMA_REQUEST_TIMER7_TI: DMAMUX TIMER7 TI request
936 \arg DMA_REQUEST_TIMER7_UP: DMAMUX TIMER7 UP request
937 \arg DMA_REQUEST_TIMER7_CO: DMAMUX TIMER7 CO request
938 \arg DMA_REQUEST_TIMER7_MCH0: DMAMUX TIMER7 MCH0 request
939 \arg DMA_REQUEST_TIMER7_MCH1: DMAMUX TIMER7 MCH1 request
940 \arg DMA_REQUEST_TIMER7_MCH2: DMAMUX TIMER7 MCH2 request
941 \arg DMA_REQUEST_TIMER7_MCH3: DMAMUX TIMER7 MCH3 request
942 \arg DMA_REQUEST_CAN1: DMAMUX CAN1 request
943 \arg DMA_REQUEST_CAN0: DMAMUX CAN0 request
944 \arg DMA_REQUEST_USART0_RX: DMAMUX USART0 RX request
945 \arg DMA_REQUEST_USART0_TX: DMAMUX USART0 TX request
946 \arg DMA_REQUEST_USART1_RX: DMAMUX USART1 RX request
947 \arg DMA_REQUEST_USART1_TX: DMAMUX USART1 TX request
948 \arg DMA_REQUEST_USART2_RX: DMAMUX USART2 RX request
949 \arg DMA_REQUEST_USART2_TX: DMAMUX USART2 TX request
950 \arg DMA_REQUEST_TIMER5_UP: DMAMUX TIMER5 UP request
951 \arg DMA_REQUEST_TIMER6_UP: DMAMUX TIMER6 UP request
952 \arg DMA_REQUEST_TIMER19_CH0: DMAMUX TIMER19 CH0 request
953 \arg DMA_REQUEST_TIMER19_CH1: DMAMUX TIMER19 CH1 request
954 \arg DMA_REQUEST_TIMER19_CH2: DMAMUX TIMER19 CH2 request
955 \arg DMA_REQUEST_TIMER19_CH3: DMAMUX TIMER19 CH3 request
956 \arg DMA_REQUEST_TIMER19_TI: DMAMUX TIMER19 TI request
957 \arg DMA_REQUEST_TIMER19_UP: DMAMUX TIMER19 UP request
958 \arg DMA_REQUEST_TIMER19_CO: DMAMUX TIMER19 CO request
959 \arg DMA_REQUEST_TIMER19_MCH0: DMAMUX TIMER19 MCH0 request
960 \arg DMA_REQUEST_TIMER19_MCH1: DMAMUX TIMER19 MCH1 request
961 \arg DMA_REQUEST_TIMER19_MCH2: DMAMUX TIMER19 MCH2 request
962 \arg DMA_REQUEST_TIMER19_MCH3: DMAMUX TIMER19 MCH3 request
963 \arg DMA_REQUEST_TIMER20_CH0: DMAMUX TIMER20 CH0 request
964 \arg DMA_REQUEST_TIMER20_CH1: DMAMUX TIMER20 CH1 request
965 \arg DMA_REQUEST_TIMER20_CH2: DMAMUX TIMER20 CH2 request
966 \arg DMA_REQUEST_TIMER20_CH3: DMAMUX TIMER20 CH3 request
967 \arg DMA_REQUEST_TIMER20_TI: DMAMUX TIMER20 TI request
968 \arg DMA_REQUEST_TIMER20_UP: DMAMUX TIMER20 UP request
969 \arg DMA_REQUEST_TIMER20_CO: DMAMUX TIMER20 CO request
970 \arg DMA_REQUEST_TIMER20_MCH0: DMAMUX TIMER20 MCH0 request
971 \arg DMA_REQUEST_TIMER20_MCH1: DMAMUX TIMER20 MCH1 request
972 \arg DMA_REQUEST_TIMER20_MCH2: DMAMUX TIMER20 MCH2 request
973 \arg DMA_REQUEST_TIMER20_MCH3: DMAMUX TIMER20 MCH3 request
974 \param[out] none
975 \retval none
976 */
dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx,uint32_t id)977 void dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id)
978 {
979 DMAMUX_RM_CHXCFG(channelx) &= ~DMAMUX_RM_CHXCFG_MUXID;
980 DMAMUX_RM_CHXCFG(channelx) |= id;
981 }
982
983 /*!
984 \brief configure trigger input polarity
985 \param[in] channelx: specify which DMAMUX request generator channel is configured
986 only one parameter can be selected which is shown as below:
987 \arg DMAMUX_GENCHx(x=0..3)
988 \param[in] polarity: trigger input polarity
989 only one parameter can be selected which is shown as below:
990 \arg DMAMUX_GEN_NO_EVENT: no event detection
991 \arg DMAMUX_GEN_RISING: rising edge
992 \arg DMAMUX_GEN_FALLING: falling edge
993 \arg DMAMUX_GEN_RISING_FALLING: rising and falling edges
994 \param[out] none
995 \retval none
996 */
dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx,uint32_t polarity)997 void dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx, uint32_t polarity)
998 {
999 DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_RGTP;
1000 DMAMUX_RG_CHXCFG(channelx) |= polarity;
1001 }
1002
1003 /*!
1004 \brief configure number of DMA requests to be generated
1005 \param[in] channelx: specify which DMAMUX request generator channel is configured
1006 only one parameter can be selected which is shown as below:
1007 \arg DMAMUX_GENCHx(x=0..3)
1008 \param[in] number: DMA requests number to be generated
1009 only one parameter can be selected which is shown as below:
1010 \arg 1 - 32
1011 \param[out] none
1012 \retval none
1013 */
dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx,uint32_t number)1014 void dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx, uint32_t number)
1015 {
1016 DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_NBRG;
1017 DMAMUX_RG_CHXCFG(channelx) |= (number - 1U);
1018 }
1019
1020 /*!
1021 \brief configure trigger input identification
1022 \param[in] channelx: specify which DMAMUX request generator channel is configured
1023 only one parameter can be selected which is shown as below:
1024 \arg DMAMUX_GENCHx(x=0..3)
1025 \param[in] id: trigger input identification
1026 only one parameter can be selected which is shown as below:
1027 \arg DMAMUX_TRIGGER_EXTI0: trigger input is EXTI0
1028 \arg DMAMUX_TRIGGER_EXTI1: trigger input is EXTI1
1029 \arg DMAMUX_TRIGGER_EXTI2: trigger input is EXTI2
1030 \arg DMAMUX_TRIGGER_EXTI3: trigger input is EXTI3
1031 \arg DMAMUX_TRIGGER_EXTI4: trigger input is EXTI4
1032 \arg DMAMUX_TRIGGER_EXTI5: trigger input is EXTI5
1033 \arg DMAMUX_TRIGGER_EXTI6: trigger input is EXTI6
1034 \arg DMAMUX_TRIGGER_EXTI7: trigger input is EXTI7
1035 \arg DMAMUX_TRIGGER_EXTI8: trigger input is EXTI8
1036 \arg DMAMUX_TRIGGER_EXTI9: trigger input is EXTI9
1037 \arg DMAMUX_TRIGGER_EXTI10: trigger input is EXTI10
1038 \arg DMAMUX_TRIGGER_EXTI11: trigger input is EXTI11
1039 \arg DMAMUX_TRIGGER_EXTI12: trigger input is EXTI12
1040 \arg DMAMUX_TRIGGER_EXTI13: trigger input is EXTI13
1041 \arg DMAMUX_TRIGGER_EXTI14: trigger input is EXTI14
1042 \arg DMAMUX_TRIGGER_EXTI15: trigger input is EXTI15
1043 \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out0
1044 \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out1
1045 \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out2
1046 \arg DMAMUX_TRIGGER_EVTX_OUT0: trigger input is Evtx_out3
1047 \arg DMAMUX_TRIGGER_TIMER20_CH0_O: trigger input is TIMER20_CH0_O
1048 \param[out] none
1049 \retval none
1050 */
dmamux_trigger_id_config(dmamux_generator_channel_enum channelx,uint32_t id)1051 void dmamux_trigger_id_config(dmamux_generator_channel_enum channelx, uint32_t id)
1052 {
1053 DMAMUX_RG_CHXCFG(channelx) &= ~DMAMUX_RG_CHXCFG_TID;
1054 DMAMUX_RG_CHXCFG(channelx) |= id;
1055 }
1056
1057 /*!
1058 \brief get DMAMUX flag
1059 \param[in] flag: flag type
1060 only one parameter can be selected which is shown as below:
1061 \arg DMAMUX_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun flag
1062 \arg DMAMUX_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun flag
1063 \arg DMAMUX_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun flag
1064 \arg DMAMUX_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun flag
1065 \arg DMAMUX_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun flag
1066 \arg DMAMUX_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun flag
1067 \arg DMAMUX_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun flag
1068 \arg DMAMUX_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun flag
1069 \arg DMAMUX_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun flag
1070 \arg DMAMUX_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun flag
1071 \arg DMAMUX_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun flag
1072 \arg DMAMUX_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun flag
1073 \arg DMAMUX_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun flag
1074 \arg DMAMUX_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun flag
1075 \arg DMAMUX_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun flag
1076 \arg DMAMUX_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun flag
1077 \param[out] none
1078 \retval FlagStatus: SET or RESET
1079 */
dmamux_flag_get(dmamux_flag_enum flag)1080 FlagStatus dmamux_flag_get(dmamux_flag_enum flag)
1081 {
1082 FlagStatus reval;
1083
1084 if(0U != (DMAMUX_REG_VAL(flag) & BIT(DMAMUX_BIT_POS(flag)))) {
1085 reval = SET;
1086 } else {
1087 reval = RESET;
1088 }
1089
1090 return reval;
1091 }
1092
1093 /*!
1094 \brief clear DMAMUX flag
1095 \param[in] flag: flag type
1096 only one parameter can be selected which is shown as below:
1097 \arg DMAMUX_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun flag
1098 \arg DMAMUX_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun flag
1099 \arg DMAMUX_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun flag
1100 \arg DMAMUX_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun flag
1101 \arg DMAMUX_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun flag
1102 \arg DMAMUX_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun flag
1103 \arg DMAMUX_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun flag
1104 \arg DMAMUX_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun flag
1105 \arg DMAMUX_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun flag
1106 \arg DMAMUX_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun flag
1107 \arg DMAMUX_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun flag
1108 \arg DMAMUX_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun flag
1109 \arg DMAMUX_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun flag
1110 \arg DMAMUX_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun flag
1111 \arg DMAMUX_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun flag
1112 \arg DMAMUX_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun flag
1113 \param[out] none
1114 \retval none
1115 */
dmamux_flag_clear(dmamux_flag_enum flag)1116 void dmamux_flag_clear(dmamux_flag_enum flag)
1117 {
1118 DMAMUX_REG_VAL3(flag) = BIT(DMAMUX_BIT_POS(flag));
1119 }
1120
1121 /*!
1122 \brief enable DMAMUX interrupt
1123 \param[in] interrupt: specify which interrupt to enable
1124 only one parameter can be selected which is shown as below:
1125 \arg DMAMUX_INT_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt
1126 \arg DMAMUX_INT_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt
1127 \arg DMAMUX_INT_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt
1128 \arg DMAMUX_INT_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt
1129 \arg DMAMUX_INT_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt
1130 \arg DMAMUX_INT_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt
1131 \arg DMAMUX_INT_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt
1132 \arg DMAMUX_INT_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt
1133 \arg DMAMUX_INT_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt
1134 \arg DMAMUX_INT_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt
1135 \arg DMAMUX_INT_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt
1136 \arg DMAMUX_INT_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt
1137 \arg DMAMUX_INT_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt
1138 \arg DMAMUX_INT_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt
1139 \arg DMAMUX_INT_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt
1140 \arg DMAMUX_INT_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt
1141 \param[out] none
1142 \retval none
1143 */
dmamux_interrupt_enable(dmamux_interrupt_enum interrupt)1144 void dmamux_interrupt_enable(dmamux_interrupt_enum interrupt)
1145 {
1146 DMAMUX_REG_VAL(interrupt) |= BIT(DMAMUX_BIT_POS(interrupt));
1147 }
1148
1149 /*!
1150 \brief disable DMAMUX interrupt
1151 \param[in] interrupt: specify which interrupt to disable
1152 only one parameter can be selected which is shown as below:
1153 \arg DMAMUX_INT_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt
1154 \arg DMAMUX_INT_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt
1155 \arg DMAMUX_INT_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt
1156 \arg DMAMUX_INT_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt
1157 \arg DMAMUX_INT_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt
1158 \arg DMAMUX_INT_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt
1159 \arg DMAMUX_INT_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt
1160 \arg DMAMUX_INT_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt
1161 \arg DMAMUX_INT_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt
1162 \arg DMAMUX_INT_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt
1163 \arg DMAMUX_INT_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt
1164 \arg DMAMUX_INT_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt
1165 \arg DMAMUX_INT_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt
1166 \arg DMAMUX_INT_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt
1167 \arg DMAMUX_INT_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt
1168 \arg DMAMUX_INT_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt
1169 \param[out] none
1170 \retval none
1171 */
dmamux_interrupt_disable(dmamux_interrupt_enum interrupt)1172 void dmamux_interrupt_disable(dmamux_interrupt_enum interrupt)
1173 {
1174 DMAMUX_REG_VAL(interrupt) &= ~BIT(DMAMUX_BIT_POS(interrupt));
1175 }
1176
1177 /*!
1178 \brief get DMAMUX interrupt flag
1179 \param[in] int_flag: flag type
1180 only one parameter can be selected which is shown as below:
1181 \arg DMAMUX_INT_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag
1182 \arg DMAMUX_INT_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag
1183 \arg DMAMUX_INT_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag
1184 \arg DMAMUX_INT_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag
1185 \arg DMAMUX_INT_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag
1186 \arg DMAMUX_INT_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag
1187 \arg DMAMUX_INT_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag
1188 \arg DMAMUX_INT_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag
1189 \arg DMAMUX_INT_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag
1190 \arg DMAMUX_INT_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag
1191 \arg DMAMUX_INT_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag
1192 \arg DMAMUX_INT_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag
1193 \arg DMAMUX_INT_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt flag
1194 \arg DMAMUX_INT_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt flag
1195 \arg DMAMUX_INT_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt flag
1196 \arg DMAMUX_INT_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt flag
1197 \param[out] none
1198 \retval FlagStatus: SET or RESET
1199 */
dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag)1200 FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag)
1201 {
1202 FlagStatus reval;
1203 uint32_t intenable = 0U, flagstatus = 0U;
1204
1205 /* get the interrupt enable bit status */
1206 intenable = (DMAMUX_REG_VAL2(int_flag) & BIT(DMAMUX_BIT_POS2(int_flag)));
1207 /* get the corresponding flag bit status */
1208 flagstatus = (DMAMUX_REG_VAL(int_flag) & BIT(DMAMUX_BIT_POS(int_flag)));
1209
1210 if(flagstatus && intenable) {
1211 reval = SET;
1212 } else {
1213 reval = RESET;
1214 }
1215
1216 return reval;
1217 }
1218
1219 /*!
1220 \brief clear DMAMUX interrupt flag
1221 \param[in] int_flag: flag type
1222 only one parameter can be selected which is shown as below:
1223 \arg DMAMUX_INT_FLAG_MUXCH0_SO: DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag
1224 \arg DMAMUX_INT_FLAG_MUXCH1_SO: DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag
1225 \arg DMAMUX_INT_FLAG_MUXCH2_SO: DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag
1226 \arg DMAMUX_INT_FLAG_MUXCH3_SO: DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag
1227 \arg DMAMUX_INT_FLAG_MUXCH4_SO: DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag
1228 \arg DMAMUX_INT_FLAG_MUXCH5_SO: DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag
1229 \arg DMAMUX_INT_FLAG_MUXCH6_SO: DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag
1230 \arg DMAMUX_INT_FLAG_MUXCH7_SO: DMAMUX request multiplexer channel 7 synchronization overrun interrupt flag
1231 \arg DMAMUX_INT_FLAG_MUXCH8_SO: DMAMUX request multiplexer channel 8 synchronization overrun interrupt flag
1232 \arg DMAMUX_INT_FLAG_MUXCH9_SO: DMAMUX request multiplexer channel 9 synchronization overrun interrupt flag
1233 \arg DMAMUX_INT_FLAG_MUXCH10_SO: DMAMUX request multiplexer channel 10 synchronization overrun interrupt flag
1234 \arg DMAMUX_INT_FLAG_MUXCH11_SO: DMAMUX request multiplexer channel 11 synchronization overrun interrupt flag
1235 \arg DMAMUX_INT_FLAG_GENCH0_TO: DMAMUX request generator channel 0 trigger overrun interrupt flag
1236 \arg DMAMUX_INT_FLAG_GENCH1_TO: DMAMUX request generator channel 1 trigger overrun interrupt flag
1237 \arg DMAMUX_INT_FLAG_GENCH2_TO: DMAMUX request generator channel 2 trigger overrun interrupt flag
1238 \arg DMAMUX_INT_FLAG_GENCH3_TO: DMAMUX request generator channel 3 trigger overrun interrupt flag
1239 \param[out] none
1240 \retval none
1241 */
dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag)1242 void dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag)
1243 {
1244 DMAMUX_REG_VAL3(int_flag) = BIT(DMAMUX_BIT_POS(int_flag));
1245 }
1246
