1 /*! 2 \file gd32a50x_adc.h 3 \brief definitions for the ADC 4 5 \version 2022-01-30, V1.0.0, firmware for GD32A50x 6 */ 7 8 /* 9 Copyright (c) 2022, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32A50X_ADC_H 36 #define GD32A50X_ADC_H 37 38 #include "gd32a50x.h" 39 40 /* ADC definitions */ 41 #define ADC0 ADC_BASE 42 #define ADC1 (ADC_BASE + 0x00000400U) 43 44 /* registers definitions */ 45 #define ADC_STAT(adcx) REG32((adcx) + 0x00000000U) /*!< ADC status register */ 46 #define ADC_CTL0(adcx) REG32((adcx) + 0x00000004U) /*!< ADC control register 0 */ 47 #define ADC_CTL1(adcx) REG32((adcx) + 0x00000008U) /*!< ADC control register 1 */ 48 #define ADC_SAMPT0(adcx) REG32((adcx) + 0x0000000CU) /*!< ADC sampling time register 0 */ 49 #define ADC_SAMPT1(adcx) REG32((adcx) + 0x00000010U) /*!< ADC sampling time register 1 */ 50 #define ADC_IOFF0(adcx) REG32((adcx) + 0x00000014U) /*!< ADC inserted channel data offset register 0 */ 51 #define ADC_IOFF1(adcx) REG32((adcx) + 0x00000018U) /*!< ADC inserted channel data offset register 1 */ 52 #define ADC_IOFF2(adcx) REG32((adcx) + 0x0000001CU) /*!< ADC inserted channel data offset register 2 */ 53 #define ADC_IOFF3(adcx) REG32((adcx) + 0x00000020U) /*!< ADC inserted channel data offset register 3 */ 54 #define ADC_WDHT0(adcx) REG32((adcx) + 0x00000024U) /*!< ADC watchdog high threshold register 0 */ 55 #define ADC_WDLT0(adcx) REG32((adcx) + 0x00000028U) /*!< ADC watchdog low threshold register 0 */ 56 #define ADC_RSQ0(adcx) REG32((adcx) + 0x0000002CU) /*!< ADC regular sequence register 0 */ 57 #define ADC_RSQ1(adcx) REG32((adcx) + 0x00000030U) /*!< ADC regular sequence register 1 */ 58 #define ADC_RSQ2(adcx) REG32((adcx) + 0x00000034U) /*!< ADC regular sequence register 2 */ 59 #define ADC_ISQ(adcx) REG32((adcx) + 0x00000038U) /*!< ADC inserted sequence register */ 60 #define ADC_IDATA0(adcx) REG32((adcx) + 0x0000003CU) /*!< ADC inserted data register 0 */ 61 #define ADC_IDATA1(adcx) REG32((adcx) + 0x00000040U) /*!< ADC inserted data register 1 */ 62 #define ADC_IDATA2(adcx) REG32((adcx) + 0x00000044U) /*!< ADC inserted data register 2 */ 63 #define ADC_IDATA3(adcx) REG32((adcx) + 0x00000048U) /*!< ADC inserted data register 3 */ 64 #define ADC_RDATA(adcx) REG32((adcx) + 0x0000004CU) /*!< ADC regular data register */ 65 #define ADC_OVSAMPCTL(adcx) REG32((adcx) + 0x00000080U) /*!< ADC oversampling control register */ 66 #define ADC_WD1SR(adcx) REG32((adcx) + 0x000000A0U) /*!< ADC watchdog 1 channel selection register */ 67 #define ADC_WDT1(adcx) REG32((adcx) + 0x000000A8U) /*!< ADC watchdog threshold register 1 */ 68 69 /* bits definitions */ 70 /* ADC_STAT */ 71 #define ADC_STAT_WDE0 BIT(0) /*!< analog watchdog 0 event flag */ 72 #define ADC_STAT_EOC BIT(1) /*!< end of group conversion flag */ 73 #define ADC_STAT_EOIC BIT(2) /*!< end of inserted group conversion flag */ 74 #define ADC_STAT_STIC BIT(3) /*!< start flag of inserted channel group */ 75 #define ADC_STAT_STRC BIT(4) /*!< start flag of regular channel group */ 76 #define ADC_STAT_WDE1 BIT(30) /*!< analog watchdog 1 event flag */ 77 78 /* ADC_CTL0 */ 79 #define ADC_CTL0_WD0CHSEL BITS(0, 4) /*!< analog watchdog 0 channel select bits */ 80 #define ADC_CTL0_EOCIE BIT(5) /*!< interrupt enable for EOC */ 81 #define ADC_CTL0_WDE0IE BIT(6) /*!< analog watchdog 0 interrupt enable */ 82 #define ADC_CTL0_EOICIE BIT(7) /*!< interrupt enable for inserted channels */ 83 #define ADC_CTL0_SM BIT(8) /*!< scan mode */ 84 #define ADC_CTL0_WD0SC BIT(9) /*!< when in scan mode, analog watchdog 0 is effective on a single channel */ 85 #define ADC_CTL0_ICA BIT(10) /*!< automatic inserted group conversion */ 86 #define ADC_CTL0_DISRC BIT(11) /*!< discontinuous mode on regular channels */ 87 #define ADC_CTL0_DISIC BIT(12) /*!< discontinuous mode on inserted channels */ 88 #define ADC_CTL0_DISNUM BITS(13, 15) /*!< discontinuous mode channel count */ 89 #define ADC_CTL0_SYNCM BITS(16, 19) /*!< sync mode selection */ 90 #define ADC_CTL0_IWD0EN BIT(22) /*!< analog watchdog 0 enable on inserted channels */ 91 #define ADC_CTL0_RWD0EN BIT(23) /*!< analog watchdog 0 enable on regular channels */ 92 #define ADC_CTL0_WDE1IE BIT(30) /*!< analog watchdog 1 interrupt enable */ 93 94 /* ADC_CTL1 */ 95 #define ADC_CTL1_ADCON BIT(0) /*!< ADC converter on */ 96 #define ADC_CTL1_CTN BIT(1) /*!< continuous conversion */ 97 #define ADC_CTL1_CLB BIT(2) /*!< ADC calibration */ 98 #define ADC_CTL1_RSTCLB BIT(3) /*!< reset calibration */ 99 #define ADC_CTL1_DMA BIT(8) /*!< DMA request enable */ 100 #define ADC_CTL1_DAL BIT(11) /*!< data alignment */ 101 #define ADC_CTL1_ETSIC BIT(12) /*!< external trigger select for inserted channel */ 102 #define ADC_CTL1_ETEIC BIT(15) /*!< external trigger enable for inserted channel */ 103 #define ADC_CTL1_ETSRC BIT(17) /*!< external trigger select for regular channel */ 104 #define ADC_CTL1_ETERC BIT(20) /*!< external trigger enable for regular channel */ 105 #define ADC_CTL1_SWICST BIT(21) /*!< start on inserted channel */ 106 #define ADC_CTL1_SWRCST BIT(22) /*!< start on regular channel */ 107 #define ADC_CTL1_TSVEN BIT(23) /*!< channel 16 enable of ADC0 */ 108 #define ADC_CTL1_INREFEN BIT(24) /*!< channel 17 enable of ADC0 */ 109 110 /* ADC_SAMPTx x=0..1 */ 111 #define ADC_SAMPTX_SPTN BITS(0, 2) /*!< channel n(n=0..17) sample time selection */ 112 113 /* ADC_IOFFx x=0..3 */ 114 #define ADC_IOFFX_IOFF BITS(0, 11) /*!< data offset for inserted channel x */ 115 116 /* ADC_WDHT */ 117 #define ADC_WDHT0_WDHT0 BITS(0, 11) /*!< analog watchdog 0 high threshold */ 118 119 /* ADC_WDLT */ 120 #define ADC_WDLT0_WDLT0 BITS(0, 11) /*!< analog watchdog 0 low threshold */ 121 122 /* ADC_RSQx x=0..2 */ 123 #define ADC_RSQX_RSQN BITS(0, 4) /*!< n conversion in regular sequence */ 124 #define ADC_RSQ0_RL BITS(20, 23) /*!< regular channel sequence length */ 125 126 /* ADC_ISQ */ 127 #define ADC_ISQ_ISQN BITS(0, 4) /*!< n conversion in regular sequence */ 128 #define ADC_ISQ_IL BITS(20, 21) /*!< inserted sequence length */ 129 130 /* ADC_IDATAx x=0..3 */ 131 #define ADC_IDATAX_IDATAN BITS(0, 15) /*!< inserted channel x conversion data */ 132 133 /* ADC_RDATA */ 134 #define ADC_RDATA_RDATA BITS(0, 15) /*!< regular data */ 135 #define ADC_RDATA_ADC1RDTR BITS(16, 31) /*!< ADC1 regular channel data */ 136 137 /* ADC_OVSAMPCTL */ 138 #define ADC_OVSAMPCTL_OVSEN BIT(0) /*!< oversampling enable */ 139 #define ADC_OVSAMPCTL_OVSR BITS(2, 4) /*!< oversampling ratio */ 140 #define ADC_OVSAMPCTL_OVSS BITS(5, 8) /*!< oversampling shift */ 141 #define ADC_OVSAMPCTL_TOVS BIT(9) /*!< triggered oversampling */ 142 #define ADC_OVSAMPCTL_DRES BITS(12, 13) /*!< ADC resolution */ 143 144 /* ADC_WD1SR */ 145 #define ADC_WD1SR_AWD1CS BITS(0, 17) /*!< analog watchdog 1 channel selection */ 146 147 /* ADC_WDT1 */ 148 #define ADC_WDT1_WDLT1 BITS(0, 7) /*!< analog watchdog 1 low threshold */ 149 #define ADC_WDT1_WDHT1 BITS(16, 23) /*!< analog watchdog 1 high threshold */ 150 151 /* constants definitions */ 152 /* ADC flag definitions */ 153 #define ADC_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event flag */ 154 #define ADC_FLAG_EOC ADC_STAT_EOC /*!< end of conversion */ 155 #define ADC_FLAG_EOIC ADC_STAT_EOIC /*!< inserted channel end of conversion */ 156 #define ADC_FLAG_STIC ADC_STAT_STIC /*!< inserted channel start flag */ 157 #define ADC_FLAG_STRC ADC_STAT_STRC /*!< regular channel start flag */ 158 #define ADC_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event flag */ 159 160 /* configure number of conversions in discontinuous mode */ 161 #define CTL0_DISNUM(regval) (BITS(13, 15) & ((uint32_t)(regval) << 13)) /*!< write value to ADC_CTL0_DISNUM bit field */ 162 163 /* ADC special function definitions */ 164 #define ADC_SCAN_MODE ADC_CTL0_SM /*!< scan mode */ 165 #define ADC_INSERTED_CHANNEL_AUTO ADC_CTL0_ICA /*!< inserted channel group convert automatically */ 166 #define ADC_CONTINUOUS_MODE ADC_CTL1_CTN /*!< continuous mode */ 167 168 /* ADC synchronization mode */ 169 #define CTL0_SYNCM(regval) (BITS(16, 19) & ((uint32_t)(regval) << 16)) /*!< write value to ADC_CTL0_SYNCM bit field */ 170 #define ADC_MODE_FREE CTL0_SYNCM(0) /*!< all the ADCs work independently */ 171 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_PARALLEL CTL0_SYNCM(1) /*!< ADC0 and ADC1 work in combined regular parallel + inserted parallel mode */ 172 #define ADC_DAUL_REGULAL_PARALLEL_INSERTED_ROTATION CTL0_SYNCM(2) /*!< ADC0 and ADC1 work in combined regular parallel + trigger rotation mode */ 173 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(3) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up fast mode */ 174 #define ADC_DAUL_INSERTED_PARALLEL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(4) /*!< ADC0 and ADC1 work in combined inserted parallel + follow-up slow mode */ 175 #define ADC_DAUL_INSERTED_PARALLEL CTL0_SYNCM(5) /*!< ADC0 and ADC1 work in inserted parallel mode only */ 176 #define ADC_DAUL_REGULAL_PARALLEL CTL0_SYNCM(6) /*!< ADC0 and ADC1 work in regular parallel mode only */ 177 #define ADC_DAUL_REGULAL_FOLLOWUP_FAST CTL0_SYNCM(7) /*!< ADC0 and ADC1 work in follow-up fast mode only */ 178 #define ADC_DAUL_REGULAL_FOLLOWUP_SLOW CTL0_SYNCM(8) /*!< ADC0 and ADC1 work in follow-up slow mode only */ 179 #define ADC_DAUL_INSERTED_TRRIGGER_ROTATION CTL0_SYNCM(9) /*!< ADC0 and ADC1 work in trigger rotation mode only */ 180 181 /* ADC data alignment */ 182 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U) /*!< LSB alignment */ 183 #define ADC_DATAALIGN_LEFT ADC_CTL1_DAL /*!< MSB alignment */ 184 185 /* ADC external trigger select for regular channel */ 186 #define ADC0_1_EXTTRIG_REGULAR_TRIGSEL ((uint32_t)0x00000000U) /*!< TRIGSEL trigger */ 187 #define ADC0_1_EXTTRIG_REGULAR_NONE ADC_CTL1_ETSRC /*!< software trigger */ 188 189 /* ADC external trigger select for inserted channel */ 190 #define ADC0_1_EXTTRIG_INSERTED_TRIGSEL ((uint32_t)0x00000000U) /*!< TRIGSEL trigger */ 191 #define ADC0_1_EXTTRIG_INSERTED_NONE ADC_CTL1_ETSIC /*!< software trigger */ 192 193 /* ADC_SAMPTX register value */ 194 #define SAMPTX_SPT(regval) (BITS(0, 2) & ((uint32_t)(regval) << 0)) /*!< write value to ADC_SAMPTX_SPT bit field */ 195 #define ADC_SAMPLETIME_2POINT5 SAMPTX_SPT(0) /*!< 2.5 sampling cycles */ 196 #define ADC_SAMPLETIME_14POINT5 SAMPTX_SPT(1) /*!< 14.5 sampling cycles */ 197 #define ADC_SAMPLETIME_27POINT5 SAMPTX_SPT(2) /*!< 27.5 sampling cycles */ 198 #define ADC_SAMPLETIME_55POINT5 SAMPTX_SPT(3) /*!< 55.5 sampling cycles */ 199 #define ADC_SAMPLETIME_83POINT5 SAMPTX_SPT(4) /*!< 83.5 sampling cycles */ 200 #define ADC_SAMPLETIME_111POINT5 SAMPTX_SPT(5) /*!< 111.5 sampling cycles */ 201 #define ADC_SAMPLETIME_143POINT5 SAMPTX_SPT(6) /*!< 143.5 sampling cycles */ 202 #define ADC_SAMPLETIME_479POINT5 SAMPTX_SPT(7) /*!< 479.5 sampling cycles */ 203 204 /* ADC data offset for inserted channel x */ 205 #define IOFFX_IOFF(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 206 207 /* ADC analog watchdog 0 high threshold */ 208 #define WDHT0_WDHT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 209 210 /* ADC analog watchdog 0 low threshold */ 211 #define WDLT0_WDLT0(regval) (BITS(0, 11) & ((uint32_t)(regval) << 0)) 212 213 /* ADC analog watchdog 1 high threshold */ 214 #define WDT1_WDHT1(regval) (BITS(16, 23) & ((uint32_t)(regval) << 16)) 215 216 /* ADC analog watchdog 1 low threshold */ 217 #define WDT1_WDLT1(regval) (BITS(0, 7) & ((uint32_t)(regval) << 0)) 218 219 /* ADC regular channel group length */ 220 #define RSQ0_RL(regval) (BITS(20, 23) & ((uint32_t)(regval) << 20)) 221 222 /* ADC inserted channel group length */ 223 #define ISQ_IL(regval) (BITS(20, 21) & ((uint32_t)(regval) << 20)) 224 225 /* adc_ovsampctl register value */ 226 /* ADC resolution */ 227 #define OVSAMPCTL_DRES(regval) (BITS(12, 13) & ((uint32_t)(regval) << 12)) /*!< write value to ADC_OVSAMPCTL_DRES bit field */ 228 #define ADC_RESOLUTION_12B OVSAMPCTL_DRES(0) /*!< 12-bit ADC resolution */ 229 #define ADC_RESOLUTION_10B OVSAMPCTL_DRES(1) /*!< 10-bit ADC resolution */ 230 #define ADC_RESOLUTION_8B OVSAMPCTL_DRES(2) /*!< 8-bit ADC resolution */ 231 #define ADC_RESOLUTION_6B OVSAMPCTL_DRES(3) /*!< 6-bit ADC resolution */ 232 233 /* oversampling shift */ 234 #define OVSAMPCTL_OVSS(regval) (BITS(5, 8) & ((uint32_t)(regval) << 5)) /*!< write value to ADC_OVSAMPCTL_OVSS bit field */ 235 #define ADC_OVERSAMPLING_SHIFT_NONE OVSAMPCTL_OVSS(0) /*!< no oversampling shift */ 236 #define ADC_OVERSAMPLING_SHIFT_1B OVSAMPCTL_OVSS(1) /*!< 1-bit oversampling shift */ 237 #define ADC_OVERSAMPLING_SHIFT_2B OVSAMPCTL_OVSS(2) /*!< 2-bit oversampling shift */ 238 #define ADC_OVERSAMPLING_SHIFT_3B OVSAMPCTL_OVSS(3) /*!< 3-bit oversampling shift */ 239 #define ADC_OVERSAMPLING_SHIFT_4B OVSAMPCTL_OVSS(4) /*!< 4-bit oversampling shift */ 240 #define ADC_OVERSAMPLING_SHIFT_5B OVSAMPCTL_OVSS(5) /*!< 5-bit oversampling shift */ 241 #define ADC_OVERSAMPLING_SHIFT_6B OVSAMPCTL_OVSS(6) /*!< 6-bit oversampling shift */ 242 #define ADC_OVERSAMPLING_SHIFT_7B OVSAMPCTL_OVSS(7) /*!< 7-bit oversampling shift */ 243 #define ADC_OVERSAMPLING_SHIFT_8B OVSAMPCTL_OVSS(8) /*!< 8-bit oversampling shift */ 244 245 /* oversampling ratio */ 246 #define OVSAMPCTL_OVSR(regval) (BITS(2, 4) & ((uint32_t)(regval) << 2)) /*!< write value to ADC_OVSAMPCTL_OVSR bit field */ 247 #define ADC_OVERSAMPLING_RATIO_MUL2 OVSAMPCTL_OVSR(0) /*!< oversampling ratio multiple 2 */ 248 #define ADC_OVERSAMPLING_RATIO_MUL4 OVSAMPCTL_OVSR(1) /*!< oversampling ratio multiple 4 */ 249 #define ADC_OVERSAMPLING_RATIO_MUL8 OVSAMPCTL_OVSR(2) /*!< oversampling ratio multiple 8 */ 250 #define ADC_OVERSAMPLING_RATIO_MUL16 OVSAMPCTL_OVSR(3) /*!< oversampling ratio multiple 16 */ 251 #define ADC_OVERSAMPLING_RATIO_MUL32 OVSAMPCTL_OVSR(4) /*!< oversampling ratio multiple 32 */ 252 #define ADC_OVERSAMPLING_RATIO_MUL64 OVSAMPCTL_OVSR(5) /*!< oversampling ratio multiple 64 */ 253 #define ADC_OVERSAMPLING_RATIO_MUL128 OVSAMPCTL_OVSR(6) /*!< oversampling ratio multiple 128 */ 254 #define ADC_OVERSAMPLING_RATIO_MUL256 OVSAMPCTL_OVSR(7) /*!< oversampling ratio multiple 256 */ 255 256 /* triggered oversampling */ 257 #define ADC_OVERSAMPLING_ALL_CONVERT ((uint32_t)0x00000000U) /*!< all oversampled conversions for a channel are done consecutively after a trigger */ 258 #define ADC_OVERSAMPLING_ONE_CONVERT ADC_OVSAMPCTL_TOVS /*!< each oversampled conversion for a channel needs a trigger */ 259 260 /* ADC channel group definitions */ 261 #define ADC_REGULAR_CHANNEL ((uint8_t)0x01U) /*!< ADC regular channel group */ 262 #define ADC_INSERTED_CHANNEL ((uint8_t)0x02U) /*!< ADC inserted channel group */ 263 #define ADC_REGULAR_INSERTED_CHANNEL ((uint8_t)0x03U) /*!< both regular and inserted channel group */ 264 #define ADC_CHANNEL_DISCON_DISABLE ((uint8_t)0x04U) /*!< disable discontinuous mode of regular & inserted channel */ 265 266 /* ADC inserted channel definitions */ 267 #define ADC_INSERTED_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC inserted channel 0 */ 268 #define ADC_INSERTED_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC inserted channel 1 */ 269 #define ADC_INSERTED_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC inserted channel 2 */ 270 #define ADC_INSERTED_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC inserted channel 3 */ 271 272 /* ADC channel definitions */ 273 #define ADC_CHANNEL_0 ((uint8_t)0x00U) /*!< ADC channel 0 */ 274 #define ADC_CHANNEL_1 ((uint8_t)0x01U) /*!< ADC channel 1 */ 275 #define ADC_CHANNEL_2 ((uint8_t)0x02U) /*!< ADC channel 2 */ 276 #define ADC_CHANNEL_3 ((uint8_t)0x03U) /*!< ADC channel 3 */ 277 #define ADC_CHANNEL_4 ((uint8_t)0x04U) /*!< ADC channel 4 */ 278 #define ADC_CHANNEL_5 ((uint8_t)0x05U) /*!< ADC channel 5 */ 279 #define ADC_CHANNEL_6 ((uint8_t)0x06U) /*!< ADC channel 6 */ 280 #define ADC_CHANNEL_7 ((uint8_t)0x07U) /*!< ADC channel 7 */ 281 #define ADC_CHANNEL_8 ((uint8_t)0x08U) /*!< ADC channel 8 */ 282 #define ADC_CHANNEL_9 ((uint8_t)0x09U) /*!< ADC channel 9 */ 283 #define ADC_CHANNEL_10 ((uint8_t)0x0AU) /*!< ADC channel 10 */ 284 #define ADC_CHANNEL_11 ((uint8_t)0x0BU) /*!< ADC channel 11 */ 285 #define ADC_CHANNEL_12 ((uint8_t)0x0CU) /*!< ADC channel 12 */ 286 #define ADC_CHANNEL_13 ((uint8_t)0x0DU) /*!< ADC channel 13 */ 287 #define ADC_CHANNEL_14 ((uint8_t)0x0EU) /*!< ADC channel 14 */ 288 #define ADC_CHANNEL_15 ((uint8_t)0x0FU) /*!< ADC channel 15 */ 289 #define ADC_CHANNEL_16 ((uint8_t)0x10U) /*!< ADC channel 16 */ 290 #define ADC_CHANNEL_17 ((uint8_t)0x11U) /*!< ADC channel 17 */ 291 292 /* analog watchdog 1 channel selection for channel n(n=0..17) */ 293 #define ADC_AWD1_SELECTION_CHANNEL_0 ((uint32_t)0x00000001U) /*!< ADC channel 0 analog watchdog 1 selection */ 294 #define ADC_AWD1_SELECTION_CHANNEL_1 ((uint32_t)0x00000002U) /*!< ADC channel 1 analog watchdog 1 selection */ 295 #define ADC_AWD1_SELECTION_CHANNEL_2 ((uint32_t)0x00000004U) /*!< ADC channel 2 analog watchdog 1 selection */ 296 #define ADC_AWD1_SELECTION_CHANNEL_3 ((uint32_t)0x00000008U) /*!< ADC channel 3 analog watchdog 1 selection */ 297 #define ADC_AWD1_SELECTION_CHANNEL_4 ((uint32_t)0x00000010U) /*!< ADC channel 4 analog watchdog 1 selection */ 298 #define ADC_AWD1_SELECTION_CHANNEL_5 ((uint32_t)0x00000020U) /*!< ADC channel 5 analog watchdog 1 selection */ 299 #define ADC_AWD1_SELECTION_CHANNEL_6 ((uint32_t)0x00000040U) /*!< ADC channel 6 analog watchdog 1 selection */ 300 #define ADC_AWD1_SELECTION_CHANNEL_7 ((uint32_t)0x00000080U) /*!< ADC channel 7 analog watchdog 1 selection */ 301 #define ADC_AWD1_SELECTION_CHANNEL_8 ((uint32_t)0x00000100U) /*!< ADC channel 8 analog watchdog 1 selection */ 302 #define ADC_AWD1_SELECTION_CHANNEL_9 ((uint32_t)0x00000200U) /*!< ADC channel 9 analog watchdog 1 selection */ 303 #define ADC_AWD1_SELECTION_CHANNEL_10 ((uint32_t)0x00000400U) /*!< ADC channel 10 analog watchdog 1 selection */ 304 #define ADC_AWD1_SELECTION_CHANNEL_11 ((uint32_t)0x00000800U) /*!< ADC channel 11 analog watchdog 1 selection */ 305 #define ADC_AWD1_SELECTION_CHANNEL_12 ((uint32_t)0x00001000U) /*!< ADC channel 12 analog watchdog 1 selection */ 306 #define ADC_AWD1_SELECTION_CHANNEL_13 ((uint32_t)0x00002000U) /*!< ADC channel 13 analog watchdog 1 selection */ 307 #define ADC_AWD1_SELECTION_CHANNEL_14 ((uint32_t)0x00004000U) /*!< ADC channel 14 analog watchdog 1 selection */ 308 #define ADC_AWD1_SELECTION_CHANNEL_15 ((uint32_t)0x00008000U) /*!< ADC channel 15 analog watchdog 1 selection */ 309 #define ADC_AWD1_SELECTION_CHANNEL_16 ((uint32_t)0x00010000U) /*!< ADC channel 16 analog watchdog 1 selection */ 310 #define ADC_AWD1_SELECTION_CHANNEL_17 ((uint32_t)0x00020000U) /*!< ADC channel 17 analog watchdog 1 selection */ 311 #define ADC_AWD1_SELECTION_CHANNEL_ALL ((uint32_t)0x0003FFFFU) /*!< all ADC channels analog watchdog 1 selection */ 312 313 /* ADC interrupt */ 314 #define ADC_INT_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt */ 315 #define ADC_INT_EOC ADC_STAT_EOC /*!< end of group conversion interrupt */ 316 #define ADC_INT_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt */ 317 #define ADC_INT_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt */ 318 319 /* ADC interrupt flag */ 320 #define ADC_INT_FLAG_WDE0 ADC_STAT_WDE0 /*!< analog watchdog 0 event interrupt flag */ 321 #define ADC_INT_FLAG_EOC ADC_STAT_EOC /*!< end of group conversion interrupt flag */ 322 #define ADC_INT_FLAG_EOIC ADC_STAT_EOIC /*!< end of inserted group conversion interrupt flag */ 323 #define ADC_INT_FLAG_WDE1 ADC_STAT_WDE1 /*!< analog watchdog 1 event interrupt flag */ 324 325 /* function declarations */ 326 327 /* ADC deinitialization and initialization functions */ 328 /* reset ADC */ 329 void adc_deinit(uint32_t adc_periph); 330 /* enable ADC interface */ 331 void adc_enable(uint32_t adc_periph); 332 /* disable ADC interface */ 333 void adc_disable(uint32_t adc_periph); 334 335 /* ADC calibration and DMA functions */ 336 /* ADC calibration and reset calibration */ 337 void adc_calibration_enable(uint32_t adc_periph); 338 /* enable DMA request */ 339 void adc_dma_mode_enable(uint32_t adc_periph); 340 /* disable DMA request */ 341 void adc_dma_mode_disable(uint32_t adc_periph); 342 343 /* configure ADC temperature sensor and vrefint channel */ 344 /* enable the temperature sensor channel */ 345 void adc_tempsensor_enable(void); 346 /* disable the temperature sensor channel */ 347 void adc_tempsensor_disable(void); 348 /* enable vrefint channel */ 349 void adc_vrefint_enable(void); 350 /* disable vrefint channel */ 351 void adc_vrefint_disable(void); 352 353 /* ADC special function functions */ 354 /* configure ADC discontinuous mode */ 355 void adc_discontinuous_mode_config(uint32_t adc_periph , uint8_t adc_channel_group , uint8_t length); 356 /* configure the ADC0 mode */ 357 void adc_mode_config(uint32_t mode); 358 /* configure ADC special function */ 359 void adc_special_function_config(uint32_t adc_periph , uint32_t function , ControlStatus newvalue); 360 361 /* ADC channel configuration functions */ 362 /* configure ADC data alignment */ 363 void adc_data_alignment_config(uint32_t adc_periph , uint32_t data_alignment); 364 /* configure the length of regular channel group or inserted channel group */ 365 void adc_channel_length_config(uint32_t adc_periph , uint8_t adc_channel_group , uint32_t length); 366 /* configure ADC regular channel */ 367 void adc_regular_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); 368 /* configure ADC inserted channel */ 369 void adc_inserted_channel_config(uint32_t adc_periph , uint8_t rank , uint8_t adc_channel , uint32_t sample_time); 370 /* configure ADC inserted channel offset */ 371 void adc_inserted_channel_offset_config(uint32_t adc_periph , uint8_t inserted_channel , uint16_t offset); 372 373 374 /* ADC external trigger functions */ 375 /* configure ADC external trigger */ 376 void adc_external_trigger_config(uint32_t adc_periph, uint8_t adc_channel_group, ControlStatus newvalue); 377 /* configure ADC external trigger source */ 378 void adc_external_trigger_source_config(uint32_t adc_periph, uint8_t adc_channel_group, uint32_t external_trigger_source); 379 /* enable ADC software trigger */ 380 void adc_software_trigger_enable(uint32_t adc_periph , uint8_t adc_channel_group); 381 382 /* ADC data read functions */ 383 /* read ADC regular group data register */ 384 uint16_t adc_regular_data_read(uint32_t adc_periph); 385 /* read ADC inserted group data register */ 386 uint16_t adc_inserted_data_read(uint32_t adc_periph , uint8_t inserted_channel); 387 /* read the last ADC0 and ADC1 conversion result data in sync mode */ 388 uint32_t adc_sync_mode_convert_value_read(void); 389 390 /* ADC analog watchdog functions */ 391 /* configure ADC analog watchdog 0 single channel */ 392 void adc_watchdog0_single_channel_enable(uint32_t adc_periph, uint8_t adc_channel); 393 /* configure ADC analog watchdog 0 group channel */ 394 void adc_watchdog0_group_channel_enable(uint32_t adc_periph, uint8_t adc_channel_group); 395 /* disable ADC analog watchdog 0 */ 396 void adc_watchdog0_disable(uint32_t adc_periph); 397 /* configure ADC analog watchdog 1 channel */ 398 void adc_watchdog1_channel_config(uint32_t adc_periph, uint32_t adc_channel, ControlStatus newvalue); 399 /* disable ADC analog watchdog 1 */ 400 void adc_watchdog1_disable(uint32_t adc_periph); 401 /* configure ADC analog watchdog 0 threshold */ 402 void adc_watchdog0_threshold_config(uint32_t adc_periph , uint16_t low_threshold , uint16_t high_threshold); 403 /* configure ADC analog watchdog 1 threshold */ 404 void adc_watchdog1_threshold_config(uint32_t adc_periph , uint8_t low_threshold , uint8_t high_threshold); 405 406 /* ADC resolution and oversample functions */ 407 /* configure ADC resolution */ 408 void adc_resolution_config(uint32_t adc_periph , uint32_t resolution); 409 /* configure ADC oversample mode */ 410 void adc_oversample_mode_config(uint32_t adc_periph , uint32_t mode , uint16_t shift , uint8_t ratio); 411 /* enable ADC oversample mode */ 412 void adc_oversample_mode_enable(uint32_t adc_periph); 413 /* disable ADC oversample mode */ 414 void adc_oversample_mode_disable(uint32_t adc_periph); 415 416 /* flag and interrupt functions */ 417 /* get the ADC flag */ 418 FlagStatus adc_flag_get(uint32_t adc_periph , uint32_t flag); 419 /* clear the ADC flag */ 420 void adc_flag_clear(uint32_t adc_periph , uint32_t flag); 421 /* enable ADC interrupt */ 422 void adc_interrupt_enable(uint32_t adc_periph , uint32_t interrupt); 423 /* disable ADC interrupt */ 424 void adc_interrupt_disable(uint32_t adc_periph , uint32_t interrupt); 425 /* get the ADC interrupt */ 426 FlagStatus adc_interrupt_flag_get(uint32_t adc_periph , uint32_t int_flag); 427 /* clear the ADC flag */ 428 void adc_interrupt_flag_clear(uint32_t adc_periph , uint32_t int_flag); 429 430 #endif /* GD32A50X_ADC_H */ 431
