1 /*
2  * Copyright (c) 2022 Teslabs Engineering S.L.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
8 #define ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_
9 
10 /**
11  * Encode RCU register offset and configuration bit.
12  *
13  * - 0..5: bit number
14  * - 6..14: offset
15  * - 15: reserved
16  *
17  * @param reg RCU register name (expands to GD32_{reg}_OFFSET)
18  * @param bit Configuration bit
19  */
20 #define GD32_RESET_CONFIG(reg, bit) \
21 	(((GD32_ ## reg ## _OFFSET) << 6U) | (bit))
22 
23 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_RESET_GD32_RESET_COMMON_H_ */
24