1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #ifndef _FSL_MMDVSQ_H_
10 #define _FSL_MMDVSQ_H_
11
12 #include "fsl_common.h"
13
14 /*!
15 * @addtogroup mmdvsq
16 * @{
17 */
18
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 #define FSL_MMSVSQ_DRIVER_VERSION (MAKE_VERSION(2, 0, 2)) /*!< Version 2.0.2. */
27 /*@}*/
28
29 /*! @brief MMDVSQ execution status */
30 typedef enum _mmdvsq_execution_status
31 {
32 kMMDVSQ_IdleSquareRoot = 0x01U, /*!< MMDVSQ is idle; the last calculation was a square root */
33 kMMDVSQ_IdleDivide = 0x02U, /*!< MMDVSQ is idle; the last calculation was division */
34 kMMDVSQ_BusySquareRoot = 0x05U, /*!< MMDVSQ is busy processing a square root calculation */
35 kMMDVSQ_BusyDivide = 0x06U /*!< MMDVSQ is busy processing a division calculation */
36 } mmdvsq_execution_status_t;
37
38 /*! @brief MMDVSQ divide fast start select */
39 typedef enum _mmdvsq_fast_start_select
40 {
41 kMMDVSQ_EnableFastStart = 0U, /*!< Division operation is initiated by a write to the DSOR register */
42 kMMDVSQ_DisableFastStart =
43 1U /*!< Division operation is initiated by a write to CSR[SRT] = 1; normal start instead fast start */
44 } mmdvsq_fast_start_select_t;
45
46 /*******************************************************************************
47 * API
48 ******************************************************************************/
49
50 #if defined(__cplusplus)
51 extern "C" {
52 #endif /* __cplusplus */
53
54 /*!
55 * @name MMDVSQ functional Operation
56 * @{
57 */
58
59 /*!
60 * @brief Performs the MMDVSQ division operation and returns the remainder.
61 *
62 * @param base MMDVSQ peripheral address
63 * @param dividend Dividend value
64 * @param divisor Divisor value
65 * @param isUnsigned Mode of unsigned divide
66 * - true unsigned divide
67 * - false signed divide
68 *
69 */
70 int32_t MMDVSQ_GetDivideRemainder(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned);
71
72 /*!
73 * @brief Performs the MMDVSQ division operation and returns the quotient.
74 *
75 * @param base MMDVSQ peripheral address
76 * @param dividend Dividend value
77 * @param divisor Divisor value
78 * @param isUnsigned Mode of unsigned divide
79 * - true unsigned divide
80 * - false signed divide
81 *
82 */
83 int32_t MMDVSQ_GetDivideQuotient(MMDVSQ_Type *base, int32_t dividend, int32_t divisor, bool isUnsigned);
84
85 /*!
86 * @brief Performs the MMDVSQ square root operation.
87 *
88 * This function performs the MMDVSQ square root operation and returns the square root
89 * result of a given radicand value.
90 *
91 * @param base MMDVSQ peripheral address
92 * @param radicand Radicand value
93 *
94 */
95 uint16_t MMDVSQ_Sqrt(MMDVSQ_Type *base, uint32_t radicand);
96
97 /* @} */
98
99 /*!
100 * @name MMDVSQ status Operation
101 * @{
102 */
103
104 /*!
105 * @brief Gets the MMDVSQ execution status.
106 *
107 * This function checks the current MMDVSQ execution status of the combined
108 * CSR[BUSY, DIV, SQRT] indicators.
109 *
110 * @param base MMDVSQ peripheral address
111 *
112 * @return Current MMDVSQ execution status
113 */
MMDVSQ_GetExecutionStatus(MMDVSQ_Type * base)114 static inline mmdvsq_execution_status_t MMDVSQ_GetExecutionStatus(MMDVSQ_Type *base)
115 {
116 return (mmdvsq_execution_status_t)(base->CSR >> MMDVSQ_CSR_SQRT_SHIFT);
117 }
118
119 /*!
120 * @brief Configures MMDVSQ fast start mode.
121 *
122 * This function sets the MMDVSQ division fast start. The MMDVSQ supports two
123 * mechanisms for initiating a division operation. The default mechanism is
124 * a “fast start” where a write to the DSOR register begins the division.
125 * Alternatively, the start mechanism can begin after a write to the CSR
126 * register with CSR[SRT] set.
127 *
128 * @param base MMDVSQ peripheral address
129 * @param mode Mode of Divide-Fast-Start
130 * - kMmdvsqDivideFastStart = 0
131 * - kMmdvsqDivideNormalStart = 1
132 */
MMDVSQ_SetFastStartConfig(MMDVSQ_Type * base,mmdvsq_fast_start_select_t mode)133 static inline void MMDVSQ_SetFastStartConfig(MMDVSQ_Type *base, mmdvsq_fast_start_select_t mode)
134 {
135 if (mode)
136 {
137 base->CSR |= MMDVSQ_CSR_DFS_MASK;
138 }
139 else
140 {
141 base->CSR &= ~MMDVSQ_CSR_DFS_MASK;
142 }
143 }
144
145 /*!
146 * @brief Configures the MMDVSQ divide-by-zero mode.
147 *
148 * This function configures the MMDVSQ response to divide-by-zero
149 * calculations. If both CSR[DZ] and CSR[DZE] are set, then a subsequent read
150 * of the RES register is error-terminated to signal the processor of the
151 * attempted divide-by-zero. Otherwise, the register contents are returned.
152 *
153 * @param base MMDVSQ peripheral address
154 * @param isDivByZero Mode of Divide-By-Zero
155 * - kMmdvsqDivideByZeroDis = 0
156 * - kMmdvsqDivideByZeroEn = 1
157 */
MMDVSQ_SetDivideByZeroConfig(MMDVSQ_Type * base,bool isDivByZero)158 static inline void MMDVSQ_SetDivideByZeroConfig(MMDVSQ_Type *base, bool isDivByZero)
159 {
160 if (isDivByZero)
161 {
162 base->CSR |= MMDVSQ_CSR_DZE_MASK;
163 }
164 else
165 {
166 base->CSR &= ~MMDVSQ_CSR_DZE_MASK;
167 }
168 }
169
170 /* @} */
171
172 #if defined(__cplusplus)
173 }
174
175 #endif /* __cplusplus */
176
177 /*! @}*/
178
179 #endif /* _FSL_MMDVSQ_H_ */
180
