1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 #ifndef _FSL_LPTMR_H_
9 #define _FSL_LPTMR_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup lptmr
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21
22 /*! @name Driver version */
23 /*@{*/
24 #define FSL_LPTMR_DRIVER_VERSION (MAKE_VERSION(2, 0, 1)) /*!< Version 2.0.1 */
25 /*@}*/
26
27 /*! @brief LPTMR pin selection used in pulse counter mode.*/
28 typedef enum _lptmr_pin_select
29 {
30 kLPTMR_PinSelectInput_0 = 0x0U, /*!< Pulse counter input 0 is selected */
31 kLPTMR_PinSelectInput_1 = 0x1U, /*!< Pulse counter input 1 is selected */
32 kLPTMR_PinSelectInput_2 = 0x2U, /*!< Pulse counter input 2 is selected */
33 kLPTMR_PinSelectInput_3 = 0x3U /*!< Pulse counter input 3 is selected */
34 } lptmr_pin_select_t;
35
36 /*! @brief LPTMR pin polarity used in pulse counter mode.*/
37 typedef enum _lptmr_pin_polarity
38 {
39 kLPTMR_PinPolarityActiveHigh = 0x0U, /*!< Pulse Counter input source is active-high */
40 kLPTMR_PinPolarityActiveLow = 0x1U /*!< Pulse Counter input source is active-low */
41 } lptmr_pin_polarity_t;
42
43 /*! @brief LPTMR timer mode selection.*/
44 typedef enum _lptmr_timer_mode
45 {
46 kLPTMR_TimerModeTimeCounter = 0x0U, /*!< Time Counter mode */
47 kLPTMR_TimerModePulseCounter = 0x1U /*!< Pulse Counter mode */
48 } lptmr_timer_mode_t;
49
50 /*! @brief LPTMR prescaler/glitch filter values*/
51 typedef enum _lptmr_prescaler_glitch_value
52 {
53 kLPTMR_Prescale_Glitch_0 = 0x0U, /*!< Prescaler divide 2, glitch filter does not support this setting */
54 kLPTMR_Prescale_Glitch_1 = 0x1U, /*!< Prescaler divide 4, glitch filter 2 */
55 kLPTMR_Prescale_Glitch_2 = 0x2U, /*!< Prescaler divide 8, glitch filter 4 */
56 kLPTMR_Prescale_Glitch_3 = 0x3U, /*!< Prescaler divide 16, glitch filter 8 */
57 kLPTMR_Prescale_Glitch_4 = 0x4U, /*!< Prescaler divide 32, glitch filter 16 */
58 kLPTMR_Prescale_Glitch_5 = 0x5U, /*!< Prescaler divide 64, glitch filter 32 */
59 kLPTMR_Prescale_Glitch_6 = 0x6U, /*!< Prescaler divide 128, glitch filter 64 */
60 kLPTMR_Prescale_Glitch_7 = 0x7U, /*!< Prescaler divide 256, glitch filter 128 */
61 kLPTMR_Prescale_Glitch_8 = 0x8U, /*!< Prescaler divide 512, glitch filter 256 */
62 kLPTMR_Prescale_Glitch_9 = 0x9U, /*!< Prescaler divide 1024, glitch filter 512*/
63 kLPTMR_Prescale_Glitch_10 = 0xAU, /*!< Prescaler divide 2048 glitch filter 1024 */
64 kLPTMR_Prescale_Glitch_11 = 0xBU, /*!< Prescaler divide 4096, glitch filter 2048 */
65 kLPTMR_Prescale_Glitch_12 = 0xCU, /*!< Prescaler divide 8192, glitch filter 4096 */
66 kLPTMR_Prescale_Glitch_13 = 0xDU, /*!< Prescaler divide 16384, glitch filter 8192 */
67 kLPTMR_Prescale_Glitch_14 = 0xEU, /*!< Prescaler divide 32768, glitch filter 16384 */
68 kLPTMR_Prescale_Glitch_15 = 0xFU /*!< Prescaler divide 65536, glitch filter 32768 */
69 } lptmr_prescaler_glitch_value_t;
70
71 /*!
72 * @brief LPTMR prescaler/glitch filter clock select.
73 * @note Clock connections are SoC-specific
74 */
75 typedef enum _lptmr_prescaler_clock_select
76 {
77 kLPTMR_PrescalerClock_0 = 0x0U, /*!< Prescaler/glitch filter clock 0 selected. */
78 kLPTMR_PrescalerClock_1 = 0x1U, /*!< Prescaler/glitch filter clock 1 selected. */
79 kLPTMR_PrescalerClock_2 = 0x2U, /*!< Prescaler/glitch filter clock 2 selected. */
80 kLPTMR_PrescalerClock_3 = 0x3U, /*!< Prescaler/glitch filter clock 3 selected. */
81 } lptmr_prescaler_clock_select_t;
82
83 /*! @brief List of the LPTMR interrupts */
84 typedef enum _lptmr_interrupt_enable
85 {
86 kLPTMR_TimerInterruptEnable = LPTMR_CSR_TIE_MASK, /*!< Timer interrupt enable */
87 } lptmr_interrupt_enable_t;
88
89 /*! @brief List of the LPTMR status flags */
90 typedef enum _lptmr_status_flags
91 {
92 kLPTMR_TimerCompareFlag = LPTMR_CSR_TCF_MASK, /*!< Timer compare flag */
93 } lptmr_status_flags_t;
94
95 /*!
96 * @brief LPTMR config structure
97 *
98 * This structure holds the configuration settings for the LPTMR peripheral. To initialize this
99 * structure to reasonable defaults, call the LPTMR_GetDefaultConfig() function and pass a
100 * pointer to your configuration structure instance.
101 *
102 * The configuration struct can be made constant so it resides in flash.
103 */
104 typedef struct _lptmr_config
105 {
106 lptmr_timer_mode_t timerMode; /*!< Time counter mode or pulse counter mode */
107 lptmr_pin_select_t pinSelect; /*!< LPTMR pulse input pin select; used only in pulse counter mode */
108 lptmr_pin_polarity_t pinPolarity; /*!< LPTMR pulse input pin polarity; used only in pulse counter mode */
109 bool enableFreeRunning; /*!< True: enable free running, counter is reset on overflow
110 False: counter is reset when the compare flag is set */
111 bool bypassPrescaler; /*!< True: bypass prescaler; false: use clock from prescaler */
112 lptmr_prescaler_clock_select_t prescalerClockSource; /*!< LPTMR clock source */
113 lptmr_prescaler_glitch_value_t value; /*!< Prescaler or glitch filter value */
114 } lptmr_config_t;
115
116 /*******************************************************************************
117 * API
118 ******************************************************************************/
119
120 #if defined(__cplusplus)
121 extern "C" {
122 #endif
123
124 /*!
125 * @name Initialization and deinitialization
126 * @{
127 */
128
129 /*!
130 * @brief Ungates the LPTMR clock and configures the peripheral for a basic operation.
131 *
132 * @note This API should be called at the beginning of the application using the LPTMR driver.
133 *
134 * @param base LPTMR peripheral base address
135 * @param config A pointer to the LPTMR configuration structure.
136 */
137 void LPTMR_Init(LPTMR_Type *base, const lptmr_config_t *config);
138
139 /*!
140 * @brief Gates the LPTMR clock.
141 *
142 * @param base LPTMR peripheral base address
143 */
144 void LPTMR_Deinit(LPTMR_Type *base);
145
146 /*!
147 * @brief Fills in the LPTMR configuration structure with default settings.
148 *
149 * The default values are as follows.
150 * @code
151 * config->timerMode = kLPTMR_TimerModeTimeCounter;
152 * config->pinSelect = kLPTMR_PinSelectInput_0;
153 * config->pinPolarity = kLPTMR_PinPolarityActiveHigh;
154 * config->enableFreeRunning = false;
155 * config->bypassPrescaler = true;
156 * config->prescalerClockSource = kLPTMR_PrescalerClock_1;
157 * config->value = kLPTMR_Prescale_Glitch_0;
158 * @endcode
159 * @param config A pointer to the LPTMR configuration structure.
160 */
161 void LPTMR_GetDefaultConfig(lptmr_config_t *config);
162
163 /*! @}*/
164
165 /*!
166 * @name Interrupt Interface
167 * @{
168 */
169
170 /*!
171 * @brief Enables the selected LPTMR interrupts.
172 *
173 * @param base LPTMR peripheral base address
174 * @param mask The interrupts to enable. This is a logical OR of members of the
175 * enumeration ::lptmr_interrupt_enable_t
176 */
LPTMR_EnableInterrupts(LPTMR_Type * base,uint32_t mask)177 static inline void LPTMR_EnableInterrupts(LPTMR_Type *base, uint32_t mask)
178 {
179 uint32_t reg = base->CSR;
180
181 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
182 reg &= ~(LPTMR_CSR_TCF_MASK);
183 reg |= mask;
184 base->CSR = reg;
185 }
186
187 /*!
188 * @brief Disables the selected LPTMR interrupts.
189 *
190 * @param base LPTMR peripheral base address
191 * @param mask The interrupts to disable. This is a logical OR of members of the
192 * enumeration ::lptmr_interrupt_enable_t.
193 */
LPTMR_DisableInterrupts(LPTMR_Type * base,uint32_t mask)194 static inline void LPTMR_DisableInterrupts(LPTMR_Type *base, uint32_t mask)
195 {
196 uint32_t reg = base->CSR;
197
198 /* Clear the TCF bit so that we don't clear this w1c bit when writing back */
199 reg &= ~(LPTMR_CSR_TCF_MASK);
200 reg &= ~mask;
201 base->CSR = reg;
202 }
203
204 /*!
205 * @brief Gets the enabled LPTMR interrupts.
206 *
207 * @param base LPTMR peripheral base address
208 *
209 * @return The enabled interrupts. This is the logical OR of members of the
210 * enumeration ::lptmr_interrupt_enable_t
211 */
LPTMR_GetEnabledInterrupts(LPTMR_Type * base)212 static inline uint32_t LPTMR_GetEnabledInterrupts(LPTMR_Type *base)
213 {
214 return (base->CSR & LPTMR_CSR_TIE_MASK);
215 }
216
217 /*! @}*/
218
219 #if defined(FSL_FEATURE_LPTMR_HAS_CSR_TDRE) && (FSL_FEATURE_LPTMR_HAS_CSR_TDRE)
220 /*!
221 * @brief Enable or disable timer DMA request
222 *
223 * @param base base LPTMR peripheral base address
224 * @param enable Switcher of timer DMA feature. "true" means to enable, "false" means to disable.
225 */
LPTMR_EnableTimerDMA(LPTMR_Type * base,bool enable)226 static inline void LPTMR_EnableTimerDMA(LPTMR_Type *base, bool enable)
227 {
228 if(enable)
229 {
230 base->CSR |= LPTMR_CSR_TDRE_MASK;
231 }
232 else
233 {
234 base->CSR &= ~(LPTMR_CSR_TDRE_MASK);
235 }
236 }
237 #endif /* FSL_FEATURE_LPTMR_HAS_CSR_TDRE */
238
239 /*!
240 * @name Status Interface
241 * @{
242 */
243
244 /*!
245 * @brief Gets the LPTMR status flags.
246 *
247 * @param base LPTMR peripheral base address
248 *
249 * @return The status flags. This is the logical OR of members of the
250 * enumeration ::lptmr_status_flags_t
251 */
LPTMR_GetStatusFlags(LPTMR_Type * base)252 static inline uint32_t LPTMR_GetStatusFlags(LPTMR_Type *base)
253 {
254 return (base->CSR & LPTMR_CSR_TCF_MASK);
255 }
256
257 /*!
258 * @brief Clears the LPTMR status flags.
259 *
260 * @param base LPTMR peripheral base address
261 * @param mask The status flags to clear. This is a logical OR of members of the
262 * enumeration ::lptmr_status_flags_t.
263 */
LPTMR_ClearStatusFlags(LPTMR_Type * base,uint32_t mask)264 static inline void LPTMR_ClearStatusFlags(LPTMR_Type *base, uint32_t mask)
265 {
266 base->CSR |= mask;
267 }
268
269 /*! @}*/
270
271 /*!
272 * @name Read and write the timer period
273 * @{
274 */
275
276 /*!
277 * @brief Sets the timer period in units of count.
278 *
279 * Timers counts from 0 until it equals the count value set here. The count value is written to
280 * the CMR register.
281 *
282 * @note
283 * 1. The TCF flag is set with the CNR equals the count provided here and then increments.
284 * 2. Call the utility macros provided in the fsl_common.h to convert to ticks.
285 *
286 * @param base LPTMR peripheral base address
287 * @param ticks A timer period in units of ticks, which should be equal or greater than 1.
288 */
LPTMR_SetTimerPeriod(LPTMR_Type * base,uint32_t ticks)289 static inline void LPTMR_SetTimerPeriod(LPTMR_Type *base, uint32_t ticks)
290 {
291 assert(ticks > 0);
292 base->CMR = ticks - 1;
293 }
294
295 /*!
296 * @brief Reads the current timer counting value.
297 *
298 * This function returns the real-time timer counting value in a range from 0 to a
299 * timer period.
300 *
301 * @note Call the utility macros provided in the fsl_common.h to convert ticks to usec or msec.
302 *
303 * @param base LPTMR peripheral base address
304 *
305 * @return The current counter value in ticks
306 */
LPTMR_GetCurrentTimerCount(LPTMR_Type * base)307 static inline uint32_t LPTMR_GetCurrentTimerCount(LPTMR_Type *base)
308 {
309 /* Must first write any value to the CNR. This synchronizes and registers the current value
310 * of the CNR into a temporary register which can then be read
311 */
312 base->CNR = 0U;
313 return (uint32_t)((base->CNR & LPTMR_CNR_COUNTER_MASK) >> LPTMR_CNR_COUNTER_SHIFT);
314 }
315
316 /*! @}*/
317
318 /*!
319 * @name Timer Start and Stop
320 * @{
321 */
322
323 /*!
324 * @brief Starts the timer.
325 *
326 * After calling this function, the timer counts up to the CMR register value.
327 * Each time the timer reaches the CMR value and then increments, it generates a
328 * trigger pulse and sets the timeout interrupt flag. An interrupt is also
329 * triggered if the timer interrupt is enabled.
330 *
331 * @param base LPTMR peripheral base address
332 */
LPTMR_StartTimer(LPTMR_Type * base)333 static inline void LPTMR_StartTimer(LPTMR_Type *base)
334 {
335 uint32_t reg = base->CSR;
336
337 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
338 reg &= ~(LPTMR_CSR_TCF_MASK);
339 reg |= LPTMR_CSR_TEN_MASK;
340 base->CSR = reg;
341 }
342
343 /*!
344 * @brief Stops the timer.
345 *
346 * This function stops the timer and resets the timer's counter register.
347 *
348 * @param base LPTMR peripheral base address
349 */
LPTMR_StopTimer(LPTMR_Type * base)350 static inline void LPTMR_StopTimer(LPTMR_Type *base)
351 {
352 uint32_t reg = base->CSR;
353
354 /* Clear the TCF bit to avoid clearing the w1c bit when writing back. */
355 reg &= ~(LPTMR_CSR_TCF_MASK);
356 reg &= ~LPTMR_CSR_TEN_MASK;
357 base->CSR = reg;
358 }
359
360 /*! @}*/
361
362 #if defined(__cplusplus)
363 }
364 #endif
365
366 /*! @}*/
367
368 #endif /* _FSL_LPTMR_H_ */
369
